MIPS: Octeon: Setup irq_domains for interrupts.
Create two domains. One for the GPIO lines, and the other for on-chip sources. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: devicetree-discuss@lists.ozlabs.org Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Rob Herring <rob.herring@calxeda.com> Cc: linux-kernel@vger.kernel.org Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/3936/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney
Ralf Baechle
Родитель
7ed1815296
Коммит
a0c16582b5
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@ -3,14 +3,17 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004-2008, 2009, 2010, 2011 Cavium Networks
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* Copyright (C) 2004-2012 Cavium, Inc.
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*/
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/bitops.h>
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#include <linux/percpu.h>
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#include <linux/slab.h>
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#include <linux/irq.h>
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#include <linux/smp.h>
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#include <linux/of.h>
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#include <asm/octeon/octeon.h>
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@ -42,9 +45,9 @@ struct octeon_core_chip_data {
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static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES];
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static void __init octeon_irq_set_ciu_mapping(int irq, int line, int bit,
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struct irq_chip *chip,
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irq_flow_handler_t handler)
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static void octeon_irq_set_ciu_mapping(int irq, int line, int bit,
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struct irq_chip *chip,
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irq_flow_handler_t handler)
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{
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union octeon_ciu_chip_data cd;
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@ -847,6 +850,178 @@ static struct irq_chip octeon_irq_chip_ciu_wd = {
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.irq_mask = octeon_irq_dummy_mask,
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};
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static bool octeon_irq_ciu_is_edge(unsigned int line, unsigned int bit)
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{
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bool edge = false;
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if (line == 0)
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switch (bit) {
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case 48 ... 49: /* GMX DRP */
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case 50: /* IPD_DRP */
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case 52 ... 55: /* Timers */
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case 58: /* MPI */
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edge = true;
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break;
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default:
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break;
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}
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else /* line == 1 */
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switch (bit) {
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case 47: /* PTP */
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edge = true;
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break;
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default:
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break;
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}
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return edge;
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}
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struct octeon_irq_gpio_domain_data {
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unsigned int base_hwirq;
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};
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static int octeon_irq_gpio_xlat(struct irq_domain *d,
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struct device_node *node,
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const u32 *intspec,
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unsigned int intsize,
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unsigned long *out_hwirq,
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unsigned int *out_type)
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{
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unsigned int type;
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unsigned int pin;
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unsigned int trigger;
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struct octeon_irq_gpio_domain_data *gpiod;
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if (d->of_node != node)
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return -EINVAL;
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if (intsize < 2)
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return -EINVAL;
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pin = intspec[0];
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if (pin >= 16)
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return -EINVAL;
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trigger = intspec[1];
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switch (trigger) {
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case 1:
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type = IRQ_TYPE_EDGE_RISING;
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break;
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case 2:
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type = IRQ_TYPE_EDGE_FALLING;
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break;
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case 4:
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type = IRQ_TYPE_LEVEL_HIGH;
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break;
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case 8:
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type = IRQ_TYPE_LEVEL_LOW;
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break;
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default:
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pr_err("Error: (%s) Invalid irq trigger specification: %x\n",
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node->name,
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trigger);
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type = IRQ_TYPE_LEVEL_LOW;
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break;
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}
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*out_type = type;
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gpiod = d->host_data;
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*out_hwirq = gpiod->base_hwirq + pin;
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return 0;
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}
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static int octeon_irq_ciu_xlat(struct irq_domain *d,
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struct device_node *node,
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const u32 *intspec,
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unsigned int intsize,
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unsigned long *out_hwirq,
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unsigned int *out_type)
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{
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unsigned int ciu, bit;
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ciu = intspec[0];
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bit = intspec[1];
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if (ciu > 1 || bit > 63)
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return -EINVAL;
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/* These are the GPIO lines */
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if (ciu == 0 && bit >= 16 && bit < 32)
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return -EINVAL;
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*out_hwirq = (ciu << 6) | bit;
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*out_type = 0;
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return 0;
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}
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static struct irq_chip *octeon_irq_ciu_chip;
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static struct irq_chip *octeon_irq_gpio_chip;
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static bool octeon_irq_virq_in_range(unsigned int virq)
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{
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/* We cannot let it overflow the mapping array. */
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if (virq < (1ul << 8 * sizeof(octeon_irq_ciu_to_irq[0][0])))
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return true;
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WARN_ONCE(true, "virq out of range %u.\n", virq);
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return false;
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}
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static int octeon_irq_ciu_map(struct irq_domain *d,
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unsigned int virq, irq_hw_number_t hw)
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{
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unsigned int line = hw >> 6;
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unsigned int bit = hw & 63;
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if (!octeon_irq_virq_in_range(virq))
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return -EINVAL;
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if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0)
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return -EINVAL;
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if (octeon_irq_ciu_is_edge(line, bit))
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octeon_irq_set_ciu_mapping(virq, line, bit,
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octeon_irq_ciu_chip,
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handle_edge_irq);
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else
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octeon_irq_set_ciu_mapping(virq, line, bit,
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octeon_irq_ciu_chip,
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handle_level_irq);
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return 0;
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}
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static int octeon_irq_gpio_map(struct irq_domain *d,
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unsigned int virq, irq_hw_number_t hw)
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{
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unsigned int line = hw >> 6;
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unsigned int bit = hw & 63;
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if (!octeon_irq_virq_in_range(virq))
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return -EINVAL;
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if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0)
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return -EINVAL;
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octeon_irq_set_ciu_mapping(virq, line, bit,
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octeon_irq_gpio_chip,
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octeon_irq_handle_gpio);
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return 0;
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}
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static struct irq_domain_ops octeon_irq_domain_ciu_ops = {
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.map = octeon_irq_ciu_map,
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.xlate = octeon_irq_ciu_xlat,
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};
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static struct irq_domain_ops octeon_irq_domain_gpio_ops = {
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.map = octeon_irq_gpio_map,
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.xlate = octeon_irq_gpio_xlat,
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};
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static void octeon_irq_ip2_v1(void)
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{
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const unsigned long core_id = cvmx_get_core_num();
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@ -972,7 +1147,8 @@ static void __init octeon_irq_init_ciu(void)
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struct irq_chip *chip;
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struct irq_chip *chip_mbox;
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struct irq_chip *chip_wd;
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struct irq_chip *chip_gpio;
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struct device_node *gpio_node;
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struct device_node *ciu_node;
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octeon_irq_init_ciu_percpu();
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octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu;
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@ -986,15 +1162,16 @@ static void __init octeon_irq_init_ciu(void)
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chip = &octeon_irq_chip_ciu_v2;
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chip_mbox = &octeon_irq_chip_ciu_mbox_v2;
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chip_wd = &octeon_irq_chip_ciu_wd_v2;
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chip_gpio = &octeon_irq_chip_ciu_gpio_v2;
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octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio_v2;
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} else {
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octeon_irq_ip2 = octeon_irq_ip2_v1;
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octeon_irq_ip3 = octeon_irq_ip3_v1;
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chip = &octeon_irq_chip_ciu;
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chip_mbox = &octeon_irq_chip_ciu_mbox;
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chip_wd = &octeon_irq_chip_ciu_wd;
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chip_gpio = &octeon_irq_chip_ciu_gpio;
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octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio;
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}
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octeon_irq_ciu_chip = chip;
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octeon_irq_ip4 = octeon_irq_ip4_mask;
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/* Mips internal */
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@ -1003,8 +1180,6 @@ static void __init octeon_irq_init_ciu(void)
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/* CIU_0 */
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for (i = 0; i < 16; i++)
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octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq);
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for (i = 0; i < 16; i++)
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octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip_gpio, octeon_irq_handle_gpio);
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octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq);
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octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq);
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@ -1035,6 +1210,28 @@ static void __init octeon_irq_init_ciu(void)
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octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq);
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octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII1, 1, 18, chip, handle_level_irq);
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gpio_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-gpio");
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if (gpio_node) {
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struct octeon_irq_gpio_domain_data *gpiod;
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gpiod = kzalloc(sizeof(*gpiod), GFP_KERNEL);
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if (gpiod) {
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/* gpio domain host_data is the base hwirq number. */
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gpiod->base_hwirq = 16;
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irq_domain_add_linear(gpio_node, 16, &octeon_irq_domain_gpio_ops, gpiod);
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of_node_put(gpio_node);
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} else
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pr_warn("Cannot allocate memory for GPIO irq_domain.\n");
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} else
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pr_warn("Cannot find device node for cavium,octeon-3860-gpio.\n");
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ciu_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-ciu");
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if (ciu_node) {
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irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu_ops, NULL);
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of_node_put(ciu_node);
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} else
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pr_warn("Cannot find device node for cavium,octeon-3860-ciu.\n");
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/* Enable the CIU lines */
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set_c0_status(STATUSF_IP3 | STATUSF_IP2);
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clear_c0_status(STATUSF_IP4);
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