PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code
Most DWC drivers use the common register resource names "dbi", "dbi2", and "addr_space", so let's move their setup into the DWC common code. This means 'dbi_base' in particular is setup later, but it looks like no drivers touch DBI registers before dw_pcie_host_init or dw_pcie_ep_init. Link: https://lore.kernel.org/r/20201105211159.1814485-4-robh@kernel.org Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Minghuan Lian <minghuan.Lian@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Roy Zang <roy.zang@nxp.com> Cc: Jonathan Chocron <jonnyc@amazon.com> Cc: Jesper Nilsson <jesper.nilsson@axis.com> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Cc: Xiaowei Song <songxiaowei@hisilicon.com> Cc: Binghui Wang <wangbinghui@hisilicon.com> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Stanimir Varbanov <svarbanov@mm-sol.com> Cc: Pratyush Anand <pratyush.anand@gmail.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: linux-omap@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-arm-kernel@axis.com Cc: linux-arm-msm@vger.kernel.org Cc: linux-tegra@vger.kernel.org
This commit is contained in:
Родитель
1d567aac46
Коммит
a0fd361db8
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@ -578,7 +578,6 @@ static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
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{
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int ret;
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struct dw_pcie_ep *ep;
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struct resource *res;
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struct device *dev = &pdev->dev;
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struct dw_pcie *pci = dra7xx->pci;
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@ -594,13 +593,6 @@ static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
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if (IS_ERR(pci->dbi_base2))
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return PTR_ERR(pci->dbi_base2);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
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if (!res)
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return -EINVAL;
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ep->phys_base = res->start;
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ep->addr_size = resource_size(res);
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ret = dw_pcie_ep_init(ep);
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if (ret) {
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dev_err(dev, "failed to initialize endpoint\n");
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@ -977,33 +977,6 @@ static const struct dw_pcie_ep_ops ks_pcie_am654_ep_ops = {
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.get_features = &ks_pcie_am654_get_features,
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};
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static int __init ks_pcie_add_pcie_ep(struct keystone_pcie *ks_pcie,
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struct platform_device *pdev)
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{
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int ret;
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struct dw_pcie_ep *ep;
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struct resource *res;
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struct device *dev = &pdev->dev;
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struct dw_pcie *pci = ks_pcie->pci;
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ep = &pci->ep;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
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if (!res)
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return -EINVAL;
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ep->phys_base = res->start;
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ep->addr_size = resource_size(res);
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ret = dw_pcie_ep_init(ep);
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if (ret) {
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dev_err(dev, "failed to initialize endpoint\n");
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return ret;
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}
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return 0;
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}
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static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie)
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{
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int num_lanes = ks_pcie->num_lanes;
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@ -1313,7 +1286,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
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}
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pci->ep.ops = ep_ops;
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ret = ks_pcie_add_pcie_ep(ks_pcie, pdev);
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ret = dw_pcie_ep_init(&pci->ep);
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if (ret < 0)
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goto err_get_sync;
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break;
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@ -18,8 +18,6 @@
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#include "pcie-designware.h"
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#define PCIE_DBI2_OFFSET 0x1000 /* DBI2 base address*/
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#define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
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struct ls_pcie_ep_drvdata {
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@ -124,34 +122,6 @@ static const struct of_device_id ls_pcie_ep_of_match[] = {
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{ },
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};
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static int __init ls_add_pcie_ep(struct ls_pcie_ep *pcie,
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struct platform_device *pdev)
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{
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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struct dw_pcie_ep *ep;
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struct resource *res;
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int ret;
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ep = &pci->ep;
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ep->ops = pcie->drvdata->ops;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
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if (!res)
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return -EINVAL;
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ep->phys_base = res->start;
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ep->addr_size = resource_size(res);
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ret = dw_pcie_ep_init(ep);
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if (ret) {
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dev_err(dev, "failed to initialize endpoint\n");
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return ret;
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}
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return 0;
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}
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static int __init ls_pcie_ep_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@ -159,7 +129,6 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
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struct ls_pcie_ep *pcie;
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struct pci_epc_features *ls_epc;
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struct resource *dbi_base;
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int ret;
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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@ -188,13 +157,11 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
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if (IS_ERR(pci->dbi_base))
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return PTR_ERR(pci->dbi_base);
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pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET;
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pci->ep.ops = &ls_pcie_ep_ops;
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platform_set_drvdata(pdev, pcie);
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ret = ls_add_pcie_ep(pcie, pdev);
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return ret;
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return dw_pcie_ep_init(&pci->ep);
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}
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static struct platform_driver ls_pcie_ep_driver = {
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@ -347,7 +347,6 @@ static int al_pcie_probe(struct platform_device *pdev)
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struct device *dev = &pdev->dev;
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struct resource *controller_res;
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struct resource *ecam_res;
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struct resource *dbi_res;
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struct al_pcie *al_pcie;
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struct dw_pcie *pci;
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@ -365,11 +364,6 @@ static int al_pcie_probe(struct platform_device *pdev)
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al_pcie->pci = pci;
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al_pcie->dev = dev;
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dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
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pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res);
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if (IS_ERR(pci->dbi_base))
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return PTR_ERR(pci->dbi_base);
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ecam_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
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if (!ecam_res) {
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dev_err(dev, "couldn't find 'config' reg in DT\n");
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@ -386,8 +380,7 @@ static int al_pcie_probe(struct platform_device *pdev)
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return PTR_ERR(al_pcie->controller_base);
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}
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dev_dbg(dev, "From DT: dbi_base: %pR, controller_base: %pR\n",
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dbi_res, controller_res);
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dev_dbg(dev, "From DT: controller_base: %pR\n", controller_res);
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platform_set_drvdata(pdev, al_pcie);
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@ -403,38 +403,6 @@ static const struct dw_pcie_ep_ops pcie_ep_ops = {
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.raise_irq = artpec6_pcie_raise_irq,
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};
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static int artpec6_add_pcie_ep(struct artpec6_pcie *artpec6_pcie,
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struct platform_device *pdev)
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{
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int ret;
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struct dw_pcie_ep *ep;
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struct resource *res;
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struct device *dev = &pdev->dev;
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struct dw_pcie *pci = artpec6_pcie->pci;
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ep = &pci->ep;
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ep->ops = &pcie_ep_ops;
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pci->dbi_base2 = devm_platform_ioremap_resource_byname(pdev, "dbi2");
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if (IS_ERR(pci->dbi_base2))
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return PTR_ERR(pci->dbi_base2);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
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if (!res)
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return -EINVAL;
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ep->phys_base = res->start;
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ep->addr_size = resource_size(res);
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ret = dw_pcie_ep_init(ep);
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if (ret) {
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dev_err(dev, "failed to initialize endpoint\n");
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return ret;
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}
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return 0;
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}
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static int artpec6_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@ -469,10 +437,6 @@ static int artpec6_pcie_probe(struct platform_device *pdev)
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artpec6_pcie->variant = variant;
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artpec6_pcie->mode = mode;
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pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "dbi");
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if (IS_ERR(pci->dbi_base))
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return PTR_ERR(pci->dbi_base);
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artpec6_pcie->phy_base =
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devm_platform_ioremap_resource_byname(pdev, "phy");
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if (IS_ERR(artpec6_pcie->phy_base))
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@ -504,9 +468,10 @@ static int artpec6_pcie_probe(struct platform_device *pdev)
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val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
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val &= ~PCIECFG_DEVICE_TYPE_MASK;
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artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
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ret = artpec6_add_pcie_ep(artpec6_pcie, pdev);
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if (ret < 0)
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return ret;
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pci->ep.ops = &pcie_ep_ops;
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return dw_pcie_ep_init(&pci->ep);
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break;
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}
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default:
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@ -7,6 +7,7 @@
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*/
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include "pcie-designware.h"
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#include <linux/pci-epc.h>
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@ -676,20 +677,42 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
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int ret;
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void *addr;
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u8 func_no;
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struct resource *res;
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struct pci_epc *epc;
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct device *dev = pci->dev;
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struct platform_device *pdev = to_platform_device(dev);
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struct device_node *np = dev->of_node;
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const struct pci_epc_features *epc_features;
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struct dw_pcie_ep_func *ep_func;
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INIT_LIST_HEAD(&ep->func_list);
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if (!pci->dbi_base || !pci->dbi_base2) {
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dev_err(dev, "dbi_base/dbi_base2 is not populated\n");
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return -EINVAL;
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if (!pci->dbi_base) {
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
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pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
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if (IS_ERR(pci->dbi_base))
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return PTR_ERR(pci->dbi_base);
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}
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if (!pci->dbi_base2) {
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2");
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if (!res)
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pci->dbi_base2 = pci->dbi_base + SZ_4K;
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else {
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pci->dbi_base2 = devm_pci_remap_cfg_resource(dev, res);
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if (IS_ERR(pci->dbi_base2))
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return PTR_ERR(pci->dbi_base2);
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}
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
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if (!res)
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return -EINVAL;
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ep->phys_base = res->start;
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ep->addr_size = resource_size(res);
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ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows);
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if (ret < 0) {
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dev_err(dev, "Unable to read *num-ib-windows* property\n");
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@ -310,6 +310,13 @@ int dw_pcie_host_init(struct pcie_port *pp)
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dev_err(dev, "Missing *config* reg space\n");
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}
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if (!pci->dbi_base) {
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struct resource *dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
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pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res);
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if (IS_ERR(pci->dbi_base))
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return PTR_ERR(pci->dbi_base);
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}
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bridge = devm_pci_alloc_host_bridge(dev, 0);
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if (!bridge)
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return -ENOMEM;
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@ -139,43 +139,11 @@ static int dw_plat_add_pcie_port(struct dw_plat_pcie *dw_plat_pcie,
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return 0;
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}
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static int dw_plat_add_pcie_ep(struct dw_plat_pcie *dw_plat_pcie,
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struct platform_device *pdev)
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{
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int ret;
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struct dw_pcie_ep *ep;
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struct resource *res;
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struct device *dev = &pdev->dev;
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struct dw_pcie *pci = dw_plat_pcie->pci;
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ep = &pci->ep;
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ep->ops = &pcie_ep_ops;
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pci->dbi_base2 = devm_platform_ioremap_resource_byname(pdev, "dbi2");
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if (IS_ERR(pci->dbi_base2))
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return PTR_ERR(pci->dbi_base2);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
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if (!res)
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return -EINVAL;
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ep->phys_base = res->start;
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ep->addr_size = resource_size(res);
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ret = dw_pcie_ep_init(ep);
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if (ret) {
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dev_err(dev, "Failed to initialize endpoint\n");
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return ret;
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}
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return 0;
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}
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static int dw_plat_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct dw_plat_pcie *dw_plat_pcie;
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struct dw_pcie *pci;
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struct resource *res; /* Resource from DT */
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int ret;
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const struct of_device_id *match;
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const struct dw_plat_pcie_of_data *data;
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@ -202,14 +170,6 @@ static int dw_plat_pcie_probe(struct platform_device *pdev)
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dw_plat_pcie->pci = pci;
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dw_plat_pcie->mode = mode;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
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if (!res)
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pci->dbi_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(pci->dbi_base))
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return PTR_ERR(pci->dbi_base);
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platform_set_drvdata(pdev, dw_plat_pcie);
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switch (dw_plat_pcie->mode) {
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@ -225,9 +185,8 @@ static int dw_plat_pcie_probe(struct platform_device *pdev)
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if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_EP))
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return -ENODEV;
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ret = dw_plat_add_pcie_ep(dw_plat_pcie, pdev);
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if (ret < 0)
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return ret;
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pci->ep.ops = &pcie_ep_ops;
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return dw_pcie_ep_init(&pci->ep);
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break;
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default:
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dev_err(dev, "INVALID device type %d\n", dw_plat_pcie->mode);
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@ -237,10 +237,6 @@ static int intel_pcie_get_resources(struct platform_device *pdev)
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struct device *dev = pci->dev;
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int ret;
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pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "dbi");
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if (IS_ERR(pci->dbi_base))
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return PTR_ERR(pci->dbi_base);
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lpp->core_clk = devm_clk_get(dev, NULL);
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if (IS_ERR(lpp->core_clk)) {
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ret = PTR_ERR(lpp->core_clk);
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@ -157,11 +157,6 @@ static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
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if (IS_ERR(kirin_pcie->phy_base))
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return PTR_ERR(kirin_pcie->phy_base);
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kirin_pcie->pci->dbi_base =
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devm_platform_ioremap_resource_byname(pdev, "dbi");
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if (IS_ERR(kirin_pcie->pci->dbi_base))
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return PTR_ERR(kirin_pcie->pci->dbi_base);
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kirin_pcie->crgctrl =
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syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl");
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||||
if (IS_ERR(kirin_pcie->crgctrl))
|
||||
|
|
|
@ -1368,7 +1368,6 @@ static const struct dw_pcie_ops dw_pcie_ops = {
|
|||
static int qcom_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct resource *res;
|
||||
struct pcie_port *pp;
|
||||
struct dw_pcie *pci;
|
||||
struct qcom_pcie *pcie;
|
||||
|
@ -1407,13 +1406,6 @@ static int qcom_pcie_probe(struct platform_device *pdev)
|
|||
goto err_pm_runtime_put;
|
||||
}
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
|
||||
pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
|
||||
if (IS_ERR(pci->dbi_base)) {
|
||||
ret = PTR_ERR(pci->dbi_base);
|
||||
goto err_pm_runtime_put;
|
||||
}
|
||||
|
||||
pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi");
|
||||
if (IS_ERR(pcie->elbi)) {
|
||||
ret = PTR_ERR(pcie->elbi);
|
||||
|
|
|
@ -152,6 +152,8 @@ static int spear13xx_pcie_host_init(struct pcie_port *pp)
|
|||
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
||||
struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
|
||||
|
||||
spear13xx_pcie->app_base = pci->dbi_base + 0x2000;
|
||||
|
||||
spear13xx_pcie_establish_link(spear13xx_pcie);
|
||||
spear13xx_pcie_enable_interrupts(spear13xx_pcie);
|
||||
|
||||
|
@ -203,7 +205,6 @@ static int spear13xx_pcie_probe(struct platform_device *pdev)
|
|||
struct dw_pcie *pci;
|
||||
struct spear13xx_pcie *spear13xx_pcie;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct resource *dbi_base;
|
||||
int ret;
|
||||
|
||||
spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
|
||||
|
@ -242,14 +243,6 @@ static int spear13xx_pcie_probe(struct platform_device *pdev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
|
||||
pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
|
||||
if (IS_ERR(pci->dbi_base)) {
|
||||
ret = PTR_ERR(pci->dbi_base);
|
||||
goto fail_clk;
|
||||
}
|
||||
spear13xx_pcie->app_base = pci->dbi_base + 0x2000;
|
||||
|
||||
if (of_property_read_bool(np, "st,pcie-is-gen1"))
|
||||
pci->link_gen = 1;
|
||||
|
||||
|
|
|
@ -1907,19 +1907,12 @@ static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie,
|
|||
struct dw_pcie *pci = &pcie->pci;
|
||||
struct device *dev = pcie->dev;
|
||||
struct dw_pcie_ep *ep;
|
||||
struct resource *res;
|
||||
char *name;
|
||||
int ret;
|
||||
|
||||
ep = &pci->ep;
|
||||
ep->ops = &pcie_ep_ops;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
|
||||
if (!res)
|
||||
return -EINVAL;
|
||||
|
||||
ep->phys_base = res->start;
|
||||
ep->addr_size = resource_size(res);
|
||||
ep->page_size = SZ_64K;
|
||||
|
||||
ret = gpiod_set_debounce(pcie->pex_rst_gpiod, PERST_DEBOUNCE_TIME);
|
||||
|
@ -1982,7 +1975,6 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
|
|||
struct device *dev = &pdev->dev;
|
||||
struct resource *atu_dma_res;
|
||||
struct tegra_pcie_dw *pcie;
|
||||
struct resource *dbi_res;
|
||||
struct pcie_port *pp;
|
||||
struct dw_pcie *pci;
|
||||
struct phy **phys;
|
||||
|
@ -2091,20 +2083,6 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
|
|||
|
||||
pcie->phys = phys;
|
||||
|
||||
dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
|
||||
if (!dbi_res) {
|
||||
dev_err(dev, "Failed to find \"dbi\" region\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
pcie->dbi_res = dbi_res;
|
||||
|
||||
pci->dbi_base = devm_ioremap_resource(dev, dbi_res);
|
||||
if (IS_ERR(pci->dbi_base))
|
||||
return PTR_ERR(pci->dbi_base);
|
||||
|
||||
/* Tegra HW locates DBI2 at a fixed offset from DBI */
|
||||
pci->dbi_base2 = pci->dbi_base + 0x1000;
|
||||
|
||||
atu_dma_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
||||
"atu_dma");
|
||||
if (!atu_dma_res) {
|
||||
|
|
|
@ -218,35 +218,6 @@ static const struct dw_pcie_ep_ops uniphier_pcie_ep_ops = {
|
|||
.get_features = uniphier_pcie_get_features,
|
||||
};
|
||||
|
||||
static int uniphier_add_pcie_ep(struct uniphier_pcie_ep_priv *priv,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
struct dw_pcie *pci = &priv->pci;
|
||||
struct dw_pcie_ep *ep = &pci->ep;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
ep->ops = &uniphier_pcie_ep_ops;
|
||||
|
||||
pci->dbi_base2 = devm_platform_ioremap_resource_byname(pdev, "dbi2");
|
||||
if (IS_ERR(pci->dbi_base2))
|
||||
return PTR_ERR(pci->dbi_base2);
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
|
||||
if (!res)
|
||||
return -EINVAL;
|
||||
|
||||
ep->phys_base = res->start;
|
||||
ep->addr_size = resource_size(res);
|
||||
|
||||
ret = dw_pcie_ep_init(ep);
|
||||
if (ret)
|
||||
dev_err(dev, "Failed to initialize endpoint (%d)\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int uniphier_pcie_ep_enable(struct uniphier_pcie_ep_priv *priv)
|
||||
{
|
||||
int ret;
|
||||
|
@ -300,7 +271,6 @@ static int uniphier_pcie_ep_probe(struct platform_device *pdev)
|
|||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct uniphier_pcie_ep_priv *priv;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
|
@ -314,11 +284,6 @@ static int uniphier_pcie_ep_probe(struct platform_device *pdev)
|
|||
priv->pci.dev = dev;
|
||||
priv->pci.ops = &dw_pcie_ops;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
|
||||
priv->pci.dbi_base = devm_pci_remap_cfg_resource(dev, res);
|
||||
if (IS_ERR(priv->pci.dbi_base))
|
||||
return PTR_ERR(priv->pci.dbi_base);
|
||||
|
||||
priv->base = devm_platform_ioremap_resource_byname(pdev, "link");
|
||||
if (IS_ERR(priv->base))
|
||||
return PTR_ERR(priv->base);
|
||||
|
@ -352,7 +317,8 @@ static int uniphier_pcie_ep_probe(struct platform_device *pdev)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
return uniphier_add_pcie_ep(priv, pdev);
|
||||
priv->pci.ep.ops = &uniphier_pcie_ep_ops;
|
||||
return dw_pcie_ep_init(&priv->pci.ep);
|
||||
}
|
||||
|
||||
static const struct pci_epc_features uniphier_pro5_data = {
|
||||
|
|
|
@ -400,7 +400,6 @@ static int uniphier_pcie_probe(struct platform_device *pdev)
|
|||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct uniphier_pcie_priv *priv;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
|
@ -410,11 +409,6 @@ static int uniphier_pcie_probe(struct platform_device *pdev)
|
|||
priv->pci.dev = dev;
|
||||
priv->pci.ops = &dw_pcie_ops;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
|
||||
priv->pci.dbi_base = devm_pci_remap_cfg_resource(dev, res);
|
||||
if (IS_ERR(priv->pci.dbi_base))
|
||||
return PTR_ERR(priv->pci.dbi_base);
|
||||
|
||||
priv->base = devm_platform_ioremap_resource_byname(pdev, "link");
|
||||
if (IS_ERR(priv->base))
|
||||
return PTR_ERR(priv->base);
|
||||
|
|
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