[CELL] spufs: limit saving MFC_CNTL bits
At save step 8, the mfc control register in the CSA should be written _only_ with Sc and Sm bits (at least MFC_CNTL[Dh] should be set to 0) Signed-off-by: Masato Noguchi <Masato.Noguchi@jp.sony.com> Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
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@ -180,7 +180,7 @@ static inline void save_mfc_cntl(struct spu_state *csa, struct spu *spu)
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case MFC_CNTL_SUSPEND_COMPLETE:
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if (csa) {
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csa->priv2.mfc_control_RW =
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in_be64(&priv2->mfc_control_RW) |
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MFC_CNTL_SUSPEND_MASK |
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MFC_CNTL_SUSPEND_DMA_QUEUE;
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}
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break;
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@ -190,9 +190,7 @@ static inline void save_mfc_cntl(struct spu_state *csa, struct spu *spu)
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MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
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MFC_CNTL_SUSPEND_COMPLETE);
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if (csa) {
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csa->priv2.mfc_control_RW =
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in_be64(&priv2->mfc_control_RW) &
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~MFC_CNTL_SUSPEND_DMA_QUEUE;
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csa->priv2.mfc_control_RW = 0;
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}
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break;
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}
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@ -251,11 +249,8 @@ static inline void save_mfc_decr(struct spu_state *csa, struct spu *spu)
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* Read MFC_CNTL[Ds]. Update saved copy of
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* CSA.MFC_CNTL[Ds].
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*/
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if (in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DECREMENTER_RUNNING) {
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csa->priv2.mfc_control_RW |= MFC_CNTL_DECREMENTER_RUNNING;
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} else {
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csa->priv2.mfc_control_RW &= ~MFC_CNTL_DECREMENTER_RUNNING;
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}
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csa->priv2.mfc_control_RW |=
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in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DECREMENTER_RUNNING;
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}
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static inline void halt_mfc_decr(struct spu_state *csa, struct spu *spu)
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