ARM: mmp: irq_data conversion.
Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca>
This commit is contained in:
Родитель
5638538117
Коммит
a157f26b2e
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@ -20,48 +20,48 @@
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#include "common.h"
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#include "common.h"
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static void icu_mask_irq(unsigned int irq)
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static void icu_mask_irq(struct irq_data *d)
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{
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{
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uint32_t r = __raw_readl(ICU_INT_CONF(irq));
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uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
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r &= ~ICU_INT_ROUTE_PJ4_IRQ;
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r &= ~ICU_INT_ROUTE_PJ4_IRQ;
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__raw_writel(r, ICU_INT_CONF(irq));
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__raw_writel(r, ICU_INT_CONF(d->irq));
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}
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}
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static void icu_unmask_irq(unsigned int irq)
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static void icu_unmask_irq(struct irq_data *d)
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{
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{
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uint32_t r = __raw_readl(ICU_INT_CONF(irq));
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uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
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r |= ICU_INT_ROUTE_PJ4_IRQ;
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r |= ICU_INT_ROUTE_PJ4_IRQ;
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__raw_writel(r, ICU_INT_CONF(irq));
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__raw_writel(r, ICU_INT_CONF(d->irq));
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}
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}
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static struct irq_chip icu_irq_chip = {
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static struct irq_chip icu_irq_chip = {
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.name = "icu_irq",
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.name = "icu_irq",
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.mask = icu_mask_irq,
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.irq_mask = icu_mask_irq,
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.mask_ack = icu_mask_irq,
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.irq_mask_ack = icu_mask_irq,
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.unmask = icu_unmask_irq,
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.irq_unmask = icu_unmask_irq,
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};
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};
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static void pmic_irq_ack(unsigned int irq)
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static void pmic_irq_ack(struct irq_data *d)
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{
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{
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if (irq == IRQ_MMP2_PMIC)
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if (d->irq == IRQ_MMP2_PMIC)
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mmp2_clear_pmic_int();
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mmp2_clear_pmic_int();
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}
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}
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#define SECOND_IRQ_MASK(_name_, irq_base, prefix) \
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#define SECOND_IRQ_MASK(_name_, irq_base, prefix) \
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static void _name_##_mask_irq(unsigned int irq) \
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static void _name_##_mask_irq(struct irq_data *d) \
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{ \
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{ \
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uint32_t r; \
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uint32_t r; \
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r = __raw_readl(prefix##_MASK) | (1 << (irq - irq_base)); \
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r = __raw_readl(prefix##_MASK) | (1 << (d->irq - irq_base)); \
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__raw_writel(r, prefix##_MASK); \
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__raw_writel(r, prefix##_MASK); \
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}
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}
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#define SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \
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#define SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \
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static void _name_##_unmask_irq(unsigned int irq) \
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static void _name_##_unmask_irq(struct irq_data *d) \
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{ \
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{ \
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uint32_t r; \
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uint32_t r; \
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r = __raw_readl(prefix##_MASK) & ~(1 << (irq - irq_base)); \
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r = __raw_readl(prefix##_MASK) & ~(1 << (d->irq - irq_base)); \
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__raw_writel(r, prefix##_MASK); \
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__raw_writel(r, prefix##_MASK); \
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}
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}
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@ -88,8 +88,8 @@ SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \
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SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \
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SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \
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static struct irq_chip _name_##_irq_chip = { \
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static struct irq_chip _name_##_irq_chip = { \
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.name = #_name_, \
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.name = #_name_, \
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.mask = _name_##_mask_irq, \
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.irq_mask = _name_##_mask_irq, \
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.unmask = _name_##_unmask_irq, \
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.irq_unmask = _name_##_unmask_irq, \
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}
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}
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SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4);
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SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4);
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@ -103,10 +103,12 @@ static void init_mux_irq(struct irq_chip *chip, int start, int num)
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int irq;
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int irq;
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for (irq = start; num > 0; irq++, num--) {
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for (irq = start; num > 0; irq++, num--) {
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struct irq_data *d = irq_get_irq_data(irq);
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/* mask and clear the IRQ */
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/* mask and clear the IRQ */
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chip->mask(irq);
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chip->irq_mask(d);
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if (chip->ack)
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if (chip->irq_ack)
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chip->ack(irq);
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chip->irq_ack(d);
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set_irq_chip(irq, chip);
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set_irq_chip(irq, chip);
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set_irq_flags(irq, IRQF_VALID);
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set_irq_flags(irq, IRQF_VALID);
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@ -119,7 +121,7 @@ void __init mmp2_init_icu(void)
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int irq;
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int irq;
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for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
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for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
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icu_mask_irq(irq);
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icu_mask_irq(irq_get_irq_data(irq));
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set_irq_chip(irq, &icu_irq_chip);
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set_irq_chip(irq, &icu_irq_chip);
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set_irq_flags(irq, IRQF_VALID);
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set_irq_flags(irq, IRQF_VALID);
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@ -139,7 +141,7 @@ void __init mmp2_init_icu(void)
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/* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register
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/* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register
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* to be written to clear the interrupt
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* to be written to clear the interrupt
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*/
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*/
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pmic_irq_chip.ack = pmic_irq_ack;
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pmic_irq_chip.irq_ack = pmic_irq_ack;
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init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2);
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init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2);
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init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2);
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init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2);
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@ -25,21 +25,21 @@
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#define PRIORITY_DEFAULT 0x1
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#define PRIORITY_DEFAULT 0x1
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#define PRIORITY_NONE 0x0 /* means IRQ disabled */
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#define PRIORITY_NONE 0x0 /* means IRQ disabled */
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static void icu_mask_irq(unsigned int irq)
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static void icu_mask_irq(struct irq_data *d)
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{
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{
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__raw_writel(PRIORITY_NONE, ICU_INT_CONF(irq));
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__raw_writel(PRIORITY_NONE, ICU_INT_CONF(d->irq));
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}
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}
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static void icu_unmask_irq(unsigned int irq)
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static void icu_unmask_irq(struct irq_data *d)
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{
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{
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__raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(irq));
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__raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(d->irq));
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}
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}
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static struct irq_chip icu_irq_chip = {
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static struct irq_chip icu_irq_chip = {
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.name = "icu_irq",
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.name = "icu_irq",
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.ack = icu_mask_irq,
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.irq_ack = icu_mask_irq,
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.mask = icu_mask_irq,
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.irq_mask = icu_mask_irq,
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.unmask = icu_unmask_irq,
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.irq_unmask = icu_unmask_irq,
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};
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};
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void __init icu_init_irq(void)
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void __init icu_init_irq(void)
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@ -47,7 +47,7 @@ void __init icu_init_irq(void)
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int irq;
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int irq;
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for (irq = 0; irq < 64; irq++) {
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for (irq = 0; irq < 64; irq++) {
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icu_mask_irq(irq);
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icu_mask_irq(irq_get_irq_data(irq));
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set_irq_chip(irq, &icu_irq_chip);
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set_irq_chip(irq, &icu_irq_chip);
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set_irq_handler(irq, handle_level_irq);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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set_irq_flags(irq, IRQF_VALID);
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