pinctrl: sirf: drop marco support
marco chip has been dropped, clear its support. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Родитель
63b5aed37b
Коммит
a17272a46c
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@ -113,7 +113,7 @@ config PINCTRL_SINGLE
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This selects the device tree based generic pinctrl driver.
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config PINCTRL_SIRF
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bool "CSR SiRFprimaII/SiRFmarco pin controller driver"
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bool "CSR SiRFprimaII pin controller driver"
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depends on ARCH_SIRF
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select PINMUX
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select GPIOLIB_IRQCHIP
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@ -38,7 +38,6 @@ struct sirfsoc_gpio_bank {
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struct sirfsoc_gpio_chip {
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struct of_mm_gpio_chip chip;
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bool is_marco; /* for marco, some registers are different with prima2 */
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struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
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};
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@ -149,23 +148,14 @@ static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx,
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for (i = 0; i < mux->muxmask_counts; i++) {
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u32 muxval;
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if (!spmx->is_marco) {
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muxval = readl(spmx->gpio_virtbase +
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SIRFSOC_GPIO_PAD_EN(mask[i].group));
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if (enable)
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muxval = muxval & ~mask[i].mask;
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else
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muxval = muxval | mask[i].mask;
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writel(muxval, spmx->gpio_virtbase +
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SIRFSOC_GPIO_PAD_EN(mask[i].group));
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} else {
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if (enable)
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writel(mask[i].mask, spmx->gpio_virtbase +
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SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group));
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else
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writel(mask[i].mask, spmx->gpio_virtbase +
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SIRFSOC_GPIO_PAD_EN(mask[i].group));
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}
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muxval = readl(spmx->gpio_virtbase +
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SIRFSOC_GPIO_PAD_EN(mask[i].group));
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if (enable)
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muxval = muxval & ~mask[i].mask;
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else
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muxval = muxval | mask[i].mask;
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writel(muxval, spmx->gpio_virtbase +
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SIRFSOC_GPIO_PAD_EN(mask[i].group));
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}
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if (mux->funcmask && enable) {
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@ -223,16 +213,11 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
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spmx = pinctrl_dev_get_drvdata(pmxdev);
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if (!spmx->is_marco) {
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muxval = readl(spmx->gpio_virtbase +
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SIRFSOC_GPIO_PAD_EN(group));
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muxval = muxval | (1 << (offset - range->pin_base));
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writel(muxval, spmx->gpio_virtbase +
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SIRFSOC_GPIO_PAD_EN(group));
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} else {
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writel(1 << (offset - range->pin_base), spmx->gpio_virtbase +
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SIRFSOC_GPIO_PAD_EN(group));
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}
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muxval = readl(spmx->gpio_virtbase +
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SIRFSOC_GPIO_PAD_EN(group));
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muxval = muxval | (1 << (offset - range->pin_base));
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writel(muxval, spmx->gpio_virtbase +
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SIRFSOC_GPIO_PAD_EN(group));
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return 0;
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}
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@ -256,7 +241,6 @@ static void __iomem *sirfsoc_rsc_of_iomap(void)
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{
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const struct of_device_id rsc_ids[] = {
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{ .compatible = "sirf,prima2-rsc" },
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{ .compatible = "sirf,marco-rsc" },
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{}
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};
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struct device_node *np;
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@ -284,7 +268,6 @@ static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
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static const struct of_device_id pinmux_ids[] = {
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{ .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, },
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{ .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, },
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{ .compatible = "sirf,marco-pinctrl", .data = &prima2_pinctrl_data, },
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{}
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};
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@ -317,9 +300,6 @@ static int sirfsoc_pinmux_probe(struct platform_device *pdev)
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goto out_no_rsc_remap;
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}
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if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
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spmx->is_marco = 1;
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pdata = of_match_node(pinmux_ids, np)->data;
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sirfsoc_pin_groups = pdata->grps;
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sirfsoc_pingrp_cnt = pdata->grps_cnt;
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@ -803,7 +783,6 @@ static int sirfsoc_gpio_probe(struct device_node *np)
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struct sirfsoc_gpio_bank *bank;
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void __iomem *regs;
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struct platform_device *pdev;
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bool is_marco = false;
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u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
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@ -819,9 +798,6 @@ static int sirfsoc_gpio_probe(struct device_node *np)
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if (!regs)
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return -ENOMEM;
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if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
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is_marco = 1;
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sgpio->chip.gc.request = sirfsoc_gpio_request;
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sgpio->chip.gc.free = sirfsoc_gpio_free;
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sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input;
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@ -836,7 +812,6 @@ static int sirfsoc_gpio_probe(struct device_node *np)
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sgpio->chip.gc.of_gpio_n_cells = 2;
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sgpio->chip.gc.dev = &pdev->dev;
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sgpio->chip.regs = regs;
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sgpio->is_marco = is_marco;
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err = gpiochip_add(&sgpio->chip.gc);
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if (err) {
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@ -49,7 +49,6 @@ struct sirfsoc_pmx {
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u32 paden_regs[SIRFSOC_GPIO_NO_OF_BANKS];
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u32 dspen_regs;
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u32 rsc_regs[3];
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bool is_marco;
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};
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/* SIRFSOC_GPIO_PAD_EN set */
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