net: dsa: mv88e6xxx: add PPU operations
Some Marvell chips can enable/disable the PPU on demand. This is needed to access the PHY registers when there is no indirection mechanism. Add two new ppu_enable and ppu_disable ops to describe this and finally get rid of the MV88E6XXX_FLAG_PPU* flags. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vivien Didelot
David S. Miller
Родитель
17e708baf7
Коммит
a199d8b695
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@ -527,58 +527,18 @@ int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
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static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
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{
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u16 val;
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int i, err;
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if (!chip->info->ops->ppu_disable)
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return 0;
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err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
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if (err)
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return err;
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err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
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val & ~GLOBAL_CONTROL_PPU_ENABLE);
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if (err)
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return err;
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for (i = 0; i < 16; i++) {
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err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
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if (err)
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return err;
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usleep_range(1000, 2000);
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val &= GLOBAL_STATUS_PPU_STATE_MASK;
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if (val != GLOBAL_STATUS_PPU_STATE_POLLING)
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return 0;
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}
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return -ETIMEDOUT;
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return chip->info->ops->ppu_disable(chip);
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}
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static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
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{
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u16 val;
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int i, err;
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if (!chip->info->ops->ppu_enable)
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return 0;
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err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
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if (err)
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return err;
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err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
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val | GLOBAL_CONTROL_PPU_ENABLE);
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if (err)
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return err;
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for (i = 0; i < 16; i++) {
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err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
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if (err)
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return err;
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usleep_range(1000, 2000);
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val &= GLOBAL_STATUS_PPU_STATE_MASK;
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if (val == GLOBAL_STATUS_PPU_STATE_POLLING)
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return 0;
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}
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return -ETIMEDOUT;
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return chip->info->ops->ppu_enable(chip);
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}
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static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
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@ -2746,22 +2706,12 @@ static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
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{
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struct dsa_switch *ds = chip->ds;
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u32 upstream_port = dsa_upstream_port(ds);
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u16 reg;
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int err;
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/* Enable the PHY Polling Unit if present, don't discard any packets,
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* and mask all interrupt sources.
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*/
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err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, ®);
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if (err < 0)
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return err;
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reg &= ~GLOBAL_CONTROL_PPU_ENABLE;
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if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
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mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
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reg |= GLOBAL_CONTROL_PPU_ENABLE;
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err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
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err = mv88e6xxx_ppu_enable(chip);
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if (err)
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return err;
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@ -3223,6 +3173,8 @@ static const struct mv88e6xxx_ops mv88e6085_ops = {
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.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
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.g1_set_egress_port = mv88e6095_g1_set_egress_port,
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.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
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.ppu_enable = mv88e6185_g1_ppu_enable,
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.ppu_disable = mv88e6185_g1_ppu_disable,
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.reset = mv88e6185_g1_reset,
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};
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@ -3241,6 +3193,8 @@ static const struct mv88e6xxx_ops mv88e6095_ops = {
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.stats_get_strings = mv88e6095_stats_get_strings,
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.stats_get_stats = mv88e6095_stats_get_stats,
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.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
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.ppu_enable = mv88e6185_g1_ppu_enable,
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.ppu_disable = mv88e6185_g1_ppu_disable,
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.reset = mv88e6185_g1_reset,
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};
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@ -3311,6 +3265,8 @@ static const struct mv88e6xxx_ops mv88e6131_ops = {
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.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
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.g1_set_egress_port = mv88e6095_g1_set_egress_port,
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.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
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.ppu_enable = mv88e6185_g1_ppu_enable,
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.ppu_disable = mv88e6185_g1_ppu_disable,
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.reset = mv88e6185_g1_reset,
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};
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@ -3483,6 +3439,8 @@ static const struct mv88e6xxx_ops mv88e6185_ops = {
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.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
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.g1_set_egress_port = mv88e6095_g1_set_egress_port,
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.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
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.ppu_enable = mv88e6185_g1_ppu_enable,
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.ppu_disable = mv88e6185_g1_ppu_disable,
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.reset = mv88e6185_g1_reset,
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};
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@ -4263,13 +4221,13 @@ static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
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static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
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{
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if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
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if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
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mv88e6xxx_ppu_state_init(chip);
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}
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static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
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{
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if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
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if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
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mv88e6xxx_ppu_state_destroy(chip);
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}
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@ -35,6 +35,27 @@ int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
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/* Offset 0x00: Switch Global Status Register */
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static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip)
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{
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u16 state;
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int i, err;
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for (i = 0; i < 16; i++) {
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err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &state);
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if (err)
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return err;
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/* Check the value of the PPUState bits 15:14 */
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state &= GLOBAL_STATUS_PPU_STATE_MASK;
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if (state != GLOBAL_STATUS_PPU_STATE_POLLING)
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return 0;
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usleep_range(1000, 2000);
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}
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return -ETIMEDOUT;
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}
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static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
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{
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u16 state;
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@ -154,6 +175,42 @@ int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
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return mv88e6352_g1_wait_ppu_polling(chip);
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}
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int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip)
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{
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u16 val;
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int err;
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err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
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if (err)
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return err;
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val |= GLOBAL_CONTROL_PPU_ENABLE;
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err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, val);
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if (err)
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return err;
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return mv88e6185_g1_wait_ppu_polling(chip);
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}
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int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip)
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{
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u16 val;
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int err;
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err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
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if (err)
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return err;
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val &= ~GLOBAL_CONTROL_PPU_ENABLE;
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err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, val);
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if (err)
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return err;
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return mv88e6185_g1_wait_ppu_disabled(chip);
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}
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/* Offset 0x1a: Monitor Control */
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/* Offset 0x1a: Monitor & MGMT Control on some devices */
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@ -23,6 +23,9 @@ int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask);
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int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip);
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int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip);
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int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip);
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int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip);
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int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip);
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int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
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int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
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@ -490,12 +490,6 @@ enum mv88e6xxx_cap {
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MV88E6XXX_CAP_G2_PVT_DATA, /* (0x0c) Cross Chip Port VLAN Data */
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MV88E6XXX_CAP_G2_POT, /* (0x0f) Priority Override Table */
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/* PHY Polling Unit.
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* See GLOBAL_CONTROL_PPU_ENABLE and GLOBAL_STATUS_PPU_POLLING.
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*/
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MV88E6XXX_CAP_PPU,
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MV88E6XXX_CAP_PPU_ACTIVE,
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/* Per VLAN Spanning Tree Unit (STU).
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* The Port State database, if present, is accessed through VTU
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* operations and dedicated SID registers. See GLOBAL_VTU_SID.
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@ -537,8 +531,6 @@ enum mv88e6xxx_cap {
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#define MV88E6XXX_FLAG_G2_PVT_DATA BIT_ULL(MV88E6XXX_CAP_G2_PVT_DATA)
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#define MV88E6XXX_FLAG_G2_POT BIT_ULL(MV88E6XXX_CAP_G2_POT)
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#define MV88E6XXX_FLAG_PPU BIT_ULL(MV88E6XXX_CAP_PPU)
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#define MV88E6XXX_FLAG_PPU_ACTIVE BIT_ULL(MV88E6XXX_CAP_PPU_ACTIVE)
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#define MV88E6XXX_FLAG_STU BIT_ULL(MV88E6XXX_CAP_STU)
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#define MV88E6XXX_FLAG_TEMP BIT_ULL(MV88E6XXX_CAP_TEMP)
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#define MV88E6XXX_FLAG_TEMP_LIMIT BIT_ULL(MV88E6XXX_CAP_TEMP_LIMIT)
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@ -567,7 +559,6 @@ enum mv88e6xxx_cap {
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#define MV88E6XXX_FLAGS_FAMILY_6095 \
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(MV88E6XXX_FLAG_GLOBAL2 | \
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MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
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MV88E6XXX_FLAG_PPU | \
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MV88E6XXX_FLAG_VTU | \
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MV88E6XXX_FLAGS_MULTI_CHIP)
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@ -578,7 +569,6 @@ enum mv88e6xxx_cap {
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MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
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MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
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MV88E6XXX_FLAG_G2_POT | \
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MV88E6XXX_FLAG_PPU | \
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MV88E6XXX_FLAG_STU | \
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MV88E6XXX_FLAG_VTU | \
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MV88E6XXX_FLAGS_IRL | \
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@ -605,7 +595,6 @@ enum mv88e6xxx_cap {
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MV88E6XXX_FLAG_G2_INT | \
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MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
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MV88E6XXX_FLAGS_MULTI_CHIP | \
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MV88E6XXX_FLAG_PPU | \
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MV88E6XXX_FLAG_VTU)
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#define MV88E6XXX_FLAGS_FAMILY_6320 \
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@ -614,7 +603,6 @@ enum mv88e6xxx_cap {
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MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
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MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
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MV88E6XXX_FLAG_G2_POT | \
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MV88E6XXX_FLAG_PPU_ACTIVE | \
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MV88E6XXX_FLAG_TEMP | \
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MV88E6XXX_FLAG_TEMP_LIMIT | \
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MV88E6XXX_FLAG_VTU | \
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@ -630,7 +618,6 @@ enum mv88e6xxx_cap {
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MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
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MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
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MV88E6XXX_FLAG_G2_POT | \
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MV88E6XXX_FLAG_PPU_ACTIVE | \
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MV88E6XXX_FLAG_STU | \
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MV88E6XXX_FLAG_TEMP | \
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MV88E6XXX_FLAG_VTU | \
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@ -647,7 +634,6 @@ enum mv88e6xxx_cap {
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MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
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MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
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MV88E6XXX_FLAG_G2_POT | \
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MV88E6XXX_FLAG_PPU_ACTIVE | \
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MV88E6XXX_FLAG_STU | \
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MV88E6XXX_FLAG_TEMP | \
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MV88E6XXX_FLAG_TEMP_LIMIT | \
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@ -662,7 +648,6 @@ struct mv88e6xxx_ops;
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#define MV88E6XXX_FLAGS_FAMILY_6390 \
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(MV88E6XXX_FLAG_EEE | \
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MV88E6XXX_FLAG_GLOBAL2 | \
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MV88E6XXX_FLAG_PPU_ACTIVE | \
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MV88E6XXX_FLAG_STU | \
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MV88E6XXX_FLAG_TEMP | \
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MV88E6XXX_FLAG_TEMP_LIMIT | \
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@ -792,6 +777,10 @@ struct mv88e6xxx_ops {
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int (*phy_write)(struct mv88e6xxx_chip *chip, int addr, int reg,
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u16 val);
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/* PHY Polling Unit (PPU) operations */
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int (*ppu_enable)(struct mv88e6xxx_chip *chip);
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int (*ppu_disable)(struct mv88e6xxx_chip *chip);
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/* Switch Software Reset */
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int (*reset)(struct mv88e6xxx_chip *chip);
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