clk: renesas: r9a06g032: Improve readability

Several small readability improvements:
- Move enum gate_type definition up and add comments to each field.
- Use this enum instead of generic uint32_t type in clock desc struct.
- Tidy up bitfield syntax and comments in clock desc structure
- Reformat macros for building clock desc to have one assignment per line

There is no functional change.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230301215520.828455-2-ralph.siemsen@linaro.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

drivers/clk/renesas/r9a06g032-clocks.c

@@ -34,26 +34,34 @@ struct r9a06g032_gate {
 		scon, mirack, mistat;
 };
 
+enum gate_type {
+	K_GATE = 0,	/* gate which enable/disable */
+	K_FFC,		/* fixed factor clock */
+	K_DIV,		/* divisor */
+	K_BITSEL,	/* special for UARTs */
+	K_DUALGATE	/* special for UARTs */
+};
+
 /* This is used to describe a clock for instantiation */
 struct r9a06g032_clkdesc {
 	const char *name;
 	uint32_t managed:1;
-	uint32_t type: 3;
+	enum gate_type type:3;
 	uint32_t index:8;
 	uint32_t source:8; /* source index + 1 (0 == none) */
-	/* these are used to populate the bitsel struct */
 	union {
+		/* type = K_GATE */
 		struct r9a06g032_gate gate;
-		/* for dividers */
+		/* type = K_DIV  */
 		struct {
 			unsigned int div_min:10, div_max:10, reg:10;
 			u16 div_table[4];
 		};
-		/* For fixed-factor ones */
+		/* type = K_FFC */
 		struct {
 			u16 div, mul;
 		};
-		/* for dual gate */
+		/* type = K_DUALGATE */
 		struct {
 			uint16_t group:1;
 			u16 sel, g1, r1, g2, r2;
@@ -61,37 +69,68 @@ struct r9a06g032_clkdesc {
 	};
 };
 
-#define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) \
+#define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) { \
-	{ .gate = _clk, .reset = _rst, \
+	.gate = _clk, \
-		.ready = _rdy, .midle = _midle, \
+	.reset = _rst, \
-		.scon = _scon, .mirack = _mirack, .mistat = _mistat }
+	.ready = _rdy, \
-#define D_GATE(_idx, _n, _src, ...) \
+	.midle = _midle, \
-	{ .type = K_GATE, .index = R9A06G032_##_idx, \
+	.scon = _scon, \
-		.source = 1 + R9A06G032_##_src, .name = _n, \
+	.mirack = _mirack, \
-		.gate = I_GATE(__VA_ARGS__) }
+	.mistat = _mistat \
-#define D_MODULE(_idx, _n, _src, ...) \
+}
-	{ .type = K_GATE, .index = R9A06G032_##_idx, \
+#define D_GATE(_idx, _n, _src, ...) { \
-		.source = 1 + R9A06G032_##_src, .name = _n, \
+	.type = K_GATE, \
-		.managed = 1, .gate = I_GATE(__VA_ARGS__) }
+	.index = R9A06G032_##_idx, \
-#define D_ROOT(_idx, _n, _mul, _div) \
+	.source = 1 + R9A06G032_##_src, \
-	{ .type = K_FFC, .index = R9A06G032_##_idx, .name = _n, \
+	.name = _n, \
-		.div = _div, .mul = _mul }
+	.gate = I_GATE(__VA_ARGS__) \
-#define D_FFC(_idx, _n, _src, _div) \
+}
-	{ .type = K_FFC, .index = R9A06G032_##_idx, \
+#define D_MODULE(_idx, _n, _src, ...) { \
-		.source = 1 + R9A06G032_##_src, .name = _n, \
+	.type = K_GATE, \
-		.div = _div, .mul = 1}
+	.index = R9A06G032_##_idx, \
-#define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) \
+	.source = 1 + R9A06G032_##_src, \
-	{ .type = K_DIV, .index = R9A06G032_##_idx, \
+	.name = _n, \
-		.source = 1 + R9A06G032_##_src, .name = _n, \
+	.managed = 1, \
-		.reg = _reg, .div_min = _min, .div_max = _max, \
+	.gate = I_GATE(__VA_ARGS__) \
-		.div_table = { __VA_ARGS__ } }
+}
-#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) \
+#define D_ROOT(_idx, _n, _mul, _div) { \
-	{ .type = K_DUALGATE, .index = R9A06G032_##_idx, \
+	.type = K_FFC, \
-		.source = 1 + R9A06G032_##_src, .name = _n, \
+	.index = R9A06G032_##_idx, \
-		.dual = { .group = _g, \
+	.name = _n, \
-			.g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, }
+	.div = _div, \
-
+	.mul = _mul \
-enum { K_GATE = 0, K_FFC, K_DIV, K_BITSEL, K_DUALGATE };
+}
+#define D_FFC(_idx, _n, _src, _div) { \
+	.type = K_FFC, \
+	.index = R9A06G032_##_idx, \
+	.source = 1 + R9A06G032_##_src, \
+	.name = _n, \
+	.div = _div, \
+	.mul = 1 \
+}
+#define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) { \
+	.type = K_DIV, \
+	.index = R9A06G032_##_idx, \
+	.source = 1 + R9A06G032_##_src, \
+	.name = _n, \
+	.reg = _reg, \
+	.div_min = _min, \
+	.div_max = _max, \
+	.div_table = { __VA_ARGS__ } \
+}
+#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) { \
+	.type = K_DUALGATE, \
+	.index = R9A06G032_##_idx, \
+	.source = 1 + R9A06G032_##_src, \
+	.name = _n, \
+	.dual = { \
+		.group = _g, \
+		.g1 = _g1, \
+		.r1 = _r1, \
+		.g2 = _g2, \
+		.r2 = _r2 \
+	}, \
+}
 
 /* Internal clock IDs */
 #define R9A06G032_CLKOUT		0