ARM: dts: DRA7: Add device nodes for ABB
Add ABB device nodes for DRA7 family of devices. Data is based on DRA7 Technical Reference Manual revision I (Sept 2013) Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Nishanth Menon
Tony Lindgren
Родитель
e12c77371e
Коммит
a1b8ee1058
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@ -578,6 +578,138 @@
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status = "disabled";
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};
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abb_mpu: regulator-abb-mpu {
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compatible = "ti,abb-v3";
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regulator-name = "abb_mpu";
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#address-cells = <0>;
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#size-cells = <0>;
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clocks = <&sys_clkin1>;
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ti,settling-time = <50>;
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ti,clock-cycles = <16>;
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reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
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<0x4ae06014 0x4>, <0x4a003b20 0x8>,
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<0x4ae0c158 0x4>;
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reg-names = "setup-address", "control-address",
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"int-address", "efuse-address",
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"ldo-address";
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ti,tranxdone-status-mask = <0x80>;
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/* LDOVBBMPU_FBB_MUX_CTRL */
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ti,ldovbb-override-mask = <0x400>;
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/* LDOVBBMPU_FBB_VSET_OUT */
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ti,ldovbb-vset-mask = <0x1F>;
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/*
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* NOTE: only FBB mode used but actual vset will
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* determine final biasing
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*/
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ti,abb_info = <
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/*uV ABB efuse rbb_m fbb_m vset_m*/
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1060000 0 0x0 0 0x02000000 0x01F00000
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1160000 0 0x4 0 0x02000000 0x01F00000
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1210000 0 0x8 0 0x02000000 0x01F00000
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>;
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};
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abb_ivahd: regulator-abb-ivahd {
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compatible = "ti,abb-v3";
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regulator-name = "abb_ivahd";
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#address-cells = <0>;
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#size-cells = <0>;
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clocks = <&sys_clkin1>;
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ti,settling-time = <50>;
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ti,clock-cycles = <16>;
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reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
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<0x4ae06010 0x4>, <0x4a0025cc 0x8>,
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<0x4a002470 0x4>;
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reg-names = "setup-address", "control-address",
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"int-address", "efuse-address",
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"ldo-address";
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ti,tranxdone-status-mask = <0x40000000>;
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/* LDOVBBIVA_FBB_MUX_CTRL */
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ti,ldovbb-override-mask = <0x400>;
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/* LDOVBBIVA_FBB_VSET_OUT */
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ti,ldovbb-vset-mask = <0x1F>;
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/*
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* NOTE: only FBB mode used but actual vset will
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* determine final biasing
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*/
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ti,abb_info = <
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/*uV ABB efuse rbb_m fbb_m vset_m*/
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1055000 0 0x0 0 0x02000000 0x01F00000
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1150000 0 0x4 0 0x02000000 0x01F00000
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1250000 0 0x8 0 0x02000000 0x01F00000
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>;
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};
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abb_dspeve: regulator-abb-dspeve {
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compatible = "ti,abb-v3";
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regulator-name = "abb_dspeve";
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#address-cells = <0>;
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#size-cells = <0>;
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clocks = <&sys_clkin1>;
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ti,settling-time = <50>;
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ti,clock-cycles = <16>;
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reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
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<0x4ae06010 0x4>, <0x4a0025e0 0x8>,
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<0x4a00246c 0x4>;
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reg-names = "setup-address", "control-address",
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"int-address", "efuse-address",
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"ldo-address";
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ti,tranxdone-status-mask = <0x20000000>;
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/* LDOVBBDSPEVE_FBB_MUX_CTRL */
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ti,ldovbb-override-mask = <0x400>;
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/* LDOVBBDSPEVE_FBB_VSET_OUT */
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ti,ldovbb-vset-mask = <0x1F>;
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/*
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* NOTE: only FBB mode used but actual vset will
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* determine final biasing
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*/
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ti,abb_info = <
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/*uV ABB efuse rbb_m fbb_m vset_m*/
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1055000 0 0x0 0 0x02000000 0x01F00000
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1150000 0 0x4 0 0x02000000 0x01F00000
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1250000 0 0x8 0 0x02000000 0x01F00000
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>;
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};
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abb_gpu: regulator-abb-gpu {
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compatible = "ti,abb-v3";
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regulator-name = "abb_gpu";
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#address-cells = <0>;
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#size-cells = <0>;
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clocks = <&sys_clkin1>;
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ti,settling-time = <50>;
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ti,clock-cycles = <16>;
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reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
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<0x4ae06010 0x4>, <0x4a003b08 0x8>,
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<0x4ae0c154 0x4>;
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reg-names = "setup-address", "control-address",
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"int-address", "efuse-address",
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"ldo-address";
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ti,tranxdone-status-mask = <0x10000000>;
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/* LDOVBBGPU_FBB_MUX_CTRL */
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ti,ldovbb-override-mask = <0x400>;
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/* LDOVBBGPU_FBB_VSET_OUT */
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ti,ldovbb-vset-mask = <0x1F>;
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/*
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* NOTE: only FBB mode used but actual vset will
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* determine final biasing
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*/
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ti,abb_info = <
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/*uV ABB efuse rbb_m fbb_m vset_m*/
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1090000 0 0x0 0 0x02000000 0x01F00000
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1210000 0 0x4 0 0x02000000 0x01F00000
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1280000 0 0x8 0 0x02000000 0x01F00000
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>;
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};
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mcspi1: spi@48098000 {
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compatible = "ti,omap4-mcspi";
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reg = <0x48098000 0x200>;
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