Merge tag 'drm-intel-next-2021-08-10-1' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
drm/i915 changes for v5.15: Features: - Basic DG2 platform enabling (Matt, Animesh, Gwan-gyeong, José) - Add PSF GV point support for display bandwidth calculation (Stan) - Add platform release id version support (Lucas) - Add support for forcing DSC BPP for testing (Vandita, Patnana) Refactoring and cleanups: - Remove CNL support completely (Lucas) - Revid/stepping cleanup (Matt, Anusha) - Make display stepping check upper bounds exclusive (Matt) - Remove old GEN macros (Lucas) - Refactor DG1 interrupt handler (Paulo) - Refactor DMC stepping info (Anusha) Fixes: - Fix XELPD color capability reporting; it's not yet enabled (Uma) - Fix DG1 memory bandwidth computation (Clint) - Fix mux on certain HP laptops (Kai-Heng) - Various display workarounds (José, Matt, Imre) - Fix error state dumps wrt SFC_DONE (Matt) - Fix DG1 and XEPLD audio power domains (Anshuman) - Fix ADL-P and ADL-S ddi buf translation tables (Matt) - Fix DP/HDMI modeset sequences causing issues on ADL-P (José) - PSR2 fixes (José) - Fix DP MST modeset with FEC on TGL+ - Fix MBUS DBOX A credits on ADL-P (José) - Fix DP PHY test training set programming (Khaled) - Fix dgfx pcode uncore init done wait (Badal) - Fix DSC disable fuse check on GLK (Lucas) - Fix shared dpll mismatch for bigjoiner secondary pipe (Manasi) - Fix ADL-P underrun recovery (Matt) - Fix permissions on FEC support debugfs file (Vandita) Misc: - Backmerge drm-next (Rodrigo) - Bump RKL and TGL DMC firmware version (Anusha) Signed-off-by: Dave Airlie <airlied@redhat.com> # Conflicts: # drivers/gpu/drm/i915/i915_drv.h # drivers/gpu/drm/i915/intel_device_info.h From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87a6lpo1a9.fsf@intel.com
This commit is contained in:
Dave Airlie
Коммит
a22c074fd1
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@ -269,6 +269,7 @@ i915-y += \
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display/intel_pps.o \
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display/intel_qp_tables.o \
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display/intel_sdvo.o \
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display/intel_snps_phy.o \
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display/intel_tv.o \
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display/intel_vdsc.o \
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display/intel_vrr.o \
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@ -912,7 +912,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
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zpos = 0;
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drm_plane_create_zpos_immutable_property(&plane->base, zpos);
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drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
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intel_plane_helper_add(plane);
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return plane;
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@ -19,6 +19,12 @@ static const guid_t intel_dsm_guid =
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GUID_INIT(0x7ed873d3, 0xc2d0, 0x4e4f,
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0xa8, 0x54, 0x0f, 0x13, 0x17, 0xb0, 0x1c, 0x2c);
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#define INTEL_DSM_FN_GET_BIOS_DATA_FUNCS_SUPPORTED 0 /* No args */
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static const guid_t intel_dsm_guid2 =
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GUID_INIT(0x3e5b41c6, 0xeb1d, 0x4260,
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0x9d, 0x15, 0xc7, 0x1f, 0xba, 0xda, 0xe4, 0x14);
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static char *intel_dsm_port_name(u8 id)
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{
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switch (id) {
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@ -176,6 +182,19 @@ void intel_unregister_dsm_handler(void)
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{
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}
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void intel_dsm_get_bios_data_funcs_supported(struct drm_i915_private *i915)
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{
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struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
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acpi_handle dhandle;
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dhandle = ACPI_HANDLE(&pdev->dev);
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if (!dhandle)
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return;
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acpi_evaluate_dsm(dhandle, &intel_dsm_guid2, INTEL_DSM_REVISION_ID,
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INTEL_DSM_FN_GET_BIOS_DATA_FUNCS_SUPPORTED, NULL);
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}
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/*
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* ACPI Specification, Revision 5.0, Appendix B.3.2 _DOD (Enumerate All Devices
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* Attached to the Display Adapter).
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@ -11,11 +11,14 @@ struct drm_i915_private;
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#ifdef CONFIG_ACPI
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void intel_register_dsm_handler(void);
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void intel_unregister_dsm_handler(void);
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void intel_dsm_get_bios_data_funcs_supported(struct drm_i915_private *i915);
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void intel_acpi_device_id_update(struct drm_i915_private *i915);
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#else
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static inline void intel_register_dsm_handler(void) { return; }
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static inline void intel_unregister_dsm_handler(void) { return; }
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static inline
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void intel_dsm_get_bios_data_funcs_supported(struct drm_i915_private *i915) { return; }
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static inline
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void intel_acpi_device_id_update(struct drm_i915_private *i915) { return; }
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#endif /* CONFIG_ACPI */
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@ -601,7 +601,12 @@ int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
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return 0;
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}
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const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
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static const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
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.prepare_fb = intel_prepare_plane_fb,
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.cleanup_fb = intel_cleanup_plane_fb,
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};
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void intel_plane_helper_add(struct intel_plane *plane)
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{
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drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
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}
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@ -17,8 +17,6 @@ struct intel_crtc_state;
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struct intel_plane;
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struct intel_plane_state;
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extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
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unsigned int intel_adjusted_rate(const struct drm_rect *src,
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const struct drm_rect *dst,
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unsigned int rate);
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@ -65,5 +63,6 @@ int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
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bool can_position);
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void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
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struct intel_plane_state *plane_state);
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void intel_plane_helper_add(struct intel_plane *plane);
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#endif /* __INTEL_ATOMIC_PLANE_H__ */
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@ -1001,7 +1001,7 @@ static unsigned long i915_audio_component_get_power(struct device *kdev)
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/* Catch potential impedance mismatches before they occur! */
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BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long));
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ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
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ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO_PLAYBACK);
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if (dev_priv->audio_power_refcount++ == 0) {
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if (DISPLAY_VER(dev_priv) >= 9) {
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@ -1034,7 +1034,7 @@ static void i915_audio_component_put_power(struct device *kdev,
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if (IS_GEMINILAKE(dev_priv))
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glk_force_audio_cdclk(dev_priv, false);
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intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie);
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intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO_PLAYBACK, cookie);
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}
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static void i915_audio_component_codec_wake_override(struct device *kdev,
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@ -1871,12 +1871,12 @@ intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata)
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static bool is_port_valid(struct drm_i915_private *i915, enum port port)
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{
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/*
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* On some ICL/CNL SKUs port F is not present, but broken VBTs mark
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* On some ICL SKUs port F is not present, but broken VBTs mark
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* the port as present. Only try to initialize port F for the
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* SKUs that may actually have it.
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*/
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if (port == PORT_F && (IS_ICELAKE(i915) || IS_CANNONLAKE(i915)))
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return IS_ICL_WITH_PORT_F(i915) || IS_CNL_WITH_PORT_F(i915);
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if (port == PORT_F && IS_ICELAKE(i915))
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return IS_ICL_WITH_PORT_F(i915);
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return true;
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}
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@ -1998,7 +1998,7 @@ static void parse_ddi_port(struct drm_i915_private *i915,
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"Port %c VBT HDMI boost level: %d\n",
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port_name(port), hdmi_boost_level);
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/* DP max link rate for CNL+ */
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/* DP max link rate for GLK+ */
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if (i915->vbt.version >= 216) {
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if (i915->vbt.version >= 230)
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info->dp_max_link_rate = parse_bdb_230_dp_max_link_rate(child->dp_max_link_rate);
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@ -2166,7 +2166,8 @@ static void
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init_vbt_missing_defaults(struct drm_i915_private *i915)
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{
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enum port port;
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int ports = PORT_A | PORT_B | PORT_C | PORT_D | PORT_E | PORT_F;
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int ports = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) |
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BIT(PORT_D) | BIT(PORT_E) | BIT(PORT_F);
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if (!HAS_DDI(i915) && !IS_CHERRYVIEW(i915))
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return;
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@ -17,12 +17,53 @@ struct intel_qgv_point {
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u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
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};
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struct intel_psf_gv_point {
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u8 clk; /* clock in multiples of 16.6666 MHz */
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};
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struct intel_qgv_info {
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struct intel_qgv_point points[I915_NUM_QGV_POINTS];
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struct intel_psf_gv_point psf_points[I915_NUM_PSF_GV_POINTS];
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u8 num_points;
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u8 num_psf_points;
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u8 t_bl;
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};
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static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
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struct intel_qgv_point *sp,
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int point)
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{
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u32 dclk_ratio, dclk_reference;
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u32 val;
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val = intel_uncore_read(&dev_priv->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC);
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dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val);
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if (val & DG1_QCLK_REFERENCE)
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dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */
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else
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dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */
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sp->dclk = dclk_ratio * dclk_reference;
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val = intel_uncore_read(&dev_priv->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
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if (val & DG1_GEAR_TYPE)
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sp->dclk *= 2;
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if (sp->dclk == 0)
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return -EINVAL;
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val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
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sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val);
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sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val);
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val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);
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sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val);
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sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val);
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sp->t_rc = sp->t_rp + sp->t_ras;
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return 0;
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}
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static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
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struct intel_qgv_point *sp,
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int point)
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@ -49,6 +90,28 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
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return 0;
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}
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static int adls_pcode_read_psf_gv_point_info(struct drm_i915_private *dev_priv,
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struct intel_psf_gv_point *points)
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{
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u32 val = 0;
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int ret;
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int i;
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ret = sandybridge_pcode_read(dev_priv,
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ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
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ADL_PCODE_MEM_SS_READ_PSF_GV_INFO,
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&val, NULL);
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if (ret)
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return ret;
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for (i = 0; i < I915_NUM_PSF_GV_POINTS; i++) {
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points[i].clk = val & 0xff;
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val >>= 8;
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}
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return 0;
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}
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int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
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u32 points_mask)
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{
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@ -62,7 +125,7 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
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1);
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if (ret < 0) {
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drm_err(&dev_priv->drm, "Failed to disable qgv points (%d)\n", ret);
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drm_err(&dev_priv->drm, "Failed to disable qgv points (%d) points: 0x%x\n", ret, points_mask);
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return ret;
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}
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@ -76,6 +139,7 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
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int i, ret;
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qi->num_points = dram_info->num_qgv_points;
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qi->num_psf_points = dram_info->num_psf_gv_points;
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if (DISPLAY_VER(dev_priv) == 12)
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switch (dram_info->type) {
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@ -99,7 +163,11 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
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for (i = 0; i < qi->num_points; i++) {
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struct intel_qgv_point *sp = &qi->points[i];
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ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i);
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if (IS_DG1(dev_priv))
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ret = dg1_mchbar_read_qgv_point_info(dev_priv, sp, i);
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else
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ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i);
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if (ret)
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return ret;
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@ -109,6 +177,19 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
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sp->t_rcd, sp->t_rc);
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}
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if (qi->num_psf_points > 0) {
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ret = adls_pcode_read_psf_gv_point_info(dev_priv, qi->psf_points);
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if (ret) {
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drm_err(&dev_priv->drm, "Failed to read PSF point data; PSF points will not be considered in bandwidth calculations.\n");
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qi->num_psf_points = 0;
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}
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for (i = 0; i < qi->num_psf_points; i++)
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drm_dbg_kms(&dev_priv->drm,
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"PSF GV %d: CLK=%d \n",
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i, qi->psf_points[i].clk);
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}
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return 0;
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}
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@ -118,6 +199,16 @@ static int icl_calc_bw(int dclk, int num, int den)
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return DIV_ROUND_CLOSEST(num * dclk * 100, den * 6);
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}
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static int adl_calc_psf_bw(int clk)
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{
|
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/*
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* clk is multiples of 16.666MHz (100/6)
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* According to BSpec PSF GV bandwidth is
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* calculated as BW = 64 * clk * 16.666Mhz
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*/
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return DIV_ROUND_CLOSEST(64 * clk * 100, 6);
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}
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static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
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{
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u16 dclk = 0;
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@ -194,6 +285,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
|
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bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
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bi->num_qgv_points = qi.num_points;
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bi->num_psf_gv_points = qi.num_psf_points;
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for (j = 0; j < qi.num_points; j++) {
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const struct intel_qgv_point *sp = &qi.points[j];
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@ -217,6 +309,16 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
|
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i, j, bi->num_planes, bi->deratedbw[j]);
|
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}
|
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|
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for (j = 0; j < qi.num_psf_points; j++) {
|
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const struct intel_psf_gv_point *sp = &qi.psf_points[j];
|
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|
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bi->psf_bw[j] = adl_calc_psf_bw(sp->clk);
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drm_dbg_kms(&dev_priv->drm,
|
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"BW%d / PSF GV %d: num_planes=%d bw=%u\n",
|
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i, j, bi->num_planes, bi->psf_bw[j]);
|
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}
|
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|
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if (bi->num_planes == 1)
|
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break;
|
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}
|
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|
|
@ -234,6 +336,26 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
|
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return 0;
|
||||
}
|
||||
|
||||
static void dg2_get_bw_info(struct drm_i915_private *i915)
|
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{
|
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struct intel_bw_info *bi = &i915->max_bw[0];
|
||||
|
||||
/*
|
||||
* DG2 doesn't have SAGV or QGV points, just a constant max bandwidth
|
||||
* that doesn't depend on the number of planes enabled. Create a
|
||||
* single dummy QGV point to reflect that. DG2-G10 platforms have a
|
||||
* constant 50 GB/s bandwidth, whereas DG2-G11 platforms have 38 GB/s.
|
||||
*/
|
||||
bi->num_planes = 1;
|
||||
bi->num_qgv_points = 1;
|
||||
if (IS_DG2_G11(i915))
|
||||
bi->deratedbw[0] = 38000;
|
||||
else
|
||||
bi->deratedbw[0] = 50000;
|
||||
|
||||
i915->sagv_status = I915_SAGV_NOT_CONTROLLED;
|
||||
}
|
||||
|
||||
static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
|
||||
int num_planes, int qgv_point)
|
||||
{
|
||||
|
|
@ -262,12 +384,23 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
|
||||
int psf_gv_point)
|
||||
{
|
||||
const struct intel_bw_info *bi =
|
||||
&dev_priv->max_bw[0];
|
||||
|
||||
return bi->psf_bw[psf_gv_point];
|
||||
}
|
||||
|
||||
void intel_bw_init_hw(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
if (!HAS_DISPLAY(dev_priv))
|
||||
return;
|
||||
|
||||
if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
|
||||
if (IS_DG2(dev_priv))
|
||||
dg2_get_bw_info(dev_priv);
|
||||
else if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
|
||||
icl_get_bw_info(dev_priv, &adls_sa_info);
|
||||
else if (IS_ROCKETLAKE(dev_priv))
|
||||
icl_get_bw_info(dev_priv, &rkl_sa_info);
|
||||
|
|
@ -534,12 +667,24 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
|
|||
u32 allowed_points = 0;
|
||||
unsigned int max_bw_point = 0, max_bw = 0;
|
||||
unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
|
||||
u32 mask = (1 << num_qgv_points) - 1;
|
||||
unsigned int num_psf_gv_points = dev_priv->max_bw[0].num_psf_gv_points;
|
||||
u32 mask = 0;
|
||||
|
||||
/* FIXME earlier gens need some checks too */
|
||||
if (DISPLAY_VER(dev_priv) < 11)
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* We can _not_ use the whole ADLS_QGV_PT_MASK here, as PCode rejects
|
||||
* it with failure if we try masking any unadvertised points.
|
||||
* So need to operate only with those returned from PCode.
|
||||
*/
|
||||
if (num_qgv_points > 0)
|
||||
mask |= REG_GENMASK(num_qgv_points - 1, 0);
|
||||
|
||||
if (num_psf_gv_points > 0)
|
||||
mask |= REG_GENMASK(num_psf_gv_points - 1, 0) << ADLS_PSF_PT_SHIFT;
|
||||
|
||||
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
|
||||
new_crtc_state, i) {
|
||||
unsigned int old_data_rate =
|
||||
|
|
@ -602,23 +747,44 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
|
|||
max_bw = max_data_rate;
|
||||
}
|
||||
if (max_data_rate >= data_rate)
|
||||
allowed_points |= BIT(i);
|
||||
allowed_points |= REG_FIELD_PREP(ADLS_QGV_PT_MASK, BIT(i));
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm, "QGV point %d: max bw %d required %d\n",
|
||||
i, max_data_rate, data_rate);
|
||||
}
|
||||
|
||||
for (i = 0; i < num_psf_gv_points; i++) {
|
||||
unsigned int max_data_rate = adl_psf_bw(dev_priv, i);
|
||||
|
||||
if (max_data_rate >= data_rate)
|
||||
allowed_points |= REG_FIELD_PREP(ADLS_PSF_PT_MASK, BIT(i));
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm, "PSF GV point %d: max bw %d"
|
||||
" required %d\n",
|
||||
i, max_data_rate, data_rate);
|
||||
}
|
||||
|
||||
/*
|
||||
* BSpec states that we always should have at least one allowed point
|
||||
* left, so if we couldn't - simply reject the configuration for obvious
|
||||
* reasons.
|
||||
*/
|
||||
if (allowed_points == 0) {
|
||||
if ((allowed_points & ADLS_QGV_PT_MASK) == 0) {
|
||||
drm_dbg_kms(&dev_priv->drm, "No QGV points provide sufficient memory"
|
||||
" bandwidth %d for display configuration(%d active planes).\n",
|
||||
data_rate, num_active_planes);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (num_psf_gv_points > 0) {
|
||||
if ((allowed_points & ADLS_PSF_PT_MASK) == 0) {
|
||||
drm_dbg_kms(&dev_priv->drm, "No PSF GV points provide sufficient memory"
|
||||
" bandwidth %d for display configuration(%d active planes).\n",
|
||||
data_rate, num_active_planes);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Leave only single point with highest bandwidth, if
|
||||
* we can't enable SAGV due to the increased memory latency it may
|
||||
|
|
|
|||
|
|
@ -1195,17 +1195,6 @@ static const struct intel_cdclk_vals glk_cdclk_table[] = {
|
|||
{}
|
||||
};
|
||||
|
||||
static const struct intel_cdclk_vals cnl_cdclk_table[] = {
|
||||
{ .refclk = 19200, .cdclk = 168000, .divider = 4, .ratio = 35 },
|
||||
{ .refclk = 19200, .cdclk = 336000, .divider = 2, .ratio = 35 },
|
||||
{ .refclk = 19200, .cdclk = 528000, .divider = 2, .ratio = 55 },
|
||||
|
||||
{ .refclk = 24000, .cdclk = 168000, .divider = 4, .ratio = 28 },
|
||||
{ .refclk = 24000, .cdclk = 336000, .divider = 2, .ratio = 28 },
|
||||
{ .refclk = 24000, .cdclk = 528000, .divider = 2, .ratio = 44 },
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct intel_cdclk_vals icl_cdclk_table[] = {
|
||||
{ .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
|
||||
{ .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
|
||||
|
|
@ -1290,6 +1279,16 @@ static const struct intel_cdclk_vals adlp_cdclk_table[] = {
|
|||
{}
|
||||
};
|
||||
|
||||
static const struct intel_cdclk_vals dg2_cdclk_table[] = {
|
||||
{ .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
|
||||
{ .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
|
||||
{ .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
|
||||
{ .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
|
||||
{ .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
|
||||
{ .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
|
||||
{}
|
||||
};
|
||||
|
||||
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
|
||||
{
|
||||
const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
|
||||
|
|
@ -1329,16 +1328,6 @@ static u8 bxt_calc_voltage_level(int cdclk)
|
|||
return DIV_ROUND_UP(cdclk, 25000);
|
||||
}
|
||||
|
||||
static u8 cnl_calc_voltage_level(int cdclk)
|
||||
{
|
||||
if (cdclk > 336000)
|
||||
return 2;
|
||||
else if (cdclk > 168000)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u8 icl_calc_voltage_level(int cdclk)
|
||||
{
|
||||
if (cdclk > 556800)
|
||||
|
|
@ -1373,15 +1362,6 @@ static u8 tgl_calc_voltage_level(int cdclk)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void cnl_readout_refclk(struct drm_i915_private *dev_priv,
|
||||
struct intel_cdclk_config *cdclk_config)
|
||||
{
|
||||
if (intel_de_read(dev_priv, SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
|
||||
cdclk_config->ref = 24000;
|
||||
else
|
||||
cdclk_config->ref = 19200;
|
||||
}
|
||||
|
||||
static void icl_readout_refclk(struct drm_i915_private *dev_priv,
|
||||
struct intel_cdclk_config *cdclk_config)
|
||||
{
|
||||
|
|
@ -1408,10 +1388,10 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
|
|||
{
|
||||
u32 val, ratio;
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 11)
|
||||
if (IS_DG2(dev_priv))
|
||||
cdclk_config->ref = 38400;
|
||||
else if (DISPLAY_VER(dev_priv) >= 11)
|
||||
icl_readout_refclk(dev_priv, cdclk_config);
|
||||
else if (IS_CANNONLAKE(dev_priv))
|
||||
cnl_readout_refclk(dev_priv, cdclk_config);
|
||||
else
|
||||
cdclk_config->ref = 19200;
|
||||
|
||||
|
|
@ -1427,11 +1407,11 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
|
|||
}
|
||||
|
||||
/*
|
||||
* CNL+ have the ratio directly in the PLL enable register, gen9lp had
|
||||
* it in a separate PLL control register.
|
||||
* DISPLAY_VER >= 11 have the ratio directly in the PLL enable register,
|
||||
* gen9lp had it in a separate PLL control register.
|
||||
*/
|
||||
if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
|
||||
ratio = val & CNL_CDCLK_PLL_RATIO_MASK;
|
||||
if (DISPLAY_VER(dev_priv) >= 11)
|
||||
ratio = val & ICL_CDCLK_PLL_RATIO_MASK;
|
||||
else
|
||||
ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
|
||||
|
||||
|
|
@ -1518,7 +1498,7 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
|
|||
dev_priv->cdclk.hw.vco = vco;
|
||||
}
|
||||
|
||||
static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
|
||||
static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE,
|
||||
BXT_DE_PLL_PLL_ENABLE, 0);
|
||||
|
|
@ -1530,12 +1510,12 @@ static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
|
|||
dev_priv->cdclk.hw.vco = 0;
|
||||
}
|
||||
|
||||
static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
|
||||
static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
|
||||
{
|
||||
int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
|
||||
u32 val;
|
||||
|
||||
val = CNL_CDCLK_PLL_RATIO(ratio);
|
||||
val = ICL_CDCLK_PLL_RATIO(ratio);
|
||||
intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
|
||||
|
||||
val |= BXT_DE_PLL_PLL_ENABLE;
|
||||
|
|
@ -1548,18 +1528,13 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
|
|||
dev_priv->cdclk.hw.vco = vco;
|
||||
}
|
||||
|
||||
static bool has_cdclk_crawl(struct drm_i915_private *i915)
|
||||
{
|
||||
return INTEL_INFO(i915)->has_cdclk_crawl;
|
||||
}
|
||||
|
||||
static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
|
||||
{
|
||||
int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
|
||||
u32 val;
|
||||
|
||||
/* Write PLL ratio without disabling */
|
||||
val = CNL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
|
||||
val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
|
||||
intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
|
||||
|
||||
/* Submit freq change request */
|
||||
|
|
@ -1628,7 +1603,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
|
|||
int ret;
|
||||
|
||||
/* Inform power controller of upcoming frequency change. */
|
||||
if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
|
||||
if (DISPLAY_VER(dev_priv) >= 11)
|
||||
ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
|
||||
SKL_CDCLK_PREPARE_FOR_CHANGE,
|
||||
SKL_CDCLK_READY_FOR_CHANGE,
|
||||
|
|
@ -1649,16 +1624,16 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
|
|||
return;
|
||||
}
|
||||
|
||||
if (has_cdclk_crawl(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {
|
||||
if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {
|
||||
if (dev_priv->cdclk.hw.vco != vco)
|
||||
adlp_cdclk_pll_crawl(dev_priv, vco);
|
||||
} else if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
|
||||
} else if (DISPLAY_VER(dev_priv) >= 11) {
|
||||
if (dev_priv->cdclk.hw.vco != 0 &&
|
||||
dev_priv->cdclk.hw.vco != vco)
|
||||
cnl_cdclk_pll_disable(dev_priv);
|
||||
icl_cdclk_pll_disable(dev_priv);
|
||||
|
||||
if (dev_priv->cdclk.hw.vco != vco)
|
||||
cnl_cdclk_pll_enable(dev_priv, vco);
|
||||
icl_cdclk_pll_enable(dev_priv, vco);
|
||||
} else {
|
||||
if (dev_priv->cdclk.hw.vco != 0 &&
|
||||
dev_priv->cdclk.hw.vco != vco)
|
||||
|
|
@ -1684,7 +1659,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
|
|||
if (pipe != INVALID_PIPE)
|
||||
intel_wait_for_vblank(dev_priv, pipe);
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
|
||||
if (DISPLAY_VER(dev_priv) >= 11) {
|
||||
ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
|
||||
cdclk_config->voltage_level);
|
||||
} else {
|
||||
|
|
@ -1709,7 +1684,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
|
|||
|
||||
intel_update_cdclk(dev_priv);
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
|
||||
if (DISPLAY_VER(dev_priv) >= 11)
|
||||
/*
|
||||
* Can't read out the voltage level :(
|
||||
* Let's just assume everything is as expected.
|
||||
|
|
@ -1857,7 +1832,7 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
|
|||
{
|
||||
int a_div, b_div;
|
||||
|
||||
if (!has_cdclk_crawl(dev_priv))
|
||||
if (!HAS_CDCLK_CRAWL(dev_priv))
|
||||
return false;
|
||||
|
||||
/*
|
||||
|
|
@ -2118,7 +2093,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
|
|||
crtc_state->port_clock >= 540000 &&
|
||||
crtc_state->lane_count == 4) {
|
||||
if (DISPLAY_VER(dev_priv) == 10) {
|
||||
/* Display WA #1145: glk,cnl */
|
||||
/* Display WA #1145: glk */
|
||||
min_cdclk = max(316800, min_cdclk);
|
||||
} else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) {
|
||||
/* Display WA #1144: skl,bxt */
|
||||
|
|
@ -2239,7 +2214,7 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
|
|||
|
||||
/*
|
||||
* Account for port clock min voltage level requirements.
|
||||
* This only really does something on CNL+ but can be
|
||||
* This only really does something on DISPLA_VER >= 11 but can be
|
||||
* called on earlier platforms as well.
|
||||
*
|
||||
* Note that this functions assumes that 0 is
|
||||
|
|
@ -2653,8 +2628,6 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
|
|||
dev_priv->max_cdclk_freq = 648000;
|
||||
else
|
||||
dev_priv->max_cdclk_freq = 652800;
|
||||
} else if (IS_CANNONLAKE(dev_priv)) {
|
||||
dev_priv->max_cdclk_freq = 528000;
|
||||
} else if (IS_GEMINILAKE(dev_priv)) {
|
||||
dev_priv->max_cdclk_freq = 316800;
|
||||
} else if (IS_BROXTON(dev_priv)) {
|
||||
|
|
@ -2878,13 +2851,19 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
|
|||
*/
|
||||
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
if (IS_ALDERLAKE_P(dev_priv)) {
|
||||
if (IS_DG2(dev_priv)) {
|
||||
dev_priv->display.set_cdclk = bxt_set_cdclk;
|
||||
dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
|
||||
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
|
||||
dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
|
||||
/* Wa_22011320316:adlp[a0] */
|
||||
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
|
||||
dev_priv->cdclk.table = dg2_cdclk_table;
|
||||
} else if (IS_ALDERLAKE_P(dev_priv)) {
|
||||
dev_priv->display.set_cdclk = bxt_set_cdclk;
|
||||
dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
|
||||
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
|
||||
dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
|
||||
/* Wa_22011320316:adl-p[a0] */
|
||||
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
|
||||
dev_priv->cdclk.table = adlp_a_step_cdclk_table;
|
||||
else
|
||||
dev_priv->cdclk.table = adlp_cdclk_table;
|
||||
|
|
@ -2912,12 +2891,6 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
|
|||
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
|
||||
dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
|
||||
dev_priv->cdclk.table = icl_cdclk_table;
|
||||
} else if (IS_CANNONLAKE(dev_priv)) {
|
||||
dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
|
||||
dev_priv->display.set_cdclk = bxt_set_cdclk;
|
||||
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
|
||||
dev_priv->display.calc_voltage_level = cnl_calc_voltage_level;
|
||||
dev_priv->cdclk.table = cnl_cdclk_table;
|
||||
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
|
||||
dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
|
||||
dev_priv->display.set_cdclk = bxt_set_cdclk;
|
||||
|
|
|
|||
|
|
@ -305,13 +305,12 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
|
|||
ilk_csc_postoff_limited_range);
|
||||
} else if (crtc_state->csc_enable) {
|
||||
/*
|
||||
* On GLK+ both pipe CSC and degamma LUT are controlled
|
||||
* On GLK both pipe CSC and degamma LUT are controlled
|
||||
* by csc_enable. Hence for the cases where the degama
|
||||
* LUT is needed but CSC is not we need to load an
|
||||
* identity matrix.
|
||||
*/
|
||||
drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) &&
|
||||
!IS_GEMINILAKE(dev_priv));
|
||||
drm_WARN_ON(&dev_priv->drm, !IS_GEMINILAKE(dev_priv));
|
||||
|
||||
ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
|
||||
ilk_csc_coeff_identity,
|
||||
|
|
|
|||
|
|
@ -23,9 +23,9 @@ enum {
|
|||
PROCMON_1_05V_DOT_1,
|
||||
};
|
||||
|
||||
static const struct cnl_procmon {
|
||||
static const struct icl_procmon {
|
||||
u32 dw1, dw9, dw10;
|
||||
} cnl_procmon_values[] = {
|
||||
} icl_procmon_values[] = {
|
||||
[PROCMON_0_85V_DOT_0] =
|
||||
{ .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
|
||||
[PROCMON_0_95V_DOT_0] =
|
||||
|
|
@ -38,15 +38,10 @@ static const struct cnl_procmon {
|
|||
{ .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
|
||||
};
|
||||
|
||||
/*
|
||||
* CNL has just one set of registers, while gen11 has a set for each combo PHY.
|
||||
* The CNL registers are equivalent to the gen11 PHY A registers, that's why we
|
||||
* call the ICL macros even though the function has CNL on its name.
|
||||
*/
|
||||
static const struct cnl_procmon *
|
||||
cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
|
||||
static const struct icl_procmon *
|
||||
icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
|
||||
{
|
||||
const struct cnl_procmon *procmon;
|
||||
const struct icl_procmon *procmon;
|
||||
u32 val;
|
||||
|
||||
val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy));
|
||||
|
|
@ -55,32 +50,32 @@ cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
|
|||
MISSING_CASE(val);
|
||||
fallthrough;
|
||||
case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
|
||||
procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];
|
||||
procmon = &icl_procmon_values[PROCMON_0_85V_DOT_0];
|
||||
break;
|
||||
case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:
|
||||
procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0];
|
||||
procmon = &icl_procmon_values[PROCMON_0_95V_DOT_0];
|
||||
break;
|
||||
case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:
|
||||
procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1];
|
||||
procmon = &icl_procmon_values[PROCMON_0_95V_DOT_1];
|
||||
break;
|
||||
case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:
|
||||
procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0];
|
||||
procmon = &icl_procmon_values[PROCMON_1_05V_DOT_0];
|
||||
break;
|
||||
case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:
|
||||
procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1];
|
||||
procmon = &icl_procmon_values[PROCMON_1_05V_DOT_1];
|
||||
break;
|
||||
}
|
||||
|
||||
return procmon;
|
||||
}
|
||||
|
||||
static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
|
||||
static void icl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
|
||||
enum phy phy)
|
||||
{
|
||||
const struct cnl_procmon *procmon;
|
||||
const struct icl_procmon *procmon;
|
||||
u32 val;
|
||||
|
||||
procmon = cnl_get_procmon_ref_values(dev_priv, phy);
|
||||
procmon = icl_get_procmon_ref_values(dev_priv, phy);
|
||||
|
||||
val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy));
|
||||
val &= ~((0xff << 16) | 0xff);
|
||||
|
|
@ -109,13 +104,13 @@ static bool check_phy_reg(struct drm_i915_private *dev_priv,
|
|||
return true;
|
||||
}
|
||||
|
||||
static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
|
||||
static bool icl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
|
||||
enum phy phy)
|
||||
{
|
||||
const struct cnl_procmon *procmon;
|
||||
const struct icl_procmon *procmon;
|
||||
bool ret;
|
||||
|
||||
procmon = cnl_get_procmon_ref_values(dev_priv, phy);
|
||||
procmon = icl_get_procmon_ref_values(dev_priv, phy);
|
||||
|
||||
ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
|
||||
(0xff << 16) | 0xff, procmon->dw1);
|
||||
|
|
@ -127,61 +122,6 @@ static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
|
|||
return ret;
|
||||
}
|
||||
|
||||
static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
return !(intel_de_read(dev_priv, CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) &&
|
||||
(intel_de_read(dev_priv, CNL_PORT_COMP_DW0) & COMP_INIT);
|
||||
}
|
||||
|
||||
static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
enum phy phy = PHY_A;
|
||||
bool ret;
|
||||
|
||||
if (!cnl_combo_phy_enabled(dev_priv))
|
||||
return false;
|
||||
|
||||
ret = cnl_verify_procmon_ref_values(dev_priv, phy);
|
||||
|
||||
ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5,
|
||||
CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void cnl_combo_phys_init(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = intel_de_read(dev_priv, CHICKEN_MISC_2);
|
||||
val &= ~CNL_COMP_PWR_DOWN;
|
||||
intel_de_write(dev_priv, CHICKEN_MISC_2, val);
|
||||
|
||||
/* Dummy PORT_A to get the correct CNL register from the ICL macro */
|
||||
cnl_set_procmon_ref_values(dev_priv, PHY_A);
|
||||
|
||||
val = intel_de_read(dev_priv, CNL_PORT_COMP_DW0);
|
||||
val |= COMP_INIT;
|
||||
intel_de_write(dev_priv, CNL_PORT_COMP_DW0, val);
|
||||
|
||||
val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
|
||||
val |= CL_POWER_DOWN_ENABLE;
|
||||
intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);
|
||||
}
|
||||
|
||||
static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
if (!cnl_combo_phy_verify_state(dev_priv))
|
||||
drm_warn(&dev_priv->drm,
|
||||
"Combo PHY HW state changed unexpectedly.\n");
|
||||
|
||||
val = intel_de_read(dev_priv, CHICKEN_MISC_2);
|
||||
val |= CNL_COMP_PWR_DOWN;
|
||||
intel_de_write(dev_priv, CHICKEN_MISC_2, val);
|
||||
}
|
||||
|
||||
static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
|
||||
{
|
||||
/*
|
||||
|
|
@ -291,7 +231,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
|
|||
DCC_MODE_SELECT_CONTINUOSLY);
|
||||
}
|
||||
|
||||
ret &= cnl_verify_procmon_ref_values(dev_priv, phy);
|
||||
ret &= icl_verify_procmon_ref_values(dev_priv, phy);
|
||||
|
||||
if (phy_is_master(dev_priv, phy)) {
|
||||
ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
|
||||
|
|
@ -415,7 +355,7 @@ skip_phy_misc:
|
|||
intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
|
||||
}
|
||||
|
||||
cnl_set_procmon_ref_values(dev_priv, phy);
|
||||
icl_set_procmon_ref_values(dev_priv, phy);
|
||||
|
||||
if (phy_is_master(dev_priv, phy)) {
|
||||
val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy));
|
||||
|
|
@ -474,16 +414,10 @@ skip_phy_misc:
|
|||
|
||||
void intel_combo_phy_init(struct drm_i915_private *i915)
|
||||
{
|
||||
if (DISPLAY_VER(i915) >= 11)
|
||||
icl_combo_phys_init(i915);
|
||||
else if (IS_CANNONLAKE(i915))
|
||||
cnl_combo_phys_init(i915);
|
||||
icl_combo_phys_init(i915);
|
||||
}
|
||||
|
||||
void intel_combo_phy_uninit(struct drm_i915_private *i915)
|
||||
{
|
||||
if (DISPLAY_VER(i915) >= 11)
|
||||
icl_combo_phys_uninit(i915);
|
||||
else if (IS_CANNONLAKE(i915))
|
||||
cnl_combo_phys_uninit(i915);
|
||||
icl_combo_phys_uninit(i915);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -335,7 +335,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
|
|||
dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc;
|
||||
}
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
|
||||
if (DISPLAY_VER(dev_priv) >= 11)
|
||||
drm_crtc_create_scaling_filter_property(&crtc->base,
|
||||
BIT(DRM_SCALING_FILTER_DEFAULT) |
|
||||
BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
|
||||
|
|
|
|||
|
|
@ -383,7 +383,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
|
|||
if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
|
||||
cntl |= MCURSOR_ROTATE_180;
|
||||
|
||||
/* Wa_22012358565:adlp */
|
||||
/* Wa_22012358565:adl-p */
|
||||
if (DISPLAY_VER(dev_priv) == 13)
|
||||
cntl |= MCURSOR_ARB_SLOTS(1);
|
||||
|
||||
|
|
@ -629,12 +629,16 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
|
|||
|
||||
/*
|
||||
* When crtc is inactive or there is a modeset pending,
|
||||
* wait for it to complete in the slowpath
|
||||
* wait for it to complete in the slowpath.
|
||||
* PSR2 selective fetch also requires the slow path as
|
||||
* PSR2 plane and transcoder registers can only be updated during
|
||||
* vblank.
|
||||
*
|
||||
* FIXME bigjoiner fastpath would be good
|
||||
*/
|
||||
if (!crtc_state->hw.active || intel_crtc_needs_modeset(crtc_state) ||
|
||||
crtc_state->update_pipe || crtc_state->bigjoiner)
|
||||
crtc_state->update_pipe || crtc_state->bigjoiner ||
|
||||
crtc_state->enable_psr2_sel_fetch)
|
||||
goto slow;
|
||||
|
||||
/*
|
||||
|
|
@ -801,7 +805,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
|
|||
if (DISPLAY_VER(dev_priv) >= 12)
|
||||
drm_plane_enable_fb_damage_clips(&cursor->base);
|
||||
|
||||
drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
|
||||
intel_plane_helper_add(cursor);
|
||||
|
||||
return cursor;
|
||||
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@
|
|||
#include "intel_panel.h"
|
||||
#include "intel_pps.h"
|
||||
#include "intel_psr.h"
|
||||
#include "intel_snps_phy.h"
|
||||
#include "intel_sprite.h"
|
||||
#include "intel_tc.h"
|
||||
#include "intel_vdsc.h"
|
||||
|
|
@ -171,14 +172,18 @@ void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
|
|||
static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
|
||||
enum port port)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
|
||||
if (DISPLAY_VER(dev_priv) < 10) {
|
||||
usleep_range(518, 1000);
|
||||
return;
|
||||
}
|
||||
|
||||
if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
|
||||
DDI_BUF_IS_IDLE), 500))
|
||||
ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
|
||||
DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10);
|
||||
|
||||
if (ret)
|
||||
drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",
|
||||
port_name(port));
|
||||
}
|
||||
|
|
@ -822,7 +827,7 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
|
|||
static enum intel_display_power_domain
|
||||
intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
|
||||
{
|
||||
/* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
|
||||
/* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
|
||||
* DC states enabled at the same time, while for driver initiated AUX
|
||||
* transfers we need the same AUX IOs to be powered but with DC states
|
||||
* disabled. Accordingly use the AUX power domain here which leaves DC
|
||||
|
|
@ -1017,126 +1022,6 @@ static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
|
|||
return DP_TRAIN_PRE_EMPH_LEVEL_3;
|
||||
}
|
||||
|
||||
static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
int level)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
const struct intel_ddi_buf_trans *ddi_translations;
|
||||
enum port port = encoder->port;
|
||||
int n_entries, ln;
|
||||
u32 val;
|
||||
|
||||
ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
|
||||
if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
|
||||
return;
|
||||
if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
|
||||
level = n_entries - 1;
|
||||
|
||||
/* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
|
||||
val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
|
||||
val &= ~SCALING_MODE_SEL_MASK;
|
||||
val |= SCALING_MODE_SEL(2);
|
||||
intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
|
||||
|
||||
/* Program PORT_TX_DW2 */
|
||||
val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port));
|
||||
val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
|
||||
RCOMP_SCALAR_MASK);
|
||||
val |= SWING_SEL_UPPER(ddi_translations->entries[level].cnl.dw2_swing_sel);
|
||||
val |= SWING_SEL_LOWER(ddi_translations->entries[level].cnl.dw2_swing_sel);
|
||||
/* Rcomp scalar is fixed as 0x98 for every table entry */
|
||||
val |= RCOMP_SCALAR(0x98);
|
||||
intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val);
|
||||
|
||||
/* Program PORT_TX_DW4 */
|
||||
/* We cannot write to GRP. It would overrite individual loadgen */
|
||||
for (ln = 0; ln < 4; ln++) {
|
||||
val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
|
||||
val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
|
||||
CURSOR_COEFF_MASK);
|
||||
val |= POST_CURSOR_1(ddi_translations->entries[level].cnl.dw4_post_cursor_1);
|
||||
val |= POST_CURSOR_2(ddi_translations->entries[level].cnl.dw4_post_cursor_2);
|
||||
val |= CURSOR_COEFF(ddi_translations->entries[level].cnl.dw4_cursor_coeff);
|
||||
intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
|
||||
}
|
||||
|
||||
/* Program PORT_TX_DW5 */
|
||||
/* All DW5 values are fixed for every table entry */
|
||||
val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
|
||||
val &= ~RTERM_SELECT_MASK;
|
||||
val |= RTERM_SELECT(6);
|
||||
val |= TAP3_DISABLE;
|
||||
intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
|
||||
|
||||
/* Program PORT_TX_DW7 */
|
||||
val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port));
|
||||
val &= ~N_SCALAR_MASK;
|
||||
val |= N_SCALAR(ddi_translations->entries[level].cnl.dw7_n_scalar);
|
||||
intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val);
|
||||
}
|
||||
|
||||
static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
int level)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
enum port port = encoder->port;
|
||||
int width, rate, ln;
|
||||
u32 val;
|
||||
|
||||
width = crtc_state->lane_count;
|
||||
rate = crtc_state->port_clock;
|
||||
|
||||
/*
|
||||
* 1. If port type is eDP or DP,
|
||||
* set PORT_PCS_DW1 cmnkeeper_enable to 1b,
|
||||
* else clear to 0b.
|
||||
*/
|
||||
val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port));
|
||||
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
|
||||
val &= ~COMMON_KEEPER_EN;
|
||||
else
|
||||
val |= COMMON_KEEPER_EN;
|
||||
intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val);
|
||||
|
||||
/* 2. Program loadgen select */
|
||||
/*
|
||||
* Program PORT_TX_DW4_LN depending on Bit rate and used lanes
|
||||
* <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
|
||||
* <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
|
||||
* > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
|
||||
*/
|
||||
for (ln = 0; ln <= 3; ln++) {
|
||||
val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
|
||||
val &= ~LOADGEN_SELECT;
|
||||
|
||||
if ((rate <= 600000 && width == 4 && ln >= 1) ||
|
||||
(rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
|
||||
val |= LOADGEN_SELECT;
|
||||
}
|
||||
intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
|
||||
}
|
||||
|
||||
/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
|
||||
val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
|
||||
val |= SUS_CLOCK_CONFIG;
|
||||
intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);
|
||||
|
||||
/* 4. Clear training enable to change swing values */
|
||||
val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
|
||||
val &= ~TX_TRAINING_EN;
|
||||
intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
|
||||
|
||||
/* 5. Program swing and de-emphasis */
|
||||
cnl_ddi_vswing_program(encoder, crtc_state, level);
|
||||
|
||||
/* 6. Set training enable to trigger update */
|
||||
val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
|
||||
val |= TX_TRAINING_EN;
|
||||
intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
|
||||
}
|
||||
|
||||
static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
int level)
|
||||
|
|
@ -1175,8 +1060,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
|
|||
val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
|
||||
val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
|
||||
RCOMP_SCALAR_MASK);
|
||||
val |= SWING_SEL_UPPER(ddi_translations->entries[level].cnl.dw2_swing_sel);
|
||||
val |= SWING_SEL_LOWER(ddi_translations->entries[level].cnl.dw2_swing_sel);
|
||||
val |= SWING_SEL_UPPER(ddi_translations->entries[level].icl.dw2_swing_sel);
|
||||
val |= SWING_SEL_LOWER(ddi_translations->entries[level].icl.dw2_swing_sel);
|
||||
/* Program Rcomp scalar for every table entry */
|
||||
val |= RCOMP_SCALAR(0x98);
|
||||
intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
|
||||
|
|
@ -1187,16 +1072,16 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
|
|||
val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
|
||||
val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
|
||||
CURSOR_COEFF_MASK);
|
||||
val |= POST_CURSOR_1(ddi_translations->entries[level].cnl.dw4_post_cursor_1);
|
||||
val |= POST_CURSOR_2(ddi_translations->entries[level].cnl.dw4_post_cursor_2);
|
||||
val |= CURSOR_COEFF(ddi_translations->entries[level].cnl.dw4_cursor_coeff);
|
||||
val |= POST_CURSOR_1(ddi_translations->entries[level].icl.dw4_post_cursor_1);
|
||||
val |= POST_CURSOR_2(ddi_translations->entries[level].icl.dw4_post_cursor_2);
|
||||
val |= CURSOR_COEFF(ddi_translations->entries[level].icl.dw4_cursor_coeff);
|
||||
intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
|
||||
}
|
||||
|
||||
/* Program PORT_TX_DW7 */
|
||||
val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
|
||||
val &= ~N_SCALAR_MASK;
|
||||
val |= N_SCALAR(ddi_translations->entries[level].cnl.dw7_n_scalar);
|
||||
val |= N_SCALAR(ddi_translations->entries[level].icl.dw7_n_scalar);
|
||||
intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
|
||||
}
|
||||
|
||||
|
|
@ -1495,6 +1380,16 @@ static int intel_ddi_dp_level(struct intel_dp *intel_dp)
|
|||
return translate_signal_level(intel_dp, signal_levels);
|
||||
}
|
||||
|
||||
static void
|
||||
dg2_set_signal_levels(struct intel_dp *intel_dp,
|
||||
const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
|
||||
int level = intel_ddi_dp_level(intel_dp);
|
||||
|
||||
intel_snps_phy_ddi_vswing_sequence(encoder, level);
|
||||
}
|
||||
|
||||
static void
|
||||
tgl_set_signal_levels(struct intel_dp *intel_dp,
|
||||
const struct intel_crtc_state *crtc_state)
|
||||
|
|
@ -1515,16 +1410,6 @@ icl_set_signal_levels(struct intel_dp *intel_dp,
|
|||
icl_ddi_vswing_sequence(encoder, crtc_state, level);
|
||||
}
|
||||
|
||||
static void
|
||||
cnl_set_signal_levels(struct intel_dp *intel_dp,
|
||||
const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
|
||||
int level = intel_ddi_dp_level(intel_dp);
|
||||
|
||||
cnl_ddi_vswing_sequence(encoder, crtc_state, level);
|
||||
}
|
||||
|
||||
static void
|
||||
bxt_set_signal_levels(struct intel_dp *intel_dp,
|
||||
const struct intel_crtc_state *crtc_state)
|
||||
|
|
@ -1560,7 +1445,7 @@ hsw_set_signal_levels(struct intel_dp *intel_dp,
|
|||
intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
|
||||
}
|
||||
|
||||
static void _cnl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
|
||||
static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
|
||||
u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
|
||||
{
|
||||
mutex_lock(&i915->dpll.lock);
|
||||
|
|
@ -1576,7 +1461,7 @@ static void _cnl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
|
|||
mutex_unlock(&i915->dpll.lock);
|
||||
}
|
||||
|
||||
static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
|
||||
static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
|
||||
u32 clk_off)
|
||||
{
|
||||
mutex_lock(&i915->dpll.lock);
|
||||
|
|
@ -1586,14 +1471,14 @@ static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg
|
|||
mutex_unlock(&i915->dpll.lock);
|
||||
}
|
||||
|
||||
static bool _cnl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
|
||||
static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
|
||||
u32 clk_off)
|
||||
{
|
||||
return !(intel_de_read(i915, reg) & clk_off);
|
||||
}
|
||||
|
||||
static struct intel_shared_dpll *
|
||||
_cnl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
|
||||
_icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
|
||||
u32 clk_sel_mask, u32 clk_sel_shift)
|
||||
{
|
||||
enum intel_dpll_id id;
|
||||
|
|
@ -1613,7 +1498,7 @@ static void adls_ddi_enable_clock(struct intel_encoder *encoder,
|
|||
if (drm_WARN_ON(&i915->drm, !pll))
|
||||
return;
|
||||
|
||||
_cnl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
|
||||
_icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
|
||||
ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
|
||||
pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
|
||||
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
||||
|
|
@ -1624,7 +1509,7 @@ static void adls_ddi_disable_clock(struct intel_encoder *encoder)
|
|||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
||||
|
||||
_cnl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
|
||||
_icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
|
||||
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
||||
}
|
||||
|
||||
|
|
@ -1633,7 +1518,7 @@ static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
|
|||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
||||
|
||||
return _cnl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy),
|
||||
return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy),
|
||||
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
||||
}
|
||||
|
||||
|
|
@ -1642,7 +1527,7 @@ static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
|
|||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
||||
|
||||
return _cnl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
|
||||
return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
|
||||
ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
|
||||
ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
|
||||
}
|
||||
|
|
@ -1657,7 +1542,7 @@ static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
|
|||
if (drm_WARN_ON(&i915->drm, !pll))
|
||||
return;
|
||||
|
||||
_cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
|
||||
_icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
|
||||
RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
|
||||
RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
|
||||
RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
||||
|
|
@ -1668,7 +1553,7 @@ static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
|
|||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
||||
|
||||
_cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
|
||||
_icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
|
||||
RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
||||
}
|
||||
|
||||
|
|
@ -1677,7 +1562,7 @@ static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
|
|||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
||||
|
||||
return _cnl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
|
||||
return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
|
||||
RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
||||
}
|
||||
|
||||
|
|
@ -1686,7 +1571,7 @@ static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
|
|||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
||||
|
||||
return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
|
||||
return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
|
||||
RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
|
||||
RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
|
||||
}
|
||||
|
|
@ -1710,7 +1595,7 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
|
|||
(pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
|
||||
return;
|
||||
|
||||
_cnl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
|
||||
_icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
|
||||
DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
|
||||
DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
|
||||
DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
||||
|
|
@ -1721,7 +1606,7 @@ static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
|
|||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
||||
|
||||
_cnl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
|
||||
_icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
|
||||
DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
||||
}
|
||||
|
||||
|
|
@ -1730,7 +1615,7 @@ static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
|
|||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
||||
|
||||
return _cnl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy),
|
||||
return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy),
|
||||
DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
||||
}
|
||||
|
||||
|
|
@ -1767,7 +1652,7 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
|
|||
if (drm_WARN_ON(&i915->drm, !pll))
|
||||
return;
|
||||
|
||||
_cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
|
||||
_icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
|
||||
ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
|
||||
ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
|
||||
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
||||
|
|
@ -1778,7 +1663,7 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
|
|||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
||||
|
||||
_cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
|
||||
_icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
|
||||
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
||||
}
|
||||
|
||||
|
|
@ -1787,7 +1672,7 @@ static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
|
|||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
||||
|
||||
return _cnl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
|
||||
return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
|
||||
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
||||
}
|
||||
|
||||
|
|
@ -1796,7 +1681,7 @@ struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
|
|||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
||||
|
||||
return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
|
||||
return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
|
||||
ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
|
||||
ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
|
||||
}
|
||||
|
|
@ -1929,50 +1814,6 @@ static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encode
|
|||
return intel_get_shared_dpll_by_id(i915, id);
|
||||
}
|
||||
|
||||
static void cnl_ddi_enable_clock(struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
|
||||
enum port port = encoder->port;
|
||||
|
||||
if (drm_WARN_ON(&i915->drm, !pll))
|
||||
return;
|
||||
|
||||
_cnl_ddi_enable_clock(i915, DPCLKA_CFGCR0,
|
||||
DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port),
|
||||
DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port),
|
||||
DPCLKA_CFGCR0_DDI_CLK_OFF(port));
|
||||
}
|
||||
|
||||
static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
enum port port = encoder->port;
|
||||
|
||||
_cnl_ddi_disable_clock(i915, DPCLKA_CFGCR0,
|
||||
DPCLKA_CFGCR0_DDI_CLK_OFF(port));
|
||||
}
|
||||
|
||||
static bool cnl_ddi_is_clock_enabled(struct intel_encoder *encoder)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
enum port port = encoder->port;
|
||||
|
||||
return _cnl_ddi_is_clock_enabled(i915, DPCLKA_CFGCR0,
|
||||
DPCLKA_CFGCR0_DDI_CLK_OFF(port));
|
||||
}
|
||||
|
||||
static struct intel_shared_dpll *cnl_ddi_get_pll(struct intel_encoder *encoder)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
enum port port = encoder->port;
|
||||
|
||||
return _cnl_ddi_get_pll(i915, DPCLKA_CFGCR0,
|
||||
DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port),
|
||||
DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port));
|
||||
}
|
||||
|
||||
static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
|
|
@ -2196,7 +2037,7 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
|
|||
ddi_clk_needed = false;
|
||||
}
|
||||
|
||||
if (ddi_clk_needed || !encoder->disable_clock ||
|
||||
if (ddi_clk_needed || !encoder->is_clock_enabled ||
|
||||
!encoder->is_clock_enabled(encoder))
|
||||
return;
|
||||
|
||||
|
|
@ -2477,6 +2318,116 @@ static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
|
|||
OVERLAP_PIXELS_MASK, dss1);
|
||||
}
|
||||
|
||||
static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state,
|
||||
struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
const struct drm_connector_state *conn_state)
|
||||
{
|
||||
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
|
||||
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
|
||||
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
|
||||
int level = intel_ddi_dp_level(intel_dp);
|
||||
|
||||
intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
|
||||
crtc_state->lane_count);
|
||||
|
||||
/*
|
||||
* 1. Enable Power Wells
|
||||
*
|
||||
* This was handled at the beginning of intel_atomic_commit_tail(),
|
||||
* before we called down into this function.
|
||||
*/
|
||||
|
||||
/* 2. Enable Panel Power if PPS is required */
|
||||
intel_pps_on(intel_dp);
|
||||
|
||||
/*
|
||||
* 3. Enable the port PLL.
|
||||
*/
|
||||
intel_ddi_enable_clock(encoder, crtc_state);
|
||||
|
||||
/* 4. Enable IO power */
|
||||
if (!intel_phy_is_tc(dev_priv, phy) ||
|
||||
dig_port->tc_mode != TC_PORT_TBT_ALT)
|
||||
dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
|
||||
dig_port->ddi_io_power_domain);
|
||||
|
||||
/*
|
||||
* 5. The rest of the below are substeps under the bspec's "Enable and
|
||||
* Train Display Port" step. Note that steps that are specific to
|
||||
* MST will be handled by intel_mst_pre_enable_dp() before/after it
|
||||
* calls into this function. Also intel_mst_pre_enable_dp() only calls
|
||||
* us when active_mst_links==0, so any steps designated for "single
|
||||
* stream or multi-stream master transcoder" can just be performed
|
||||
* unconditionally here.
|
||||
*/
|
||||
|
||||
/*
|
||||
* 5.a Configure Transcoder Clock Select to direct the Port clock to the
|
||||
* Transcoder.
|
||||
*/
|
||||
intel_ddi_enable_pipe_clock(encoder, crtc_state);
|
||||
|
||||
/* 5.b Not relevant to i915 for now */
|
||||
|
||||
/*
|
||||
* 5.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
|
||||
* Transport Select
|
||||
*/
|
||||
intel_ddi_config_transcoder_func(encoder, crtc_state);
|
||||
|
||||
/*
|
||||
* 5.d Configure & enable DP_TP_CTL with link training pattern 1
|
||||
* selected
|
||||
*
|
||||
* This will be handled by the intel_dp_start_link_train() farther
|
||||
* down this function.
|
||||
*/
|
||||
|
||||
/* 5.e Configure voltage swing and related IO settings */
|
||||
intel_snps_phy_ddi_vswing_sequence(encoder, level);
|
||||
|
||||
/*
|
||||
* 5.f Configure and enable DDI_BUF_CTL
|
||||
* 5.g Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
|
||||
* after 1200 us.
|
||||
*
|
||||
* We only configure what the register value will be here. Actual
|
||||
* enabling happens during link training farther down.
|
||||
*/
|
||||
intel_ddi_init_dp_buf_reg(encoder, crtc_state);
|
||||
|
||||
if (!is_mst)
|
||||
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
|
||||
|
||||
intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
|
||||
/*
|
||||
* DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
|
||||
* in the FEC_CONFIGURATION register to 1 before initiating link
|
||||
* training
|
||||
*/
|
||||
intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
|
||||
|
||||
/*
|
||||
* 5.h Follow DisplayPort specification training sequence (see notes for
|
||||
* failure handling)
|
||||
* 5.i If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
|
||||
* Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
|
||||
* (timeout after 800 us)
|
||||
*/
|
||||
intel_dp_start_link_train(intel_dp, crtc_state);
|
||||
|
||||
/* 5.j Set DP_TP_CTL link training to Normal */
|
||||
if (!is_trans_port_sync_mode(crtc_state))
|
||||
intel_dp_stop_link_train(intel_dp, crtc_state);
|
||||
|
||||
/* 5.k Configure and enable FEC if needed */
|
||||
intel_ddi_enable_fec(encoder, crtc_state);
|
||||
intel_dsc_enable(encoder, crtc_state);
|
||||
}
|
||||
|
||||
static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
|
||||
struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
|
|
@ -2657,8 +2608,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
|
|||
|
||||
if (DISPLAY_VER(dev_priv) >= 11)
|
||||
icl_ddi_vswing_sequence(encoder, crtc_state, level);
|
||||
else if (IS_CANNONLAKE(dev_priv))
|
||||
cnl_ddi_vswing_sequence(encoder, crtc_state, level);
|
||||
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
|
||||
bxt_ddi_vswing_sequence(encoder, crtc_state, level);
|
||||
else
|
||||
|
|
@ -2694,7 +2643,9 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
|
|||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 12)
|
||||
if (IS_DG2(dev_priv))
|
||||
dg2_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
|
||||
else if (DISPLAY_VER(dev_priv) >= 12)
|
||||
tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
|
||||
else
|
||||
hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
|
||||
|
|
@ -3101,12 +3052,12 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
|
|||
"[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
|
||||
connector->base.id, connector->name);
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 12)
|
||||
if (IS_DG2(dev_priv))
|
||||
intel_snps_phy_ddi_vswing_sequence(encoder, U32_MAX);
|
||||
else if (DISPLAY_VER(dev_priv) >= 12)
|
||||
tgl_ddi_vswing_sequence(encoder, crtc_state, level);
|
||||
else if (DISPLAY_VER(dev_priv) == 11)
|
||||
icl_ddi_vswing_sequence(encoder, crtc_state, level);
|
||||
else if (IS_CANNONLAKE(dev_priv))
|
||||
cnl_ddi_vswing_sequence(encoder, crtc_state, level);
|
||||
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
|
||||
bxt_ddi_vswing_sequence(encoder, crtc_state, level);
|
||||
else
|
||||
|
|
@ -3204,12 +3155,6 @@ static void intel_disable_ddi_dp(struct intel_atomic_state *state,
|
|||
|
||||
intel_dp->link_trained = false;
|
||||
|
||||
if (old_crtc_state->has_audio)
|
||||
intel_audio_codec_disable(encoder,
|
||||
old_crtc_state, old_conn_state);
|
||||
|
||||
intel_edp_drrs_disable(intel_dp, old_crtc_state);
|
||||
intel_psr_disable(intel_dp, old_crtc_state);
|
||||
intel_edp_backlight_off(old_conn_state);
|
||||
/* Disable the decompression in DP Sink */
|
||||
intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
|
||||
|
|
@ -3227,10 +3172,6 @@ static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
|
|||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
struct drm_connector *connector = old_conn_state->connector;
|
||||
|
||||
if (old_crtc_state->has_audio)
|
||||
intel_audio_codec_disable(encoder,
|
||||
old_crtc_state, old_conn_state);
|
||||
|
||||
if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
|
||||
false, false))
|
||||
drm_dbg_kms(&i915->drm,
|
||||
|
|
@ -3238,6 +3179,25 @@ static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
|
|||
connector->base.id, connector->name);
|
||||
}
|
||||
|
||||
static void intel_pre_disable_ddi(struct intel_atomic_state *state,
|
||||
struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *old_crtc_state,
|
||||
const struct drm_connector_state *old_conn_state)
|
||||
{
|
||||
struct intel_dp *intel_dp;
|
||||
|
||||
if (old_crtc_state->has_audio)
|
||||
intel_audio_codec_disable(encoder, old_crtc_state,
|
||||
old_conn_state);
|
||||
|
||||
if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
|
||||
return;
|
||||
|
||||
intel_dp = enc_to_intel_dp(encoder);
|
||||
intel_edp_drrs_disable(intel_dp, old_crtc_state);
|
||||
intel_psr_disable(intel_dp, old_crtc_state);
|
||||
}
|
||||
|
||||
static void intel_disable_ddi(struct intel_atomic_state *state,
|
||||
struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *old_crtc_state,
|
||||
|
|
@ -3454,7 +3414,7 @@ static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
|
|||
if (cpu_transcoder == TRANSCODER_EDP)
|
||||
return false;
|
||||
|
||||
if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
|
||||
if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO))
|
||||
return false;
|
||||
|
||||
return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
|
||||
|
|
@ -3470,8 +3430,6 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
|
|||
crtc_state->min_voltage_level = 3;
|
||||
else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)
|
||||
crtc_state->min_voltage_level = 1;
|
||||
else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
|
||||
crtc_state->min_voltage_level = 2;
|
||||
}
|
||||
|
||||
static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
|
||||
|
|
@ -3745,6 +3703,15 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
|
|||
&crtc_state->dpll_hw_state);
|
||||
}
|
||||
|
||||
static void dg2_ddi_get_config(struct intel_encoder *encoder,
|
||||
struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state);
|
||||
crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state);
|
||||
|
||||
intel_ddi_get_config(encoder, crtc_state);
|
||||
}
|
||||
|
||||
static void adls_ddi_get_config(struct intel_encoder *encoder,
|
||||
struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
|
|
@ -3812,13 +3779,6 @@ static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
|
|||
intel_ddi_get_config(encoder, crtc_state);
|
||||
}
|
||||
|
||||
static void cnl_ddi_get_config(struct intel_encoder *encoder,
|
||||
struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
intel_ddi_get_clock(encoder, crtc_state, cnl_ddi_get_pll(encoder));
|
||||
intel_ddi_get_config(encoder, crtc_state);
|
||||
}
|
||||
|
||||
static void bxt_ddi_get_config(struct intel_encoder *encoder,
|
||||
struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
|
|
@ -4065,12 +4025,12 @@ intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
|
|||
dig_port->dp.set_link_train = intel_ddi_set_link_train;
|
||||
dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 12)
|
||||
if (IS_DG2(dev_priv))
|
||||
dig_port->dp.set_signal_levels = dg2_set_signal_levels;
|
||||
else if (DISPLAY_VER(dev_priv) >= 12)
|
||||
dig_port->dp.set_signal_levels = tgl_set_signal_levels;
|
||||
else if (DISPLAY_VER(dev_priv) >= 11)
|
||||
dig_port->dp.set_signal_levels = icl_set_signal_levels;
|
||||
else if (IS_CANNONLAKE(dev_priv))
|
||||
dig_port->dp.set_signal_levels = cnl_set_signal_levels;
|
||||
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
|
||||
dig_port->dp.set_signal_levels = bxt_set_signal_levels;
|
||||
else
|
||||
|
|
@ -4317,15 +4277,6 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
|
|||
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
|
||||
return true;
|
||||
|
||||
/* Cannonlake: Most of SKUs don't support DDI_E, and the only
|
||||
* one who does also have a full A/E split called
|
||||
* DDI_F what makes DDI_E useless. However for this
|
||||
* case let's trust VBT info.
|
||||
*/
|
||||
if (IS_CANNONLAKE(dev_priv) &&
|
||||
!intel_bios_is_port_present(dev_priv, PORT_E))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
@ -4430,15 +4381,6 @@ static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv,
|
|||
return HPD_PORT_A + port - PORT_A;
|
||||
}
|
||||
|
||||
static enum hpd_pin cnl_hpd_pin(struct drm_i915_private *dev_priv,
|
||||
enum port port)
|
||||
{
|
||||
if (port == PORT_F)
|
||||
return HPD_PORT_E;
|
||||
|
||||
return HPD_PORT_A + port - PORT_A;
|
||||
}
|
||||
|
||||
static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port)
|
||||
{
|
||||
if (HAS_PCH_TGP(dev_priv))
|
||||
|
|
@ -4590,6 +4532,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
|
|||
encoder->enable = intel_enable_ddi;
|
||||
encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
|
||||
encoder->pre_enable = intel_ddi_pre_enable;
|
||||
encoder->pre_disable = intel_pre_disable_ddi;
|
||||
encoder->disable = intel_disable_ddi;
|
||||
encoder->post_disable = intel_ddi_post_disable;
|
||||
encoder->update_pipe = intel_ddi_update_pipe;
|
||||
|
|
@ -4606,7 +4549,11 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
|
|||
encoder->cloneable = 0;
|
||||
encoder->pipe_mask = ~0;
|
||||
|
||||
if (IS_ALDERLAKE_S(dev_priv)) {
|
||||
if (IS_DG2(dev_priv)) {
|
||||
encoder->enable_clock = intel_mpllb_enable;
|
||||
encoder->disable_clock = intel_mpllb_disable;
|
||||
encoder->get_config = dg2_ddi_get_config;
|
||||
} else if (IS_ALDERLAKE_S(dev_priv)) {
|
||||
encoder->enable_clock = adls_ddi_enable_clock;
|
||||
encoder->disable_clock = adls_ddi_disable_clock;
|
||||
encoder->is_clock_enabled = adls_ddi_is_clock_enabled;
|
||||
|
|
@ -4645,11 +4592,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
|
|||
encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
|
||||
encoder->get_config = icl_ddi_combo_get_config;
|
||||
}
|
||||
} else if (IS_CANNONLAKE(dev_priv)) {
|
||||
encoder->enable_clock = cnl_ddi_enable_clock;
|
||||
encoder->disable_clock = cnl_ddi_disable_clock;
|
||||
encoder->is_clock_enabled = cnl_ddi_is_clock_enabled;
|
||||
encoder->get_config = cnl_ddi_get_config;
|
||||
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
|
||||
/* BXT/GLK have fixed PLL->port mapping */
|
||||
encoder->get_config = bxt_ddi_get_config;
|
||||
|
|
@ -4679,8 +4621,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
|
|||
encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
|
||||
else if (DISPLAY_VER(dev_priv) == 11)
|
||||
encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
|
||||
else if (IS_CANNONLAKE(dev_priv))
|
||||
encoder->hpd_pin = cnl_hpd_pin(dev_priv, port);
|
||||
else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
|
||||
encoder->hpd_pin = skl_hpd_pin(dev_priv, port);
|
||||
else
|
||||
|
|
|
|||
|
|
@ -417,199 +417,19 @@ static const struct intel_ddi_buf_trans bxt_ddi_translations_hdmi = {
|
|||
.hdmi_default_entry = ARRAY_SIZE(_bxt_ddi_translations_hdmi) - 1,
|
||||
};
|
||||
|
||||
/* Voltage Swing Programming for VccIO 0.85V for DP */
|
||||
static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_dp_0_85V[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0xA, 0x5D, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .cnl = { 0xA, 0x6A, 0x38, 0x00, 0x07 } }, /* 350 500 3.1 */
|
||||
{ .cnl = { 0xB, 0x7A, 0x32, 0x00, 0x0D } }, /* 350 700 6.0 */
|
||||
{ .cnl = { 0x6, 0x7C, 0x2D, 0x00, 0x12 } }, /* 350 900 8.2 */
|
||||
{ .cnl = { 0xA, 0x69, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .cnl = { 0xB, 0x7A, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */
|
||||
{ .cnl = { 0x6, 0x7C, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */
|
||||
{ .cnl = { 0xB, 0x7D, 0x3C, 0x00, 0x03 } }, /* 650 725 0.9 */
|
||||
{ .cnl = { 0x6, 0x7C, 0x34, 0x00, 0x0B } }, /* 600 900 3.5 */
|
||||
{ .cnl = { 0x6, 0x7B, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans cnl_ddi_translations_dp_0_85V = {
|
||||
.entries = _cnl_ddi_translations_dp_0_85V,
|
||||
.num_entries = ARRAY_SIZE(_cnl_ddi_translations_dp_0_85V),
|
||||
};
|
||||
|
||||
/* Voltage Swing Programming for VccIO 0.85V for HDMI */
|
||||
static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_0_85V[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0 */
|
||||
{ .cnl = { 0xB, 0x73, 0x36, 0x00, 0x09 } }, /* 450 650 3.2 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } }, /* 450 850 5.5 */
|
||||
{ .cnl = { 0xB, 0x73, 0x3F, 0x00, 0x00 } }, /* 650 650 0.0 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 650 850 2.3 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 850 850 0.0 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V = {
|
||||
.entries = _cnl_ddi_translations_hdmi_0_85V,
|
||||
.num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_85V),
|
||||
.hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_85V) - 1,
|
||||
};
|
||||
|
||||
/* Voltage Swing Programming for VccIO 0.85V for eDP */
|
||||
static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_edp_0_85V[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0xA, 0x66, 0x3A, 0x00, 0x05 } }, /* 384 500 2.3 */
|
||||
{ .cnl = { 0x0, 0x7F, 0x38, 0x00, 0x07 } }, /* 153 200 2.3 */
|
||||
{ .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 192 250 2.3 */
|
||||
{ .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 230 300 2.3 */
|
||||
{ .cnl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } }, /* 269 350 2.3 */
|
||||
{ .cnl = { 0xA, 0x66, 0x3C, 0x00, 0x03 } }, /* 446 500 1.0 */
|
||||
{ .cnl = { 0xB, 0x70, 0x3C, 0x00, 0x03 } }, /* 460 600 2.3 */
|
||||
{ .cnl = { 0xC, 0x75, 0x3C, 0x00, 0x03 } }, /* 537 700 2.3 */
|
||||
{ .cnl = { 0x2, 0x7F, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans cnl_ddi_translations_edp_0_85V = {
|
||||
.entries = _cnl_ddi_translations_edp_0_85V,
|
||||
.num_entries = ARRAY_SIZE(_cnl_ddi_translations_edp_0_85V),
|
||||
};
|
||||
|
||||
/* Voltage Swing Programming for VccIO 0.95V for DP */
|
||||
static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_dp_0_95V[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0xA, 0x5D, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .cnl = { 0xA, 0x6A, 0x38, 0x00, 0x07 } }, /* 350 500 3.1 */
|
||||
{ .cnl = { 0xB, 0x7A, 0x32, 0x00, 0x0D } }, /* 350 700 6.0 */
|
||||
{ .cnl = { 0x6, 0x7C, 0x2D, 0x00, 0x12 } }, /* 350 900 8.2 */
|
||||
{ .cnl = { 0xA, 0x69, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .cnl = { 0xB, 0x7A, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */
|
||||
{ .cnl = { 0x6, 0x7C, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */
|
||||
{ .cnl = { 0xB, 0x7D, 0x3C, 0x00, 0x03 } }, /* 650 725 0.9 */
|
||||
{ .cnl = { 0x6, 0x7C, 0x34, 0x00, 0x0B } }, /* 600 900 3.5 */
|
||||
{ .cnl = { 0x6, 0x7B, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans cnl_ddi_translations_dp_0_95V = {
|
||||
.entries = _cnl_ddi_translations_dp_0_95V,
|
||||
.num_entries = ARRAY_SIZE(_cnl_ddi_translations_dp_0_95V),
|
||||
};
|
||||
|
||||
/* Voltage Swing Programming for VccIO 0.95V for HDMI */
|
||||
static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_0_95V[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0xA, 0x5C, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */
|
||||
{ .cnl = { 0xB, 0x69, 0x37, 0x00, 0x08 } }, /* 400 600 3.5 */
|
||||
{ .cnl = { 0x5, 0x76, 0x31, 0x00, 0x0E } }, /* 400 800 6.0 */
|
||||
{ .cnl = { 0xA, 0x5E, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0 */
|
||||
{ .cnl = { 0xB, 0x69, 0x3F, 0x00, 0x00 } }, /* 600 600 0.0 */
|
||||
{ .cnl = { 0xB, 0x79, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */
|
||||
{ .cnl = { 0x6, 0x7D, 0x32, 0x00, 0x0D } }, /* 600 1000 4.4 */
|
||||
{ .cnl = { 0x5, 0x76, 0x3F, 0x00, 0x00 } }, /* 800 800 0.0 */
|
||||
{ .cnl = { 0x6, 0x7D, 0x39, 0x00, 0x06 } }, /* 800 1000 1.9 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x39, 0x00, 0x06 } }, /* 850 1050 1.8 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1050 1050 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V = {
|
||||
.entries = _cnl_ddi_translations_hdmi_0_95V,
|
||||
.num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_95V),
|
||||
.hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_95V) - 1,
|
||||
};
|
||||
|
||||
/* Voltage Swing Programming for VccIO 0.95V for eDP */
|
||||
static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_edp_0_95V[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0xA, 0x61, 0x3A, 0x00, 0x05 } }, /* 384 500 2.3 */
|
||||
{ .cnl = { 0x0, 0x7F, 0x38, 0x00, 0x07 } }, /* 153 200 2.3 */
|
||||
{ .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 192 250 2.3 */
|
||||
{ .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 230 300 2.3 */
|
||||
{ .cnl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } }, /* 269 350 2.3 */
|
||||
{ .cnl = { 0xA, 0x61, 0x3C, 0x00, 0x03 } }, /* 446 500 1.0 */
|
||||
{ .cnl = { 0xB, 0x68, 0x39, 0x00, 0x06 } }, /* 460 600 2.3 */
|
||||
{ .cnl = { 0xC, 0x6E, 0x39, 0x00, 0x06 } }, /* 537 700 2.3 */
|
||||
{ .cnl = { 0x4, 0x7F, 0x3A, 0x00, 0x05 } }, /* 460 600 2.3 */
|
||||
{ .cnl = { 0x2, 0x7F, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans cnl_ddi_translations_edp_0_95V = {
|
||||
.entries = _cnl_ddi_translations_edp_0_95V,
|
||||
.num_entries = ARRAY_SIZE(_cnl_ddi_translations_edp_0_95V),
|
||||
};
|
||||
|
||||
/* Voltage Swing Programming for VccIO 1.05V for DP */
|
||||
static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_dp_1_05V[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0xA, 0x58, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */
|
||||
{ .cnl = { 0xB, 0x64, 0x37, 0x00, 0x08 } }, /* 400 600 3.5 */
|
||||
{ .cnl = { 0x5, 0x70, 0x31, 0x00, 0x0E } }, /* 400 800 6.0 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 400 1050 8.4 */
|
||||
{ .cnl = { 0xB, 0x64, 0x3F, 0x00, 0x00 } }, /* 600 600 0.0 */
|
||||
{ .cnl = { 0x5, 0x73, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 550 1050 5.6 */
|
||||
{ .cnl = { 0x5, 0x76, 0x3E, 0x00, 0x01 } }, /* 850 900 0.5 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x36, 0x00, 0x09 } }, /* 750 1050 2.9 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1050 1050 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans cnl_ddi_translations_dp_1_05V = {
|
||||
.entries = _cnl_ddi_translations_dp_1_05V,
|
||||
.num_entries = ARRAY_SIZE(_cnl_ddi_translations_dp_1_05V),
|
||||
};
|
||||
|
||||
/* Voltage Swing Programming for VccIO 1.05V for HDMI */
|
||||
static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_1_05V[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0xA, 0x58, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */
|
||||
{ .cnl = { 0xB, 0x64, 0x37, 0x00, 0x08 } }, /* 400 600 3.5 */
|
||||
{ .cnl = { 0x5, 0x70, 0x31, 0x00, 0x0E } }, /* 400 800 6.0 */
|
||||
{ .cnl = { 0xA, 0x5B, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0 */
|
||||
{ .cnl = { 0xB, 0x64, 0x3F, 0x00, 0x00 } }, /* 600 600 0.0 */
|
||||
{ .cnl = { 0x5, 0x73, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */
|
||||
{ .cnl = { 0x6, 0x7C, 0x32, 0x00, 0x0D } }, /* 600 1000 4.4 */
|
||||
{ .cnl = { 0x5, 0x70, 0x3F, 0x00, 0x00 } }, /* 800 800 0.0 */
|
||||
{ .cnl = { 0x6, 0x7C, 0x39, 0x00, 0x06 } }, /* 800 1000 1.9 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x39, 0x00, 0x06 } }, /* 850 1050 1.8 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1050 1050 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V = {
|
||||
.entries = _cnl_ddi_translations_hdmi_1_05V,
|
||||
.num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_1_05V),
|
||||
.hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_1_05V) - 1,
|
||||
};
|
||||
|
||||
/* Voltage Swing Programming for VccIO 1.05V for eDP */
|
||||
static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_edp_1_05V[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0xA, 0x5E, 0x3A, 0x00, 0x05 } }, /* 384 500 2.3 */
|
||||
{ .cnl = { 0x0, 0x7F, 0x38, 0x00, 0x07 } }, /* 153 200 2.3 */
|
||||
{ .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 192 250 2.3 */
|
||||
{ .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 230 300 2.3 */
|
||||
{ .cnl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } }, /* 269 350 2.3 */
|
||||
{ .cnl = { 0xA, 0x5E, 0x3C, 0x00, 0x03 } }, /* 446 500 1.0 */
|
||||
{ .cnl = { 0xB, 0x64, 0x39, 0x00, 0x06 } }, /* 460 600 2.3 */
|
||||
{ .cnl = { 0xE, 0x6A, 0x39, 0x00, 0x06 } }, /* 537 700 2.3 */
|
||||
{ .cnl = { 0x2, 0x7F, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans cnl_ddi_translations_edp_1_05V = {
|
||||
.entries = _cnl_ddi_translations_edp_1_05V,
|
||||
.num_entries = ARRAY_SIZE(_cnl_ddi_translations_edp_1_05V),
|
||||
};
|
||||
|
||||
/* icl_combo_phy_ddi_translations */
|
||||
static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
|
||||
{ .cnl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */
|
||||
{ .cnl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .cnl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
|
||||
{ .cnl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
|
||||
{ .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
|
||||
{ .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */
|
||||
{ .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
|
||||
{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
|
||||
{ .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */
|
||||
{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3 = {
|
||||
|
|
@ -619,16 +439,16 @@ static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2_e
|
|||
|
||||
static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_edp_hbr2[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0x0, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */
|
||||
{ .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 200 250 1.9 */
|
||||
{ .cnl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } }, /* 200 300 3.5 */
|
||||
{ .cnl = { 0x9, 0x7F, 0x31, 0x00, 0x0E } }, /* 200 350 4.9 */
|
||||
{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */
|
||||
{ .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */
|
||||
{ .cnl = { 0x9, 0x7F, 0x35, 0x00, 0x0A } }, /* 250 350 2.9 */
|
||||
{ .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */
|
||||
{ .cnl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */
|
||||
{ .cnl = { 0x9, 0x7F, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .icl = { 0x0, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */
|
||||
{ .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 200 250 1.9 */
|
||||
{ .icl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } }, /* 200 300 3.5 */
|
||||
{ .icl = { 0x9, 0x7F, 0x31, 0x00, 0x0E } }, /* 200 350 4.9 */
|
||||
{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */
|
||||
{ .icl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */
|
||||
{ .icl = { 0x9, 0x7F, 0x35, 0x00, 0x0A } }, /* 250 350 2.9 */
|
||||
{ .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */
|
||||
{ .icl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */
|
||||
{ .icl = { 0x9, 0x7F, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2 = {
|
||||
|
|
@ -638,13 +458,13 @@ static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2
|
|||
|
||||
static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_hdmi[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0 */
|
||||
{ .cnl = { 0xB, 0x73, 0x36, 0x00, 0x09 } }, /* 450 650 3.2 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } }, /* 450 850 5.5 */
|
||||
{ .cnl = { 0xB, 0x73, 0x3F, 0x00, 0x00 } }, /* 650 650 0.0 ALS */
|
||||
{ .cnl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 650 850 2.3 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 850 850 0.0 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */
|
||||
{ .icl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0 */
|
||||
{ .icl = { 0xB, 0x73, 0x36, 0x00, 0x09 } }, /* 450 650 3.2 */
|
||||
{ .icl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } }, /* 450 850 5.5 */
|
||||
{ .icl = { 0xB, 0x73, 0x3F, 0x00, 0x00 } }, /* 650 650 0.0 ALS */
|
||||
{ .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 650 850 2.3 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 850 850 0.0 */
|
||||
{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi = {
|
||||
|
|
@ -655,16 +475,16 @@ static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi = {
|
|||
|
||||
static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_dp[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0xA, 0x33, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .cnl = { 0xA, 0x47, 0x36, 0x00, 0x09 } }, /* 350 500 3.1 */
|
||||
{ .cnl = { 0xC, 0x64, 0x34, 0x00, 0x0B } }, /* 350 700 6.0 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 350 900 8.2 */
|
||||
{ .cnl = { 0xA, 0x46, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .cnl = { 0xC, 0x64, 0x38, 0x00, 0x07 } }, /* 500 700 2.9 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */
|
||||
{ .cnl = { 0xC, 0x61, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } }, /* 600 900 3.5 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
{ .icl = { 0xA, 0x33, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .icl = { 0xA, 0x47, 0x36, 0x00, 0x09 } }, /* 350 500 3.1 */
|
||||
{ .icl = { 0xC, 0x64, 0x34, 0x00, 0x0B } }, /* 350 700 6.0 */
|
||||
{ .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 350 900 8.2 */
|
||||
{ .icl = { 0xA, 0x46, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .icl = { 0xC, 0x64, 0x38, 0x00, 0x07 } }, /* 500 700 2.9 */
|
||||
{ .icl = { 0x6, 0x7F, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */
|
||||
{ .icl = { 0xC, 0x61, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
|
||||
{ .icl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } }, /* 600 900 3.5 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_dp = {
|
||||
|
|
@ -674,16 +494,16 @@ static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_dp = {
|
|||
|
||||
static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_edp_hbr2[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */
|
||||
{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 250 1.9 */
|
||||
{ .cnl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } }, /* 200 300 3.5 */
|
||||
{ .cnl = { 0xA, 0x35, 0x39, 0x00, 0x06 } }, /* 200 350 4.9 */
|
||||
{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */
|
||||
{ .cnl = { 0x1, 0x7F, 0x3C, 0x00, 0x03 } }, /* 250 300 1.6 */
|
||||
{ .cnl = { 0xA, 0x35, 0x39, 0x00, 0x06 } }, /* 250 350 2.9 */
|
||||
{ .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */
|
||||
{ .cnl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */
|
||||
{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */
|
||||
{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 250 1.9 */
|
||||
{ .icl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } }, /* 200 300 3.5 */
|
||||
{ .icl = { 0xA, 0x35, 0x39, 0x00, 0x06 } }, /* 200 350 4.9 */
|
||||
{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */
|
||||
{ .icl = { 0x1, 0x7F, 0x3C, 0x00, 0x03 } }, /* 250 300 1.6 */
|
||||
{ .icl = { 0xA, 0x35, 0x39, 0x00, 0x06 } }, /* 250 350 2.9 */
|
||||
{ .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */
|
||||
{ .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */
|
||||
{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_edp_hbr2 = {
|
||||
|
|
@ -693,16 +513,16 @@ static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_edp_hbr2
|
|||
|
||||
static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp_hbr[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */
|
||||
{ .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 200 250 1.9 */
|
||||
{ .cnl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } }, /* 200 300 3.5 */
|
||||
{ .cnl = { 0xA, 0x35, 0x36, 0x00, 0x09 } }, /* 200 350 4.9 */
|
||||
{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */
|
||||
{ .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */
|
||||
{ .cnl = { 0xA, 0x35, 0x35, 0x00, 0x0A } }, /* 250 350 2.9 */
|
||||
{ .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */
|
||||
{ .cnl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */
|
||||
{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */
|
||||
{ .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 200 250 1.9 */
|
||||
{ .icl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } }, /* 200 300 3.5 */
|
||||
{ .icl = { 0xA, 0x35, 0x36, 0x00, 0x09 } }, /* 200 350 4.9 */
|
||||
{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */
|
||||
{ .icl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */
|
||||
{ .icl = { 0xA, 0x35, 0x35, 0x00, 0x0A } }, /* 250 350 2.9 */
|
||||
{ .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */
|
||||
{ .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */
|
||||
{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr = {
|
||||
|
|
@ -712,16 +532,16 @@ static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr =
|
|||
|
||||
static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp_hbr2[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */
|
||||
{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 250 1.9 */
|
||||
{ .cnl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } }, /* 200 300 3.5 */
|
||||
{ .cnl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 200 350 4.9 */
|
||||
{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */
|
||||
{ .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 300 1.6 */
|
||||
{ .cnl = { 0xA, 0x35, 0x3A, 0x00, 0x05 } }, /* 250 350 2.9 */
|
||||
{ .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */
|
||||
{ .cnl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */
|
||||
{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */
|
||||
{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 250 1.9 */
|
||||
{ .icl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } }, /* 200 300 3.5 */
|
||||
{ .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 200 350 4.9 */
|
||||
{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */
|
||||
{ .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 300 1.6 */
|
||||
{ .icl = { 0xA, 0x35, 0x3A, 0x00, 0x05 } }, /* 250 350 2.9 */
|
||||
{ .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */
|
||||
{ .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */
|
||||
{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2 = {
|
||||
|
|
@ -731,16 +551,16 @@ static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2
|
|||
|
||||
static const union intel_ddi_buf_trans_entry _dg1_combo_phy_ddi_translations_dp_rbr_hbr[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .cnl = { 0xA, 0x48, 0x35, 0x00, 0x0A } }, /* 350 500 3.1 */
|
||||
{ .cnl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */
|
||||
{ .cnl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .cnl = { 0xC, 0x60, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */
|
||||
{ .cnl = { 0xC, 0x60, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 600 900 3.5 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
{ .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } }, /* 350 500 3.1 */
|
||||
{ .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
|
||||
{ .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */
|
||||
{ .icl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .icl = { 0xC, 0x60, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */
|
||||
{ .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */
|
||||
{ .icl = { 0xC, 0x60, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
|
||||
{ .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 600 900 3.5 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_rbr_hbr = {
|
||||
|
|
@ -750,16 +570,16 @@ static const struct intel_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_rbr_hb
|
|||
|
||||
static const union intel_ddi_buf_trans_entry _dg1_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .cnl = { 0xA, 0x48, 0x35, 0x00, 0x0A } }, /* 350 500 3.1 */
|
||||
{ .cnl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */
|
||||
{ .cnl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .cnl = { 0xC, 0x60, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */
|
||||
{ .cnl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
{ .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } }, /* 350 500 3.1 */
|
||||
{ .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
|
||||
{ .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */
|
||||
{ .icl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .icl = { 0xC, 0x60, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */
|
||||
{ .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */
|
||||
{ .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
|
||||
{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2_hbr3 = {
|
||||
|
|
@ -885,16 +705,16 @@ static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_hdmi = {
|
|||
|
||||
static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_hbr[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
|
||||
{ .cnl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
|
||||
{ .cnl = { 0x6, 0x7D, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */
|
||||
{ .cnl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .cnl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
|
||||
{ .cnl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
{ .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
|
||||
{ .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
|
||||
{ .icl = { 0x6, 0x7D, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */
|
||||
{ .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
|
||||
{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
|
||||
{ .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */
|
||||
{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr = {
|
||||
|
|
@ -904,16 +724,16 @@ static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr =
|
|||
|
||||
static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_hbr2[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
|
||||
{ .cnl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */
|
||||
{ .cnl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .cnl = { 0xC, 0x63, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
|
||||
{ .cnl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */
|
||||
{ .cnl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
|
||||
{ .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
|
||||
{ .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */
|
||||
{ .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .icl = { 0xC, 0x63, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
|
||||
{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
|
||||
{ .icl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */
|
||||
{ .icl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2 = {
|
||||
|
|
@ -923,16 +743,16 @@ static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2 =
|
|||
|
||||
static const union intel_ddi_buf_trans_entry _tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .cnl = { 0xA, 0x4F, 0x36, 0x00, 0x09 } }, /* 350 500 3.1 */
|
||||
{ .cnl = { 0xC, 0x60, 0x32, 0x00, 0x0D } }, /* 350 700 6.0 */
|
||||
{ .cnl = { 0xC, 0x7F, 0x2D, 0x00, 0x12 } }, /* 350 900 8.2 */
|
||||
{ .cnl = { 0xC, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .cnl = { 0xC, 0x6F, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */
|
||||
{ .cnl = { 0x6, 0x7D, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */
|
||||
{ .cnl = { 0x6, 0x60, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x34, 0x00, 0x0B } }, /* 600 900 3.5 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .icl = { 0xA, 0x4F, 0x36, 0x00, 0x09 } }, /* 350 500 3.1 */
|
||||
{ .icl = { 0xC, 0x60, 0x32, 0x00, 0x0D } }, /* 350 700 6.0 */
|
||||
{ .icl = { 0xC, 0x7F, 0x2D, 0x00, 0x12 } }, /* 350 900 8.2 */
|
||||
{ .icl = { 0xC, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .icl = { 0xC, 0x6F, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */
|
||||
{ .icl = { 0x6, 0x7D, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */
|
||||
{ .icl = { 0x6, 0x60, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */
|
||||
{ .icl = { 0x6, 0x7F, 0x34, 0x00, 0x0B } }, /* 600 900 3.5 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr2 = {
|
||||
|
|
@ -946,15 +766,15 @@ static const struct intel_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr
|
|||
*/
|
||||
static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = {
|
||||
/* VS pre-emp */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 0 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 1 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 2 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 3 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1 0 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1 1 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1 2 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 2 0 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 2 1 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 0 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 1 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 2 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 3 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1 0 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1 1 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1 2 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 2 0 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 2 1 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl = {
|
||||
|
|
@ -964,16 +784,16 @@ static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_
|
|||
|
||||
static const union intel_ddi_buf_trans_entry _rkl_combo_phy_ddi_translations_dp_hbr[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0xA, 0x2F, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
|
||||
{ .cnl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
|
||||
{ .cnl = { 0x6, 0x7D, 0x2A, 0x00, 0x15 } }, /* 350 900 8.2 */
|
||||
{ .cnl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .cnl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
|
||||
{ .cnl = { 0xC, 0x6E, 0x3E, 0x00, 0x01 } }, /* 650 700 0.6 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
{ .icl = { 0xA, 0x2F, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
|
||||
{ .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
|
||||
{ .icl = { 0x6, 0x7D, 0x2A, 0x00, 0x15 } }, /* 350 900 8.2 */
|
||||
{ .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
|
||||
{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
|
||||
{ .icl = { 0xC, 0x6E, 0x3E, 0x00, 0x01 } }, /* 650 700 0.6 */
|
||||
{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr = {
|
||||
|
|
@ -983,16 +803,16 @@ static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr =
|
|||
|
||||
static const union intel_ddi_buf_trans_entry _rkl_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .cnl = { 0xA, 0x50, 0x38, 0x00, 0x07 } }, /* 350 500 3.1 */
|
||||
{ .cnl = { 0xC, 0x61, 0x33, 0x00, 0x0C } }, /* 350 700 6.0 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } }, /* 350 900 8.2 */
|
||||
{ .cnl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .cnl = { 0xC, 0x5F, 0x38, 0x00, 0x07 } }, /* 500 700 2.9 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
|
||||
{ .cnl = { 0xC, 0x5F, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
|
||||
{ .cnl = { 0x6, 0x7E, 0x36, 0x00, 0x09 } }, /* 600 900 3.5 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .icl = { 0xA, 0x50, 0x38, 0x00, 0x07 } }, /* 350 500 3.1 */
|
||||
{ .icl = { 0xC, 0x61, 0x33, 0x00, 0x0C } }, /* 350 700 6.0 */
|
||||
{ .icl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } }, /* 350 900 8.2 */
|
||||
{ .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .icl = { 0xC, 0x5F, 0x38, 0x00, 0x07 } }, /* 500 700 2.9 */
|
||||
{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
|
||||
{ .icl = { 0xC, 0x5F, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
|
||||
{ .icl = { 0x6, 0x7E, 0x36, 0x00, 0x09 } }, /* 600 900 3.5 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_hbr3 = {
|
||||
|
|
@ -1002,16 +822,16 @@ static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_h
|
|||
|
||||
static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
|
||||
{ .cnl = { 0xC, 0x63, 0x30, 0x00, 0x0F } }, /* 350 700 6.0 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */
|
||||
{ .cnl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .cnl = { 0xC, 0x63, 0x37, 0x00, 0x08 } }, /* 500 700 2.9 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } }, /* 500 900 5.1 */
|
||||
{ .cnl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */
|
||||
{ .cnl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
|
||||
{ .icl = { 0xC, 0x63, 0x31, 0x00, 0x0E } }, /* 350 700 6.0 */
|
||||
{ .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */
|
||||
{ .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .icl = { 0xC, 0x63, 0x37, 0x00, 0x08 } }, /* 500 700 2.9 */
|
||||
{ .icl = { 0x6, 0x73, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */
|
||||
{ .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
|
||||
{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_dp_hbr2_hbr3 = {
|
||||
|
|
@ -1021,16 +841,16 @@ static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_dp_hbr2_
|
|||
|
||||
static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr2[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0x9, 0x70, 0x3C, 0x00, 0x03 } }, /* 200 200 0.0 */
|
||||
{ .cnl = { 0x9, 0x6D, 0x3A, 0x00, 0x05 } }, /* 200 250 1.9 */
|
||||
{ .cnl = { 0x9, 0x7F, 0x36, 0x00, 0x09 } }, /* 200 300 3.5 */
|
||||
{ .cnl = { 0x4, 0x59, 0x32, 0x00, 0x0D } }, /* 200 350 4.9 */
|
||||
{ .cnl = { 0x2, 0x77, 0x3A, 0x00, 0x05 } }, /* 250 250 0.0 */
|
||||
{ .cnl = { 0x2, 0x7F, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */
|
||||
{ .cnl = { 0x4, 0x5A, 0x36, 0x00, 0x09 } }, /* 250 350 2.9 */
|
||||
{ .cnl = { 0x4, 0x5E, 0x3D, 0x00, 0x04 } }, /* 300 300 0.0 */
|
||||
{ .cnl = { 0x4, 0x65, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */
|
||||
{ .cnl = { 0x4, 0x6F, 0x3A, 0x00, 0x05 } }, /* 350 350 0.0 */
|
||||
{ .icl = { 0x9, 0x73, 0x3D, 0x00, 0x02 } }, /* 200 200 0.0 */
|
||||
{ .icl = { 0x9, 0x7A, 0x3C, 0x00, 0x03 } }, /* 200 250 1.9 */
|
||||
{ .icl = { 0x9, 0x7F, 0x3B, 0x00, 0x04 } }, /* 200 300 3.5 */
|
||||
{ .icl = { 0x4, 0x6C, 0x33, 0x00, 0x0C } }, /* 200 350 4.9 */
|
||||
{ .icl = { 0x2, 0x73, 0x3A, 0x00, 0x05 } }, /* 250 250 0.0 */
|
||||
{ .icl = { 0x2, 0x7C, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */
|
||||
{ .icl = { 0x4, 0x5A, 0x36, 0x00, 0x09 } }, /* 250 350 2.9 */
|
||||
{ .icl = { 0x4, 0x57, 0x3D, 0x00, 0x02 } }, /* 300 300 0.0 */
|
||||
{ .icl = { 0x4, 0x65, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */
|
||||
{ .icl = { 0x4, 0x6C, 0x3A, 0x00, 0x05 } }, /* 350 350 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr2 = {
|
||||
|
|
@ -1040,16 +860,16 @@ static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr2
|
|||
|
||||
static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr3[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .cnl = { 0xA, 0x5E, 0x34, 0x00, 0x0B } }, /* 350 350 0.0 */
|
||||
{ .cnl = { 0xA, 0x69, 0x32, 0x00, 0x0D } }, /* 350 500 3.1 */
|
||||
{ .cnl = { 0xC, 0x74, 0x31, 0x00, 0x0E } }, /* 350 700 6.0 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } }, /* 350 900 8.2 */
|
||||
{ .cnl = { 0xA, 0x5C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .cnl = { 0xC, 0x7F, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x33, 0x00, 0x0C } }, /* 500 900 5.1 */
|
||||
{ .cnl = { 0xC, 0x7F, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3C, 0x00, 0x03 } }, /* 600 900 3.5 */
|
||||
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
|
||||
{ .icl = { 0xC, 0x63, 0x31, 0x00, 0x0E } }, /* 350 700 6.0 */
|
||||
{ .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */
|
||||
{ .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .icl = { 0xC, 0x63, 0x37, 0x00, 0x08 } }, /* 500 700 2.9 */
|
||||
{ .icl = { 0x6, 0x73, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */
|
||||
{ .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
|
||||
{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr3 = {
|
||||
|
|
@ -1057,6 +877,74 @@ static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr3
|
|||
.num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_edp_hbr3),
|
||||
};
|
||||
|
||||
static const union intel_ddi_buf_trans_entry _adlp_combo_phy_ddi_translations_hdmi[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .icl = { 0x6, 0x60, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */
|
||||
{ .icl = { 0x6, 0x68, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .icl = { 0xA, 0x73, 0x3F, 0x00, 0x00 } }, /* 650 650 0.0 ALS */
|
||||
{ .icl = { 0xA, 0x78, 0x3F, 0x00, 0x00 } }, /* 800 800 0.0 */
|
||||
{ .icl = { 0xB, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1000 1000 0.0 Re-timer */
|
||||
{ .icl = { 0xB, 0x7F, 0x3B, 0x00, 0x04 } }, /* Full Red -1.5 */
|
||||
{ .icl = { 0xB, 0x7F, 0x39, 0x00, 0x06 } }, /* Full Red -1.8 */
|
||||
{ .icl = { 0xB, 0x7F, 0x37, 0x00, 0x08 } }, /* Full Red -2.0 CRLS */
|
||||
{ .icl = { 0xB, 0x7F, 0x35, 0x00, 0x0A } }, /* Full Red -2.5 */
|
||||
{ .icl = { 0xB, 0x7F, 0x33, 0x00, 0x0C } }, /* Full Red -3.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_hdmi = {
|
||||
.entries = _adlp_combo_phy_ddi_translations_hdmi,
|
||||
.num_entries = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_hdmi),
|
||||
.hdmi_default_entry = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_hdmi) - 1,
|
||||
};
|
||||
|
||||
static const union intel_ddi_buf_trans_entry _adlp_combo_phy_ddi_translations_dp_hbr[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
|
||||
{ .icl = { 0xC, 0x71, 0x31, 0x00, 0x0E } }, /* 350 700 6.0 */
|
||||
{ .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */
|
||||
{ .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
|
||||
{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
|
||||
{ .icl = { 0xC, 0x73, 0x3E, 0x00, 0x01 } }, /* 650 700 0.6 */
|
||||
{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_dp_hbr = {
|
||||
.entries = _adlp_combo_phy_ddi_translations_dp_hbr,
|
||||
.num_entries = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_dp_hbr),
|
||||
};
|
||||
|
||||
static const union intel_ddi_buf_trans_entry _adlp_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
|
||||
/* NT mV Trans mV db */
|
||||
{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
|
||||
{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
|
||||
{ .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
|
||||
{ .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */
|
||||
{ .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
|
||||
{ .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
|
||||
{ .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */
|
||||
{ .icl = { 0xC, 0x63, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
|
||||
{ .icl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } }, /* 600 900 3.5 */
|
||||
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_dp_hbr2_hbr3 = {
|
||||
.entries = _adlp_combo_phy_ddi_translations_dp_hbr2_hbr3,
|
||||
.num_entries = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_dp_hbr2_hbr3),
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_edp_hbr3 = {
|
||||
.entries = _icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3,
|
||||
.num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3),
|
||||
};
|
||||
|
||||
static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_edp_up_to_hbr2 = {
|
||||
.entries = _icl_combo_phy_ddi_translations_edp_hbr2,
|
||||
.num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_edp_hbr2),
|
||||
};
|
||||
|
||||
static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_ddi_translations_dp_hbr[] = {
|
||||
/* VS pre-emp Non-trans mV Pre-emph dB */
|
||||
{ .dkl = { 0x7, 0x0, 0x01 } }, /* 0 0 400mV 0 dB */
|
||||
|
|
@ -1269,88 +1157,6 @@ bxt_get_buf_trans(struct intel_encoder *encoder,
|
|||
return intel_get_buf_trans(&bxt_ddi_translations_dp, n_entries);
|
||||
}
|
||||
|
||||
static const struct intel_ddi_buf_trans *
|
||||
cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
|
||||
|
||||
if (voltage == VOLTAGE_INFO_0_85V) {
|
||||
return intel_get_buf_trans(&cnl_ddi_translations_hdmi_0_85V,
|
||||
n_entries);
|
||||
} else if (voltage == VOLTAGE_INFO_0_95V) {
|
||||
return intel_get_buf_trans(&cnl_ddi_translations_hdmi_0_95V,
|
||||
n_entries);
|
||||
} else if (voltage == VOLTAGE_INFO_1_05V) {
|
||||
return intel_get_buf_trans(&cnl_ddi_translations_hdmi_1_05V,
|
||||
n_entries);
|
||||
} else {
|
||||
*n_entries = 1; /* shut up gcc */
|
||||
MISSING_CASE(voltage);
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static const struct intel_ddi_buf_trans *
|
||||
cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
|
||||
|
||||
if (voltage == VOLTAGE_INFO_0_85V) {
|
||||
return intel_get_buf_trans(&cnl_ddi_translations_dp_0_85V,
|
||||
n_entries);
|
||||
} else if (voltage == VOLTAGE_INFO_0_95V) {
|
||||
return intel_get_buf_trans(&cnl_ddi_translations_dp_0_95V,
|
||||
n_entries);
|
||||
} else if (voltage == VOLTAGE_INFO_1_05V) {
|
||||
return intel_get_buf_trans(&cnl_ddi_translations_dp_1_05V,
|
||||
n_entries);
|
||||
} else {
|
||||
*n_entries = 1; /* shut up gcc */
|
||||
MISSING_CASE(voltage);
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static const struct intel_ddi_buf_trans *
|
||||
cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
|
||||
|
||||
if (dev_priv->vbt.edp.low_vswing) {
|
||||
if (voltage == VOLTAGE_INFO_0_85V) {
|
||||
return intel_get_buf_trans(&cnl_ddi_translations_edp_0_85V,
|
||||
n_entries);
|
||||
} else if (voltage == VOLTAGE_INFO_0_95V) {
|
||||
return intel_get_buf_trans(&cnl_ddi_translations_edp_0_95V,
|
||||
n_entries);
|
||||
} else if (voltage == VOLTAGE_INFO_1_05V) {
|
||||
return intel_get_buf_trans(&cnl_ddi_translations_edp_1_05V,
|
||||
n_entries);
|
||||
} else {
|
||||
*n_entries = 1; /* shut up gcc */
|
||||
MISSING_CASE(voltage);
|
||||
}
|
||||
return NULL;
|
||||
} else {
|
||||
return cnl_get_buf_trans_dp(encoder, n_entries);
|
||||
}
|
||||
}
|
||||
|
||||
static const struct intel_ddi_buf_trans *
|
||||
cnl_get_buf_trans(struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
int *n_entries)
|
||||
{
|
||||
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
|
||||
return cnl_get_buf_trans_hdmi(encoder, n_entries);
|
||||
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
|
||||
return cnl_get_buf_trans_edp(encoder, n_entries);
|
||||
return cnl_get_buf_trans_dp(encoder, n_entries);
|
||||
}
|
||||
|
||||
static const struct intel_ddi_buf_trans *
|
||||
icl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
|
|
@ -1661,6 +1467,52 @@ adls_get_combo_buf_trans(struct intel_encoder *encoder,
|
|||
return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
|
||||
}
|
||||
|
||||
static const struct intel_ddi_buf_trans *
|
||||
adlp_get_combo_buf_trans_dp(struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
int *n_entries)
|
||||
{
|
||||
if (crtc_state->port_clock > 270000)
|
||||
return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries);
|
||||
else
|
||||
return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_dp_hbr, n_entries);
|
||||
}
|
||||
|
||||
static const struct intel_ddi_buf_trans *
|
||||
adlp_get_combo_buf_trans_edp(struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
int *n_entries)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
||||
|
||||
if (crtc_state->port_clock > 540000) {
|
||||
return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_edp_hbr3,
|
||||
n_entries);
|
||||
} else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) {
|
||||
return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl,
|
||||
n_entries);
|
||||
} else if (dev_priv->vbt.edp.low_vswing) {
|
||||
return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_edp_up_to_hbr2,
|
||||
n_entries);
|
||||
}
|
||||
|
||||
return adlp_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
|
||||
}
|
||||
|
||||
static const struct intel_ddi_buf_trans *
|
||||
adlp_get_combo_buf_trans(struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
int *n_entries)
|
||||
{
|
||||
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
|
||||
return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_hdmi, n_entries);
|
||||
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
|
||||
return adlp_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
|
||||
else
|
||||
return adlp_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
|
||||
}
|
||||
|
||||
static const struct intel_ddi_buf_trans *
|
||||
tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
|
|
@ -1738,7 +1590,7 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
|
|||
|
||||
if (IS_ALDERLAKE_P(i915)) {
|
||||
if (intel_phy_is_combo(i915, phy))
|
||||
encoder->get_buf_trans = tgl_get_combo_buf_trans;
|
||||
encoder->get_buf_trans = adlp_get_combo_buf_trans;
|
||||
else
|
||||
encoder->get_buf_trans = adlp_get_dkl_buf_trans;
|
||||
} else if (IS_ALDERLAKE_S(i915)) {
|
||||
|
|
@ -1761,8 +1613,6 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
|
|||
encoder->get_buf_trans = icl_get_combo_buf_trans;
|
||||
else
|
||||
encoder->get_buf_trans = icl_get_mg_buf_trans;
|
||||
} else if (IS_CANNONLAKE(i915)) {
|
||||
encoder->get_buf_trans = cnl_get_buf_trans;
|
||||
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
|
||||
encoder->get_buf_trans = bxt_get_buf_trans;
|
||||
} else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KBL_ULX(i915)) {
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ struct bxt_ddi_buf_trans {
|
|||
u8 deemphasis;
|
||||
};
|
||||
|
||||
struct cnl_ddi_buf_trans {
|
||||
struct icl_ddi_buf_trans {
|
||||
u8 dw2_swing_sel;
|
||||
u8 dw7_n_scalar;
|
||||
u8 dw4_cursor_coeff;
|
||||
|
|
@ -48,7 +48,7 @@ struct tgl_dkl_phy_ddi_buf_trans {
|
|||
union intel_ddi_buf_trans_entry {
|
||||
struct hsw_ddi_buf_trans hsw;
|
||||
struct bxt_ddi_buf_trans bxt;
|
||||
struct cnl_ddi_buf_trans cnl;
|
||||
struct icl_ddi_buf_trans icl;
|
||||
struct icl_mg_phy_ddi_buf_trans mg;
|
||||
struct tgl_dkl_phy_ddi_buf_trans dkl;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -59,6 +59,7 @@
|
|||
#include "display/intel_hdmi.h"
|
||||
#include "display/intel_lvds.h"
|
||||
#include "display/intel_sdvo.h"
|
||||
#include "display/intel_snps_phy.h"
|
||||
#include "display/intel_tv.h"
|
||||
#include "display/intel_vdsc.h"
|
||||
#include "display/intel_vrr.h"
|
||||
|
|
@ -975,7 +976,7 @@ void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
|
|||
/* FIXME: assert CPU port conditions for SNB+ */
|
||||
}
|
||||
|
||||
/* Wa_22012358565:adlp */
|
||||
/* Wa_22012358565:adl-p */
|
||||
if (DISPLAY_VER(dev_priv) == 13)
|
||||
intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
|
||||
0, PIPE_ARB_USE_PROG_SLOTS);
|
||||
|
|
@ -1035,6 +1036,10 @@ void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
|
|||
if (!IS_I830(dev_priv))
|
||||
val &= ~PIPECONF_ENABLE;
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 12)
|
||||
intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
|
||||
FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
|
||||
|
||||
intel_de_write(dev_priv, reg, val);
|
||||
if ((val & PIPECONF_ENABLE) == 0)
|
||||
intel_wait_for_pipe_off(old_crtc_state);
|
||||
|
|
@ -2207,8 +2212,26 @@ unlock:
|
|||
clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
|
||||
}
|
||||
|
||||
static void icl_set_pipe_chicken(struct intel_crtc *crtc)
|
||||
static bool underrun_recovery_supported(const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
if (crtc_state->pch_pfit.enabled &&
|
||||
(crtc_state->pipe_src_w > drm_rect_width(&crtc_state->pch_pfit.dst) ||
|
||||
crtc_state->pipe_src_h > drm_rect_height(&crtc_state->pch_pfit.dst) ||
|
||||
crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420))
|
||||
return false;
|
||||
|
||||
if (crtc_state->dsc.compression_enable)
|
||||
return false;
|
||||
|
||||
if (crtc_state->has_psr2)
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
enum pipe pipe = crtc->pipe;
|
||||
u32 tmp;
|
||||
|
|
@ -2229,19 +2252,19 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc)
|
|||
*/
|
||||
tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
|
||||
|
||||
/*
|
||||
* "The underrun recovery mechanism should be disabled
|
||||
* when the following is enabled for this pipe:
|
||||
* WiDi
|
||||
* Downscaling (this includes YUV420 fullblend)
|
||||
* COG
|
||||
* DSC
|
||||
* PSR2"
|
||||
*
|
||||
* FIXME: enable whenever possible...
|
||||
*/
|
||||
if (IS_ALDERLAKE_P(dev_priv))
|
||||
tmp |= UNDERRUN_RECOVERY_DISABLE;
|
||||
if (IS_DG2(dev_priv)) {
|
||||
/*
|
||||
* Underrun recovery must always be disabled on DG2. However
|
||||
* the chicken bit meaning is inverted compared to other
|
||||
* platforms.
|
||||
*/
|
||||
tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
|
||||
} else if (DISPLAY_VER(dev_priv) >= 13) {
|
||||
if (underrun_recovery_supported(crtc_state))
|
||||
tmp &= ~UNDERRUN_RECOVERY_DISABLE_ADLP;
|
||||
else
|
||||
tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
|
||||
}
|
||||
|
||||
intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
|
||||
}
|
||||
|
|
@ -3191,6 +3214,28 @@ static void intel_encoders_enable(struct intel_atomic_state *state,
|
|||
}
|
||||
}
|
||||
|
||||
static void intel_encoders_pre_disable(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc)
|
||||
{
|
||||
const struct intel_crtc_state *old_crtc_state =
|
||||
intel_atomic_get_old_crtc_state(state, crtc);
|
||||
const struct drm_connector_state *old_conn_state;
|
||||
struct drm_connector *conn;
|
||||
int i;
|
||||
|
||||
for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
|
||||
struct intel_encoder *encoder =
|
||||
to_intel_encoder(old_conn_state->best_encoder);
|
||||
|
||||
if (old_conn_state->crtc != &crtc->base)
|
||||
continue;
|
||||
|
||||
if (encoder->pre_disable)
|
||||
encoder->pre_disable(state, encoder, old_crtc_state,
|
||||
old_conn_state);
|
||||
}
|
||||
}
|
||||
|
||||
static void intel_encoders_disable(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc)
|
||||
{
|
||||
|
|
@ -3400,13 +3445,17 @@ static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
|
|||
intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
|
||||
}
|
||||
|
||||
static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
|
||||
static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
enum pipe pipe = crtc->pipe;
|
||||
u32 val;
|
||||
|
||||
val = MBUS_DBOX_A_CREDIT(2);
|
||||
/* Wa_22010947358:adl-p */
|
||||
if (IS_ALDERLAKE_P(dev_priv))
|
||||
val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4);
|
||||
else
|
||||
val = MBUS_DBOX_A_CREDIT(2);
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 12) {
|
||||
val |= MBUS_DBOX_BW_CREDIT(2);
|
||||
|
|
@ -3474,7 +3523,8 @@ static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
|
|||
* Enable sequence steps 1-7 on bigjoiner master
|
||||
*/
|
||||
intel_encoders_pre_pll_enable(state, master);
|
||||
intel_enable_shared_dpll(master_crtc_state);
|
||||
if (master_crtc_state->shared_dpll)
|
||||
intel_enable_shared_dpll(master_crtc_state);
|
||||
intel_encoders_pre_enable(state, master);
|
||||
|
||||
/* and DSC on slave */
|
||||
|
|
@ -3532,7 +3582,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
|
|||
|
||||
crtc->active = true;
|
||||
|
||||
/* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
|
||||
/* Display WA #1180: WaDisableScalarClockGating: glk */
|
||||
psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
|
||||
new_crtc_state->pch_pfit.enabled;
|
||||
if (psl_clkgate_wa)
|
||||
|
|
@ -3556,13 +3606,17 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
|
|||
hsw_set_linetime_wm(new_crtc_state);
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 11)
|
||||
icl_set_pipe_chicken(crtc);
|
||||
icl_set_pipe_chicken(new_crtc_state);
|
||||
|
||||
if (dev_priv->display.initial_watermarks)
|
||||
dev_priv->display.initial_watermarks(state, crtc);
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 11)
|
||||
icl_pipe_mbus_enable(crtc);
|
||||
if (DISPLAY_VER(dev_priv) >= 11) {
|
||||
const struct intel_dbuf_state *dbuf_state =
|
||||
intel_atomic_get_new_dbuf_state(state);
|
||||
|
||||
icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus);
|
||||
}
|
||||
|
||||
if (new_crtc_state->bigjoiner_slave)
|
||||
intel_crtc_vblank_on(new_crtc_state);
|
||||
|
|
@ -3696,6 +3750,13 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
|
|||
{
|
||||
if (phy == PHY_NONE)
|
||||
return false;
|
||||
else if (IS_DG2(dev_priv))
|
||||
/*
|
||||
* DG2 outputs labelled as "combo PHY" in the bspec use
|
||||
* SNPS PHYs with completely different programming,
|
||||
* hence we always return false here.
|
||||
*/
|
||||
return false;
|
||||
else if (IS_ALDERLAKE_S(dev_priv))
|
||||
return phy <= PHY_E;
|
||||
else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
|
||||
|
|
@ -3710,7 +3771,10 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
|
|||
|
||||
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
|
||||
{
|
||||
if (IS_ALDERLAKE_P(dev_priv))
|
||||
if (IS_DG2(dev_priv))
|
||||
/* DG2's "TC1" output uses a SNPS PHY */
|
||||
return false;
|
||||
else if (IS_ALDERLAKE_P(dev_priv))
|
||||
return phy >= PHY_F && phy <= PHY_I;
|
||||
else if (IS_TIGERLAKE(dev_priv))
|
||||
return phy >= PHY_D && phy <= PHY_I;
|
||||
|
|
@ -3720,6 +3784,20 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
|
|||
return false;
|
||||
}
|
||||
|
||||
bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
|
||||
{
|
||||
if (phy == PHY_NONE)
|
||||
return false;
|
||||
else if (IS_DG2(dev_priv))
|
||||
/*
|
||||
* All four "combo" ports and the TC1 port (PHY E) use
|
||||
* Synopsis PHYs.
|
||||
*/
|
||||
return phy <= PHY_E;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
|
||||
{
|
||||
if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
|
||||
|
|
@ -3864,7 +3942,7 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
|
|||
}
|
||||
|
||||
if (HAS_DDI(dev_priv) && crtc_state->has_audio)
|
||||
mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
|
||||
mask |= BIT_ULL(POWER_DOMAIN_AUDIO_MMIO);
|
||||
|
||||
if (crtc_state->shared_dpll)
|
||||
mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
|
||||
|
|
@ -8633,10 +8711,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
|
|||
|
||||
PIPE_CONF_CHECK_BOOL(double_wide);
|
||||
|
||||
PIPE_CONF_CHECK_P(shared_dpll);
|
||||
if (dev_priv->dpll.mgr)
|
||||
PIPE_CONF_CHECK_P(shared_dpll);
|
||||
|
||||
/* FIXME do the readout properly and get rid of this quirk */
|
||||
if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
|
||||
if (dev_priv->dpll.mgr && !PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
|
||||
PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
|
||||
PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
|
||||
PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
|
||||
|
|
@ -8668,7 +8747,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
|
|||
PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
|
||||
PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
|
||||
PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
|
||||
}
|
||||
|
||||
if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
|
||||
PIPE_CONF_CHECK_X(dsi_pll.ctrl);
|
||||
PIPE_CONF_CHECK_X(dsi_pll.div);
|
||||
|
||||
|
|
@ -9006,6 +9087,10 @@ verify_crtc_state(struct intel_crtc *crtc,
|
|||
if (!new_crtc_state->hw.active)
|
||||
return;
|
||||
|
||||
if (new_crtc_state->bigjoiner_slave)
|
||||
/* No PLLs set for slave */
|
||||
pipe_config->shared_dpll = NULL;
|
||||
|
||||
intel_pipe_config_sanity_check(dev_priv, pipe_config);
|
||||
|
||||
if (!intel_pipe_config_compare(new_crtc_state,
|
||||
|
|
@ -9108,6 +9193,55 @@ verify_shared_dpll_state(struct intel_crtc *crtc,
|
|||
}
|
||||
}
|
||||
|
||||
static void
|
||||
verify_mpllb_state(struct intel_atomic_state *state,
|
||||
struct intel_crtc_state *new_crtc_state)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(state->base.dev);
|
||||
struct intel_mpllb_state mpllb_hw_state = { 0 };
|
||||
struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state;
|
||||
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
|
||||
struct intel_encoder *encoder;
|
||||
|
||||
if (!IS_DG2(i915))
|
||||
return;
|
||||
|
||||
if (!new_crtc_state->hw.active)
|
||||
return;
|
||||
|
||||
if (new_crtc_state->bigjoiner_slave)
|
||||
return;
|
||||
|
||||
encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
|
||||
intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state);
|
||||
|
||||
#define MPLLB_CHECK(name) do { \
|
||||
if (mpllb_sw_state->name != mpllb_hw_state.name) { \
|
||||
pipe_config_mismatch(false, crtc, "MPLLB:" __stringify(name), \
|
||||
"(expected 0x%08x, found 0x%08x)", \
|
||||
mpllb_sw_state->name, \
|
||||
mpllb_hw_state.name); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
MPLLB_CHECK(mpllb_cp);
|
||||
MPLLB_CHECK(mpllb_div);
|
||||
MPLLB_CHECK(mpllb_div2);
|
||||
MPLLB_CHECK(mpllb_fracn1);
|
||||
MPLLB_CHECK(mpllb_fracn2);
|
||||
MPLLB_CHECK(mpllb_sscen);
|
||||
MPLLB_CHECK(mpllb_sscstep);
|
||||
|
||||
/*
|
||||
* ref_control is handled by the hardware/firemware and never
|
||||
* programmed by the software, but the proper values are supplied
|
||||
* in the bspec for verification purposes.
|
||||
*/
|
||||
MPLLB_CHECK(ref_control);
|
||||
|
||||
#undef MPLLB_CHECK
|
||||
}
|
||||
|
||||
static void
|
||||
intel_modeset_verify_crtc(struct intel_crtc *crtc,
|
||||
struct intel_atomic_state *state,
|
||||
|
|
@ -9121,6 +9255,7 @@ intel_modeset_verify_crtc(struct intel_crtc *crtc,
|
|||
verify_connector_state(state, crtc);
|
||||
verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
|
||||
verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
|
||||
verify_mpllb_state(state, new_crtc_state);
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -9746,7 +9881,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
|
|||
|
||||
/*
|
||||
* FIXME: This check is kept generic for all platforms.
|
||||
* Need to verify this for all gen9 and gen10 platforms to enable
|
||||
* Need to verify this for all gen9 platforms to enable
|
||||
* this selectively if required.
|
||||
*/
|
||||
switch (new_plane_state->hw.fb->modifier) {
|
||||
|
|
@ -10157,7 +10292,7 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
|
|||
hsw_set_linetime_wm(new_crtc_state);
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 11)
|
||||
icl_set_pipe_chicken(crtc);
|
||||
icl_set_pipe_chicken(new_crtc_state);
|
||||
}
|
||||
|
||||
static void commit_pipe_pre_planes(struct intel_atomic_state *state,
|
||||
|
|
@ -10291,6 +10426,8 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
|
|||
|
||||
drm_WARN_ON(&dev_priv->drm, old_crtc_state->bigjoiner_slave);
|
||||
|
||||
intel_encoders_pre_disable(state, crtc);
|
||||
|
||||
intel_crtc_disable_planes(state, crtc);
|
||||
|
||||
/*
|
||||
|
|
@ -11325,7 +11462,12 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
|
|||
if (!HAS_DISPLAY(dev_priv))
|
||||
return;
|
||||
|
||||
if (IS_ALDERLAKE_P(dev_priv)) {
|
||||
if (IS_DG2(dev_priv)) {
|
||||
intel_ddi_init(dev_priv, PORT_A);
|
||||
intel_ddi_init(dev_priv, PORT_B);
|
||||
intel_ddi_init(dev_priv, PORT_C);
|
||||
intel_ddi_init(dev_priv, PORT_D_XELPD);
|
||||
} else if (IS_ALDERLAKE_P(dev_priv)) {
|
||||
intel_ddi_init(dev_priv, PORT_A);
|
||||
intel_ddi_init(dev_priv, PORT_B);
|
||||
intel_ddi_init(dev_priv, PORT_TC1);
|
||||
|
|
@ -11378,7 +11520,6 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
|
|||
intel_ddi_init(dev_priv, PORT_C);
|
||||
intel_ddi_init(dev_priv, PORT_D);
|
||||
intel_ddi_init(dev_priv, PORT_E);
|
||||
intel_ddi_init(dev_priv, PORT_F);
|
||||
} else if (HAS_DDI(dev_priv)) {
|
||||
u32 found;
|
||||
|
||||
|
|
@ -13127,7 +13268,7 @@ get_encoder_power_domains(struct drm_i915_private *dev_priv)
|
|||
static void intel_early_display_was(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
/*
|
||||
* Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl
|
||||
* Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl
|
||||
* Also known as Wa_14010480278.
|
||||
*/
|
||||
if (IS_DISPLAY_VER(dev_priv, 10, 12))
|
||||
|
|
|
|||
|
|
@ -561,6 +561,7 @@ struct drm_display_mode *
|
|||
intel_encoder_current_mode(struct intel_encoder *encoder);
|
||||
bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
|
||||
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
|
||||
bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy);
|
||||
enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
|
||||
enum port port);
|
||||
int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
|
||||
|
|
|
|||
|
|
@ -2256,6 +2256,11 @@ static int i915_lpsp_capability_show(struct seq_file *m, void *data)
|
|||
if (connector->status != connector_status_connected)
|
||||
return -ENODEV;
|
||||
|
||||
if (DISPLAY_VER(i915) >= 13) {
|
||||
LPSP_CAPABLE(encoder->port <= PORT_B);
|
||||
return 0;
|
||||
}
|
||||
|
||||
switch (DISPLAY_VER(i915)) {
|
||||
case 12:
|
||||
/*
|
||||
|
|
@ -2390,6 +2395,73 @@ static const struct file_operations i915_dsc_fec_support_fops = {
|
|||
.write = i915_dsc_fec_support_write
|
||||
};
|
||||
|
||||
static int i915_dsc_bpp_show(struct seq_file *m, void *data)
|
||||
{
|
||||
struct drm_connector *connector = m->private;
|
||||
struct drm_device *dev = connector->dev;
|
||||
struct drm_crtc *crtc;
|
||||
struct intel_crtc_state *crtc_state;
|
||||
struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
|
||||
int ret;
|
||||
|
||||
if (!encoder)
|
||||
return -ENODEV;
|
||||
|
||||
ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
crtc = connector->state->crtc;
|
||||
if (connector->status != connector_status_connected || !crtc) {
|
||||
ret = -ENODEV;
|
||||
goto out;
|
||||
}
|
||||
|
||||
crtc_state = to_intel_crtc_state(crtc->state);
|
||||
seq_printf(m, "Compressed_BPP: %d\n", crtc_state->dsc.compressed_bpp);
|
||||
|
||||
out: drm_modeset_unlock(&dev->mode_config.connection_mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static ssize_t i915_dsc_bpp_write(struct file *file,
|
||||
const char __user *ubuf,
|
||||
size_t len, loff_t *offp)
|
||||
{
|
||||
struct drm_connector *connector =
|
||||
((struct seq_file *)file->private_data)->private;
|
||||
struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
|
||||
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
||||
int dsc_bpp = 0;
|
||||
int ret;
|
||||
|
||||
ret = kstrtoint_from_user(ubuf, len, 0, &dsc_bpp);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
intel_dp->force_dsc_bpp = dsc_bpp;
|
||||
*offp += len;
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
static int i915_dsc_bpp_open(struct inode *inode,
|
||||
struct file *file)
|
||||
{
|
||||
return single_open(file, i915_dsc_bpp_show,
|
||||
inode->i_private);
|
||||
}
|
||||
|
||||
static const struct file_operations i915_dsc_bpp_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.open = i915_dsc_bpp_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
.write = i915_dsc_bpp_write
|
||||
};
|
||||
|
||||
/**
|
||||
* intel_connector_debugfs_add - add i915 specific connector debugfs files
|
||||
* @connector: pointer to a registered drm_connector
|
||||
|
|
@ -2428,10 +2500,17 @@ int intel_connector_debugfs_add(struct drm_connector *connector)
|
|||
connector, &i915_hdcp_sink_capability_fops);
|
||||
}
|
||||
|
||||
if ((DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) && ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort && !to_intel_connector(connector)->mst_port) || connector->connector_type == DRM_MODE_CONNECTOR_eDP))
|
||||
debugfs_create_file("i915_dsc_fec_support", S_IRUGO, root,
|
||||
if (DISPLAY_VER(dev_priv) >= 11 &&
|
||||
((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort &&
|
||||
!to_intel_connector(connector)->mst_port) ||
|
||||
connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
|
||||
debugfs_create_file("i915_dsc_fec_support", 0644, root,
|
||||
connector, &i915_dsc_fec_support_fops);
|
||||
|
||||
debugfs_create_file("i915_dsc_bpp", 0644, root,
|
||||
connector, &i915_dsc_bpp_fops);
|
||||
}
|
||||
|
||||
/* Legacy panels doesn't lpsp on any platform */
|
||||
if ((DISPLAY_VER(dev_priv) >= 9 || IS_HASWELL(dev_priv) ||
|
||||
IS_BROADWELL(dev_priv)) &&
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
#include "intel_pm.h"
|
||||
#include "intel_pps.h"
|
||||
#include "intel_sideband.h"
|
||||
#include "intel_snps_phy.h"
|
||||
#include "intel_tc.h"
|
||||
#include "intel_vga.h"
|
||||
|
||||
|
|
@ -106,8 +107,10 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
|
|||
return "PORT_OTHER";
|
||||
case POWER_DOMAIN_VGA:
|
||||
return "VGA";
|
||||
case POWER_DOMAIN_AUDIO:
|
||||
return "AUDIO";
|
||||
case POWER_DOMAIN_AUDIO_MMIO:
|
||||
return "AUDIO_MMIO";
|
||||
case POWER_DOMAIN_AUDIO_PLAYBACK:
|
||||
return "AUDIO_PLAYBACK";
|
||||
case POWER_DOMAIN_AUX_A:
|
||||
return "AUX_A";
|
||||
case POWER_DOMAIN_AUX_B:
|
||||
|
|
@ -341,6 +344,17 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
|
|||
{
|
||||
const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
|
||||
int pw_idx = power_well->desc->hsw.idx;
|
||||
int enable_delay = power_well->desc->hsw.fixed_enable_delay;
|
||||
|
||||
/*
|
||||
* For some power wells we're not supposed to watch the status bit for
|
||||
* an ack, but rather just wait a fixed amount of time and then
|
||||
* proceed. This is only used on DG2.
|
||||
*/
|
||||
if (IS_DG2(dev_priv) && enable_delay) {
|
||||
usleep_range(enable_delay, 2 * enable_delay);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
|
||||
if (intel_de_wait_for_set(dev_priv, regs->driver,
|
||||
|
|
@ -436,17 +450,6 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
|
|||
|
||||
hsw_wait_for_power_well_enable(dev_priv, power_well, false);
|
||||
|
||||
/* Display WA #1178: cnl */
|
||||
if (IS_CANNONLAKE(dev_priv) &&
|
||||
pw_idx >= GLK_PW_CTL_IDX_AUX_B &&
|
||||
pw_idx <= CNL_PW_CTL_IDX_AUX_F) {
|
||||
u32 val;
|
||||
|
||||
val = intel_de_read(dev_priv, CNL_AUX_ANAOVRD1(pw_idx));
|
||||
val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
|
||||
intel_de_write(dev_priv, CNL_AUX_ANAOVRD1(pw_idx), val);
|
||||
}
|
||||
|
||||
if (power_well->desc->hsw.has_fuses) {
|
||||
enum skl_power_gate pg;
|
||||
|
||||
|
|
@ -2508,7 +2511,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
|
|||
BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
|
||||
BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
|
||||
BIT_ULL(POWER_DOMAIN_VGA) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_B) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_C) | \
|
||||
BIT_ULL(POWER_DOMAIN_GMBUS) | \
|
||||
|
|
@ -2558,7 +2562,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
|
|||
BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
|
||||
BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
|
||||
BIT_ULL(POWER_DOMAIN_VGA) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_B) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_C) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_D) | \
|
||||
|
|
@ -2591,7 +2596,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
|
|||
BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
|
||||
BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
|
||||
BIT_ULL(POWER_DOMAIN_VGA) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
|
||||
#define BDW_DISPLAY_POWER_DOMAINS ( \
|
||||
|
|
@ -2607,7 +2613,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
|
|||
BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
|
||||
BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
|
||||
BIT_ULL(POWER_DOMAIN_VGA) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
|
||||
#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
|
||||
|
|
@ -2625,7 +2632,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
|
|||
BIT_ULL(POWER_DOMAIN_AUX_B) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_C) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_D) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
|
||||
BIT_ULL(POWER_DOMAIN_VGA) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \
|
||||
|
|
@ -2660,7 +2668,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
|
|||
BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_B) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_C) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
|
||||
BIT_ULL(POWER_DOMAIN_VGA) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
|
||||
|
|
@ -2693,7 +2702,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
|
|||
BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_B) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_C) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
|
||||
BIT_ULL(POWER_DOMAIN_VGA) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS ( \
|
||||
|
|
@ -2732,63 +2742,6 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
|
|||
BIT_ULL(POWER_DOMAIN_GMBUS) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
|
||||
#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
|
||||
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
|
||||
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
|
||||
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
|
||||
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
|
||||
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
|
||||
BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
|
||||
BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
|
||||
BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
|
||||
BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
|
||||
BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
|
||||
BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_B) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_C) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_D) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_F) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_VGA) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
#define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \
|
||||
BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
#define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \
|
||||
BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
#define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS ( \
|
||||
BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
#define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS ( \
|
||||
BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
#define CNL_DISPLAY_AUX_A_POWER_DOMAINS ( \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_A) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
#define CNL_DISPLAY_AUX_B_POWER_DOMAINS ( \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_B) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
#define CNL_DISPLAY_AUX_C_POWER_DOMAINS ( \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_C) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
#define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_D) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
#define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_F) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
#define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS ( \
|
||||
BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
|
||||
CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
|
||||
BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
|
||||
BIT_ULL(POWER_DOMAIN_MODESET) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_A) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
|
||||
/*
|
||||
* ICL PW_0/PG_0 domains (HW/DMC control):
|
||||
* - PCI
|
||||
|
|
@ -2830,7 +2783,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
|
|||
BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
|
||||
BIT_ULL(POWER_DOMAIN_VGA) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
/*
|
||||
* - transcoder WD
|
||||
|
|
@ -2922,7 +2876,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
|
|||
BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
|
||||
BIT_ULL(POWER_DOMAIN_VGA) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
|
||||
#define TGL_PW_2_POWER_DOMAINS ( \
|
||||
|
|
@ -2992,7 +2947,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
|
|||
RKL_PW_4_POWER_DOMAINS | \
|
||||
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
|
||||
BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
|
||||
BIT_ULL(POWER_DOMAIN_VGA) | \
|
||||
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
|
||||
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
|
||||
|
|
@ -3029,6 +2985,35 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
|
|||
BIT_ULL(POWER_DOMAIN_AUX_B) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
|
||||
/*
|
||||
* DG1 onwards Audio MMIO/VERBS lies in PG0 power well.
|
||||
*/
|
||||
#define DG1_PW_3_POWER_DOMAINS ( \
|
||||
TGL_PW_4_POWER_DOMAINS | \
|
||||
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
|
||||
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
|
||||
BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
|
||||
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
|
||||
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
|
||||
BIT_ULL(POWER_DOMAIN_VGA) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
|
||||
#define DG1_PW_2_POWER_DOMAINS ( \
|
||||
DG1_PW_3_POWER_DOMAINS | \
|
||||
BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
|
||||
#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS ( \
|
||||
DG1_PW_3_POWER_DOMAINS | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_MODESET) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_A) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_B) | \
|
||||
BIT_ULL(POWER_DOMAIN_INIT))
|
||||
|
||||
/*
|
||||
* XE_LPD Power Domains
|
||||
*
|
||||
|
|
@ -3074,7 +3059,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
|
|||
XELPD_PW_B_POWER_DOMAINS | \
|
||||
XELPD_PW_C_POWER_DOMAINS | \
|
||||
XELPD_PW_D_POWER_DOMAINS | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
|
||||
BIT_ULL(POWER_DOMAIN_VGA) | \
|
||||
BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
|
||||
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) | \
|
||||
|
|
@ -3115,6 +3100,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
|
|||
|
||||
#define XELPD_DISPLAY_DC_OFF_POWER_DOMAINS ( \
|
||||
XELPD_PW_2_POWER_DOMAINS | \
|
||||
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
|
||||
BIT_ULL(POWER_DOMAIN_MODESET) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_A) | \
|
||||
BIT_ULL(POWER_DOMAIN_AUX_B) | \
|
||||
|
|
@ -3695,148 +3681,6 @@ static const struct i915_power_well_desc glk_power_wells[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static const struct i915_power_well_desc cnl_power_wells[] = {
|
||||
{
|
||||
.name = "always-on",
|
||||
.always_on = true,
|
||||
.domains = POWER_DOMAIN_MASK,
|
||||
.ops = &i9xx_always_on_power_well_ops,
|
||||
.id = DISP_PW_ID_NONE,
|
||||
},
|
||||
{
|
||||
.name = "power well 1",
|
||||
/* Handled by the DMC firmware */
|
||||
.always_on = true,
|
||||
.domains = 0,
|
||||
.ops = &hsw_power_well_ops,
|
||||
.id = SKL_DISP_PW_1,
|
||||
{
|
||||
.hsw.regs = &hsw_power_well_regs,
|
||||
.hsw.idx = SKL_PW_CTL_IDX_PW_1,
|
||||
.hsw.has_fuses = true,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "AUX A",
|
||||
.domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
|
||||
.ops = &hsw_power_well_ops,
|
||||
.id = DISP_PW_ID_NONE,
|
||||
{
|
||||
.hsw.regs = &hsw_power_well_regs,
|
||||
.hsw.idx = GLK_PW_CTL_IDX_AUX_A,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "AUX B",
|
||||
.domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
|
||||
.ops = &hsw_power_well_ops,
|
||||
.id = DISP_PW_ID_NONE,
|
||||
{
|
||||
.hsw.regs = &hsw_power_well_regs,
|
||||
.hsw.idx = GLK_PW_CTL_IDX_AUX_B,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "AUX C",
|
||||
.domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
|
||||
.ops = &hsw_power_well_ops,
|
||||
.id = DISP_PW_ID_NONE,
|
||||
{
|
||||
.hsw.regs = &hsw_power_well_regs,
|
||||
.hsw.idx = GLK_PW_CTL_IDX_AUX_C,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "AUX D",
|
||||
.domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
|
||||
.ops = &hsw_power_well_ops,
|
||||
.id = DISP_PW_ID_NONE,
|
||||
{
|
||||
.hsw.regs = &hsw_power_well_regs,
|
||||
.hsw.idx = CNL_PW_CTL_IDX_AUX_D,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "DC off",
|
||||
.domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
|
||||
.ops = &gen9_dc_off_power_well_ops,
|
||||
.id = SKL_DISP_DC_OFF,
|
||||
},
|
||||
{
|
||||
.name = "power well 2",
|
||||
.domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
|
||||
.ops = &hsw_power_well_ops,
|
||||
.id = SKL_DISP_PW_2,
|
||||
{
|
||||
.hsw.regs = &hsw_power_well_regs,
|
||||
.hsw.idx = SKL_PW_CTL_IDX_PW_2,
|
||||
.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
|
||||
.hsw.has_vga = true,
|
||||
.hsw.has_fuses = true,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "DDI A IO power well",
|
||||
.domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
|
||||
.ops = &hsw_power_well_ops,
|
||||
.id = DISP_PW_ID_NONE,
|
||||
{
|
||||
.hsw.regs = &hsw_power_well_regs,
|
||||
.hsw.idx = GLK_PW_CTL_IDX_DDI_A,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "DDI B IO power well",
|
||||
.domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
|
||||
.ops = &hsw_power_well_ops,
|
||||
.id = DISP_PW_ID_NONE,
|
||||
{
|
||||
.hsw.regs = &hsw_power_well_regs,
|
||||
.hsw.idx = SKL_PW_CTL_IDX_DDI_B,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "DDI C IO power well",
|
||||
.domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
|
||||
.ops = &hsw_power_well_ops,
|
||||
.id = DISP_PW_ID_NONE,
|
||||
{
|
||||
.hsw.regs = &hsw_power_well_regs,
|
||||
.hsw.idx = SKL_PW_CTL_IDX_DDI_C,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "DDI D IO power well",
|
||||
.domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
|
||||
.ops = &hsw_power_well_ops,
|
||||
.id = DISP_PW_ID_NONE,
|
||||
{
|
||||
.hsw.regs = &hsw_power_well_regs,
|
||||
.hsw.idx = SKL_PW_CTL_IDX_DDI_D,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "DDI F IO power well",
|
||||
.domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
|
||||
.ops = &hsw_power_well_ops,
|
||||
.id = CNL_DISP_PW_DDI_F_IO,
|
||||
{
|
||||
.hsw.regs = &hsw_power_well_regs,
|
||||
.hsw.idx = CNL_PW_CTL_IDX_DDI_F,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "AUX F",
|
||||
.domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
|
||||
.ops = &hsw_power_well_ops,
|
||||
.id = CNL_DISP_PW_DDI_F_AUX,
|
||||
{
|
||||
.hsw.regs = &hsw_power_well_regs,
|
||||
.hsw.idx = CNL_PW_CTL_IDX_AUX_F,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct i915_power_well_ops icl_aux_power_well_ops = {
|
||||
.sync_hw = hsw_power_well_sync_hw,
|
||||
.enable = icl_aux_power_well_enable,
|
||||
|
|
@ -4643,6 +4487,165 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static const struct i915_power_well_desc dg1_power_wells[] = {
|
||||
{
|
||||
.name = "always-on",
|
||||
.always_on = true,
|
||||
.domains = POWER_DOMAIN_MASK,
|
||||
.ops = &i9xx_always_on_power_well_ops,
|
||||
.id = DISP_PW_ID_NONE,
|
||||
},
|
||||
{
|
||||
.name = "power well 1",
|
||||
/* Handled by the DMC firmware */
|
||||
.always_on = true,
|
||||
.domains = 0,
|
||||
.ops = &hsw_power_well_ops,
|
||||
.id = SKL_DISP_PW_1,
|
||||
{
|
||||
.hsw.regs = &hsw_power_well_regs,
|
||||
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
|
||||
.hsw.has_fuses = true,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "DC off",
|
||||
.domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
|
||||
.ops = &gen9_dc_off_power_well_ops,
|
||||
.id = SKL_DISP_DC_OFF,
|
||||
},
|
||||
{
|
||||
.name = "power well 2",
|
||||
.domains = DG1_PW_2_POWER_DOMAINS,
|
||||
.ops = &hsw_power_well_ops,
|
||||
.id = SKL_DISP_PW_2,
|
||||
{
|
||||
.hsw.regs = &hsw_power_well_regs,
|
||||
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
|
||||
.hsw.has_fuses = true,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "power well 3",
|
||||
.domains = DG1_PW_3_POWER_DOMAINS,
|
||||
.ops = &hsw_power_well_ops,
|
||||
.id = ICL_DISP_PW_3,
|
||||
{
|
||||
.hsw.regs = &hsw_power_well_regs,
|
||||
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
|
||||
.hsw.irq_pipe_mask = BIT(PIPE_B),
|
||||
.hsw.has_vga = true,
|
||||
.hsw.has_fuses = true,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "DDI A IO",
|
||||
.domains = ICL_DDI_IO_A_POWER_DOMAINS,
|
||||
.ops = &hsw_power_well_ops,
|
||||
.id = DISP_PW_ID_NONE,
|
||||
{
|
||||
.hsw.regs = &icl_ddi_power_well_regs,
|
||||
.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
|
||||
}
|
||||
},
|
||||
{
|
||||
.name = "DDI B IO",
|
||||
.domains = ICL_DDI_IO_B_POWER_DOMAINS,
|
||||
.ops = &hsw_power_well_ops,
|
||||
.id = DISP_PW_ID_NONE,
|
||||
{
|
||||
.hsw.regs = &icl_ddi_power_well_regs,
|
||||
.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
|
||||
}
|
||||
},
|
||||
{
|
||||
.name = "DDI IO TC1",
|
||||
.domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
|
||||
.ops = &hsw_power_well_ops,
|
||||
.id = DISP_PW_ID_NONE,
|
||||
{
|
||||
.hsw.regs = &icl_ddi_power_well_regs,
|
||||
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "DDI IO TC2",
|
||||
.domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
|
||||
.ops = &hsw_power_well_ops,
|
||||
.id = DISP_PW_ID_NONE,
|
||||
{
|
||||
.hsw.regs = &icl_ddi_power_well_regs,
|
||||
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "AUX A",
|
||||
.domains = TGL_AUX_A_IO_POWER_DOMAINS,
|
||||
.ops = &icl_aux_power_well_ops,
|
||||
.id = DISP_PW_ID_NONE,
|
||||
{
|
||||
.hsw.regs = &icl_aux_power_well_regs,
|
||||
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "AUX B",
|
||||
.domains = TGL_AUX_B_IO_POWER_DOMAINS,
|
||||
.ops = &icl_aux_power_well_ops,
|
||||
.id = DISP_PW_ID_NONE,
|
||||
{
|
||||
.hsw.regs = &icl_aux_power_well_regs,
|
||||
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "AUX USBC1",
|
||||
.domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
|
||||
.ops = &icl_aux_power_well_ops,
|
||||
.id = DISP_PW_ID_NONE,
|
||||
{
|
||||
.hsw.regs = &icl_aux_power_well_regs,
|
||||
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
|
||||
.hsw.is_tc_tbt = false,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "AUX USBC2",
|
||||
.domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
|
||||
.ops = &icl_aux_power_well_ops,
|
||||
.id = DISP_PW_ID_NONE,
|
||||
{
|
||||
.hsw.regs = &icl_aux_power_well_regs,
|
||||
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
|
||||
.hsw.is_tc_tbt = false,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "power well 4",
|
||||
.domains = TGL_PW_4_POWER_DOMAINS,
|
||||
.ops = &hsw_power_well_ops,
|
||||
.id = DISP_PW_ID_NONE,
|
||||
{
|
||||
.hsw.regs = &hsw_power_well_regs,
|
||||
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
|
||||
.hsw.has_fuses = true,
|
||||
.hsw.irq_pipe_mask = BIT(PIPE_C),
|
||||
}
|
||||
},
|
||||
{
|
||||
.name = "power well 5",
|
||||
.domains = TGL_PW_5_POWER_DOMAINS,
|
||||
.ops = &hsw_power_well_ops,
|
||||
.id = DISP_PW_ID_NONE,
|
||||
{
|
||||
.hsw.regs = &hsw_power_well_regs,
|
||||
.hsw.idx = TGL_PW_CTL_IDX_PW_5,
|
||||
.hsw.has_fuses = true,
|
||||
.hsw.irq_pipe_mask = BIT(PIPE_D),
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct i915_power_well_desc xelpd_power_wells[] = {
|
||||
{
|
||||
.name = "always-on",
|
||||
|
|
@ -4828,6 +4831,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
|
|||
{
|
||||
.hsw.regs = &icl_aux_power_well_regs,
|
||||
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
|
||||
.hsw.fixed_enable_delay = 600,
|
||||
},
|
||||
},
|
||||
{
|
||||
|
|
@ -4838,6 +4842,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
|
|||
{
|
||||
.hsw.regs = &icl_aux_power_well_regs,
|
||||
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
|
||||
.hsw.fixed_enable_delay = 600,
|
||||
},
|
||||
},
|
||||
{
|
||||
|
|
@ -4848,6 +4853,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
|
|||
{
|
||||
.hsw.regs = &icl_aux_power_well_regs,
|
||||
.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
|
||||
.hsw.fixed_enable_delay = 600,
|
||||
},
|
||||
},
|
||||
{
|
||||
|
|
@ -4858,6 +4864,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
|
|||
{
|
||||
.hsw.regs = &icl_aux_power_well_regs,
|
||||
.hsw.idx = XELPD_PW_CTL_IDX_AUX_D,
|
||||
.hsw.fixed_enable_delay = 600,
|
||||
},
|
||||
},
|
||||
{
|
||||
|
|
@ -4878,6 +4885,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
|
|||
{
|
||||
.hsw.regs = &icl_aux_power_well_regs,
|
||||
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
|
||||
.hsw.fixed_enable_delay = 600,
|
||||
},
|
||||
},
|
||||
{
|
||||
|
|
@ -5122,7 +5130,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
|
|||
err = 0;
|
||||
} else if (DISPLAY_VER(dev_priv) >= 13) {
|
||||
err = set_power_wells(power_domains, xelpd_power_wells);
|
||||
} else if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
|
||||
} else if (IS_DG1(dev_priv)) {
|
||||
err = set_power_wells(power_domains, dg1_power_wells);
|
||||
} else if (IS_ALDERLAKE_S(dev_priv)) {
|
||||
err = set_power_wells_mask(power_domains, tgl_power_wells,
|
||||
BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
|
||||
} else if (IS_ROCKETLAKE(dev_priv)) {
|
||||
|
|
@ -5131,12 +5141,6 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
|
|||
err = set_power_wells(power_domains, tgl_power_wells);
|
||||
} else if (DISPLAY_VER(dev_priv) == 11) {
|
||||
err = set_power_wells(power_domains, icl_power_wells);
|
||||
} else if (IS_CNL_WITH_PORT_F(dev_priv)) {
|
||||
err = set_power_wells(power_domains, cnl_power_wells);
|
||||
} else if (IS_CANNONLAKE(dev_priv)) {
|
||||
err = set_power_wells_mask(power_domains, cnl_power_wells,
|
||||
BIT_ULL(CNL_DISP_PW_DDI_F_IO) |
|
||||
BIT_ULL(CNL_DISP_PW_DDI_F_AUX));
|
||||
} else if (IS_GEMINILAKE(dev_priv)) {
|
||||
err = set_power_wells(power_domains, glk_power_wells);
|
||||
} else if (IS_BROXTON(dev_priv)) {
|
||||
|
|
@ -5691,75 +5695,6 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
|
|||
usleep_range(10, 30); /* 10 us delay per Bspec */
|
||||
}
|
||||
|
||||
static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
|
||||
{
|
||||
struct i915_power_domains *power_domains = &dev_priv->power_domains;
|
||||
struct i915_power_well *well;
|
||||
|
||||
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
|
||||
|
||||
/* 1. Enable PCH Reset Handshake */
|
||||
intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
|
||||
|
||||
if (!HAS_DISPLAY(dev_priv))
|
||||
return;
|
||||
|
||||
/* 2-3. */
|
||||
intel_combo_phy_init(dev_priv);
|
||||
|
||||
/*
|
||||
* 4. Enable Power Well 1 (PG1).
|
||||
* The AUX IO power wells will be enabled on demand.
|
||||
*/
|
||||
mutex_lock(&power_domains->lock);
|
||||
well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
|
||||
intel_power_well_enable(dev_priv, well);
|
||||
mutex_unlock(&power_domains->lock);
|
||||
|
||||
/* 5. Enable CD clock */
|
||||
intel_cdclk_init_hw(dev_priv);
|
||||
|
||||
/* 6. Enable DBUF */
|
||||
gen9_dbuf_enable(dev_priv);
|
||||
|
||||
if (resume && intel_dmc_has_payload(dev_priv))
|
||||
intel_dmc_load_program(dev_priv);
|
||||
}
|
||||
|
||||
static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct i915_power_domains *power_domains = &dev_priv->power_domains;
|
||||
struct i915_power_well *well;
|
||||
|
||||
if (!HAS_DISPLAY(dev_priv))
|
||||
return;
|
||||
|
||||
gen9_disable_dc_states(dev_priv);
|
||||
|
||||
/* 1. Disable all display engine functions -> aready done */
|
||||
|
||||
/* 2. Disable DBUF */
|
||||
gen9_dbuf_disable(dev_priv);
|
||||
|
||||
/* 3. Disable CD clock */
|
||||
intel_cdclk_uninit_hw(dev_priv);
|
||||
|
||||
/*
|
||||
* 4. Disable Power Well 1 (PG1).
|
||||
* The AUX IO power wells are toggled on demand, so they are already
|
||||
* disabled at this point.
|
||||
*/
|
||||
mutex_lock(&power_domains->lock);
|
||||
well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
|
||||
intel_power_well_disable(dev_priv, well);
|
||||
mutex_unlock(&power_domains->lock);
|
||||
|
||||
usleep_range(10, 30); /* 10 us delay per Bspec */
|
||||
|
||||
/* 5. */
|
||||
intel_combo_phy_uninit(dev_priv);
|
||||
}
|
||||
|
||||
struct buddy_page_mask {
|
||||
u32 page_mask;
|
||||
u8 type;
|
||||
|
|
@ -5798,9 +5733,14 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
|
|||
unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
|
||||
int config, i;
|
||||
|
||||
/* BW_BUDDY registers are not used on dgpu's beyond DG1 */
|
||||
if (IS_DGFX(dev_priv) && !IS_DG1(dev_priv))
|
||||
return;
|
||||
|
||||
if (IS_ALDERLAKE_S(dev_priv) ||
|
||||
IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
|
||||
IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
|
||||
IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
|
||||
IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
|
||||
IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
|
||||
/* Wa_1409767108:tgl,dg1,adl-s */
|
||||
table = wa_1409767108_buddy_page_masks;
|
||||
else
|
||||
|
|
@ -5822,10 +5762,11 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
|
|||
intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i),
|
||||
table[config].page_mask);
|
||||
|
||||
/* Wa_22010178259:tgl,rkl */
|
||||
intel_de_rmw(dev_priv, BW_BUDDY_CTL(i),
|
||||
BW_BUDDY_TLB_REQ_TIMER_MASK,
|
||||
BW_BUDDY_TLB_REQ_TIMER(0x8));
|
||||
/* Wa_22010178259:tgl,dg1,rkl,adl-s */
|
||||
if (DISPLAY_VER(dev_priv) == 12)
|
||||
intel_de_rmw(dev_priv, BW_BUDDY_CTL(i),
|
||||
BW_BUDDY_TLB_REQ_TIMER_MASK,
|
||||
BW_BUDDY_TLB_REQ_TIMER(0x8));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -5879,11 +5820,15 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
|
|||
if (DISPLAY_VER(dev_priv) >= 12)
|
||||
tgl_bw_buddy_init(dev_priv);
|
||||
|
||||
/* 8. Ensure PHYs have completed calibration and adaptation */
|
||||
if (IS_DG2(dev_priv))
|
||||
intel_snps_phy_wait_for_calibration(dev_priv);
|
||||
|
||||
if (resume && intel_dmc_has_payload(dev_priv))
|
||||
intel_dmc_load_program(dev_priv);
|
||||
|
||||
/* Wa_14011508470 */
|
||||
if (DISPLAY_VER(dev_priv) == 12) {
|
||||
/* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p */
|
||||
if (DISPLAY_VER(dev_priv) >= 12) {
|
||||
val = DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM |
|
||||
DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR;
|
||||
intel_uncore_rmw(&dev_priv->uncore, GEN11_CHICKEN_DCPR_2, 0, val);
|
||||
|
|
@ -6098,8 +6043,6 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
|
|||
|
||||
if (DISPLAY_VER(i915) >= 11) {
|
||||
icl_display_core_init(i915, resume);
|
||||
} else if (IS_CANNONLAKE(i915)) {
|
||||
cnl_display_core_init(i915, resume);
|
||||
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
|
||||
bxt_display_core_init(i915, resume);
|
||||
} else if (DISPLAY_VER(i915) == 9) {
|
||||
|
|
@ -6259,8 +6202,6 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
|
|||
|
||||
if (DISPLAY_VER(i915) >= 11)
|
||||
icl_display_core_uninit(i915);
|
||||
else if (IS_CANNONLAKE(i915))
|
||||
cnl_display_core_uninit(i915);
|
||||
else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
|
||||
bxt_display_core_uninit(i915);
|
||||
else if (DISPLAY_VER(i915) == 9)
|
||||
|
|
|
|||
|
|
@ -76,7 +76,8 @@ enum intel_display_power_domain {
|
|||
POWER_DOMAIN_PORT_CRT,
|
||||
POWER_DOMAIN_PORT_OTHER,
|
||||
POWER_DOMAIN_VGA,
|
||||
POWER_DOMAIN_AUDIO,
|
||||
POWER_DOMAIN_AUDIO_MMIO,
|
||||
POWER_DOMAIN_AUDIO_PLAYBACK,
|
||||
POWER_DOMAIN_AUX_A,
|
||||
POWER_DOMAIN_AUX_B,
|
||||
POWER_DOMAIN_AUX_C,
|
||||
|
|
@ -142,8 +143,6 @@ enum i915_power_well_id {
|
|||
SKL_DISP_PW_MISC_IO,
|
||||
SKL_DISP_PW_1,
|
||||
SKL_DISP_PW_2,
|
||||
CNL_DISP_PW_DDI_F_IO,
|
||||
CNL_DISP_PW_DDI_F_AUX,
|
||||
ICL_DISP_PW_3,
|
||||
SKL_DISP_DC_OFF,
|
||||
TGL_DISP_PW_TC_COLD_OFF,
|
||||
|
|
@ -223,6 +222,12 @@ struct i915_power_well_desc {
|
|||
u8 idx;
|
||||
/* Mask of pipes whose IRQ logic is backed by the pw */
|
||||
u8 irq_pipe_mask;
|
||||
/*
|
||||
* Instead of waiting for the status bit to ack enables,
|
||||
* just wait a specific amount of time and then consider
|
||||
* the well enabled.
|
||||
*/
|
||||
u16 fixed_enable_delay;
|
||||
/* The pw is backing the VGA functionality */
|
||||
bool has_vga:1;
|
||||
bool has_fuses:1;
|
||||
|
|
@ -386,6 +391,10 @@ intel_display_power_put_all_in_set(struct drm_i915_private *i915,
|
|||
intel_display_power_put_mask_in_set(i915, power_domain_set, power_domain_set->mask);
|
||||
}
|
||||
|
||||
/*
|
||||
* FIXME: We should probably switch this to a 0-based scheme to be consistent
|
||||
* with how we now name/number DBUF_CTL instances.
|
||||
*/
|
||||
enum dbuf_slice {
|
||||
DBUF_S1,
|
||||
DBUF_S2,
|
||||
|
|
|
|||
|
|
@ -196,6 +196,10 @@ struct intel_encoder {
|
|||
void (*update_complete)(struct intel_atomic_state *,
|
||||
struct intel_encoder *,
|
||||
struct intel_crtc *);
|
||||
void (*pre_disable)(struct intel_atomic_state *,
|
||||
struct intel_encoder *,
|
||||
const struct intel_crtc_state *,
|
||||
const struct drm_connector_state *);
|
||||
void (*disable)(struct intel_atomic_state *,
|
||||
struct intel_encoder *,
|
||||
const struct intel_crtc_state *,
|
||||
|
|
@ -884,6 +888,18 @@ enum intel_output_format {
|
|||
INTEL_OUTPUT_FORMAT_YCBCR444,
|
||||
};
|
||||
|
||||
struct intel_mpllb_state {
|
||||
u32 clock; /* in KHz */
|
||||
u32 ref_control;
|
||||
u32 mpllb_cp;
|
||||
u32 mpllb_div;
|
||||
u32 mpllb_div2;
|
||||
u32 mpllb_fracn1;
|
||||
u32 mpllb_fracn2;
|
||||
u32 mpllb_sscen;
|
||||
u32 mpllb_sscstep;
|
||||
};
|
||||
|
||||
struct intel_crtc_state {
|
||||
/*
|
||||
* uapi (drm) state. This is the software state shown to userspace.
|
||||
|
|
@ -1018,7 +1034,10 @@ struct intel_crtc_state {
|
|||
struct intel_shared_dpll *shared_dpll;
|
||||
|
||||
/* Actual register state of the dpll, for shared dpll cross-checking. */
|
||||
struct intel_dpll_hw_state dpll_hw_state;
|
||||
union {
|
||||
struct intel_dpll_hw_state dpll_hw_state;
|
||||
struct intel_mpllb_state mpllb_state;
|
||||
};
|
||||
|
||||
/*
|
||||
* ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
|
||||
|
|
@ -1612,6 +1631,7 @@ struct intel_dp {
|
|||
|
||||
/* Display stream compression testing */
|
||||
bool force_dsc_en;
|
||||
int force_dsc_bpp;
|
||||
|
||||
bool hobl_failed;
|
||||
bool hobl_active;
|
||||
|
|
|
|||
|
|
@ -57,12 +57,12 @@ MODULE_FIRMWARE(ADLS_DMC_PATH);
|
|||
#define DG1_DMC_VERSION_REQUIRED DMC_VERSION(2, 2)
|
||||
MODULE_FIRMWARE(DG1_DMC_PATH);
|
||||
|
||||
#define RKL_DMC_PATH DMC_PATH(rkl, 2, 02)
|
||||
#define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 2)
|
||||
#define RKL_DMC_PATH DMC_PATH(rkl, 2, 03)
|
||||
#define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 3)
|
||||
MODULE_FIRMWARE(RKL_DMC_PATH);
|
||||
|
||||
#define TGL_DMC_PATH DMC_PATH(tgl, 2, 08)
|
||||
#define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 8)
|
||||
#define TGL_DMC_PATH DMC_PATH(tgl, 2, 12)
|
||||
#define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 12)
|
||||
MODULE_FIRMWARE(TGL_DMC_PATH);
|
||||
|
||||
#define ICL_DMC_PATH DMC_PATH(icl, 1, 09)
|
||||
|
|
@ -70,11 +70,6 @@ MODULE_FIRMWARE(TGL_DMC_PATH);
|
|||
#define ICL_DMC_MAX_FW_SIZE 0x6000
|
||||
MODULE_FIRMWARE(ICL_DMC_PATH);
|
||||
|
||||
#define CNL_DMC_PATH DMC_PATH(cnl, 1, 07)
|
||||
#define CNL_DMC_VERSION_REQUIRED DMC_VERSION(1, 7)
|
||||
#define CNL_DMC_MAX_FW_SIZE GLK_DMC_MAX_FW_SIZE
|
||||
MODULE_FIRMWARE(CNL_DMC_PATH);
|
||||
|
||||
#define GLK_DMC_PATH DMC_PATH(glk, 1, 04)
|
||||
#define GLK_DMC_VERSION_REQUIRED DMC_VERSION(1, 4)
|
||||
#define GLK_DMC_MAX_FW_SIZE 0x4000
|
||||
|
|
@ -247,50 +242,15 @@ bool intel_dmc_has_payload(struct drm_i915_private *i915)
|
|||
return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
|
||||
}
|
||||
|
||||
static const struct stepping_info skl_stepping_info[] = {
|
||||
{'A', '0'}, {'B', '0'}, {'C', '0'},
|
||||
{'D', '0'}, {'E', '0'}, {'F', '0'},
|
||||
{'G', '0'}, {'H', '0'}, {'I', '0'},
|
||||
{'J', '0'}, {'K', '0'}
|
||||
};
|
||||
|
||||
static const struct stepping_info bxt_stepping_info[] = {
|
||||
{'A', '0'}, {'A', '1'}, {'A', '2'},
|
||||
{'B', '0'}, {'B', '1'}, {'B', '2'}
|
||||
};
|
||||
|
||||
static const struct stepping_info icl_stepping_info[] = {
|
||||
{'A', '0'}, {'A', '1'}, {'A', '2'},
|
||||
{'B', '0'}, {'B', '2'},
|
||||
{'C', '0'}
|
||||
};
|
||||
|
||||
static const struct stepping_info no_stepping_info = { '*', '*' };
|
||||
|
||||
static const struct stepping_info *
|
||||
intel_get_stepping_info(struct drm_i915_private *dev_priv)
|
||||
intel_get_stepping_info(struct drm_i915_private *i915,
|
||||
struct stepping_info *si)
|
||||
{
|
||||
const struct stepping_info *si;
|
||||
unsigned int size;
|
||||
const char *step_name = intel_step_name(RUNTIME_INFO(i915)->step.display_step);
|
||||
|
||||
if (IS_ICELAKE(dev_priv)) {
|
||||
size = ARRAY_SIZE(icl_stepping_info);
|
||||
si = icl_stepping_info;
|
||||
} else if (IS_SKYLAKE(dev_priv)) {
|
||||
size = ARRAY_SIZE(skl_stepping_info);
|
||||
si = skl_stepping_info;
|
||||
} else if (IS_BROXTON(dev_priv)) {
|
||||
size = ARRAY_SIZE(bxt_stepping_info);
|
||||
si = bxt_stepping_info;
|
||||
} else {
|
||||
size = 0;
|
||||
si = NULL;
|
||||
}
|
||||
|
||||
if (INTEL_REVID(dev_priv) < size)
|
||||
return si + INTEL_REVID(dev_priv);
|
||||
|
||||
return &no_stepping_info;
|
||||
si->stepping = step_name[0];
|
||||
si->substepping = step_name[1];
|
||||
return si;
|
||||
}
|
||||
|
||||
static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
|
||||
|
|
@ -616,7 +576,8 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
|
|||
struct intel_package_header *package_header;
|
||||
struct intel_dmc_header_base *dmc_header;
|
||||
struct intel_dmc *dmc = &dev_priv->dmc;
|
||||
const struct stepping_info *si = intel_get_stepping_info(dev_priv);
|
||||
struct stepping_info display_info = { '*', '*'};
|
||||
const struct stepping_info *si = intel_get_stepping_info(dev_priv, &display_info);
|
||||
u32 readcount = 0;
|
||||
u32 r, offset;
|
||||
int id;
|
||||
|
|
@ -752,10 +713,6 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
|
|||
dmc->fw_path = ICL_DMC_PATH;
|
||||
dmc->required_version = ICL_DMC_VERSION_REQUIRED;
|
||||
dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE;
|
||||
} else if (IS_CANNONLAKE(dev_priv)) {
|
||||
dmc->fw_path = CNL_DMC_PATH;
|
||||
dmc->required_version = CNL_DMC_VERSION_REQUIRED;
|
||||
dmc->max_fw_size = CNL_DMC_MAX_FW_SIZE;
|
||||
} else if (IS_GEMINILAKE(dev_priv)) {
|
||||
dmc->fw_path = GLK_DMC_PATH;
|
||||
dmc->required_version = GLK_DMC_VERSION_REQUIRED;
|
||||
|
|
|
|||
|
|
@ -222,29 +222,6 @@ bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
|
|||
encoder->port != PORT_A);
|
||||
}
|
||||
|
||||
static int cnl_max_source_rate(struct intel_dp *intel_dp)
|
||||
{
|
||||
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
||||
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
|
||||
enum port port = dig_port->base.port;
|
||||
|
||||
u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
|
||||
|
||||
/* Low voltage SKUs are limited to max of 5.4G */
|
||||
if (voltage == VOLTAGE_INFO_0_85V)
|
||||
return 540000;
|
||||
|
||||
/* For this SKU 8.1G is supported in all ports */
|
||||
if (IS_CNL_WITH_PORT_F(dev_priv))
|
||||
return 810000;
|
||||
|
||||
/* For other SKUs, max rate on ports A and D is 5.4G */
|
||||
if (port == PORT_A || port == PORT_D)
|
||||
return 540000;
|
||||
|
||||
return 810000;
|
||||
}
|
||||
|
||||
static int icl_max_source_rate(struct intel_dp *intel_dp)
|
||||
{
|
||||
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
||||
|
|
@ -270,7 +247,7 @@ static void
|
|||
intel_dp_set_source_rates(struct intel_dp *intel_dp)
|
||||
{
|
||||
/* The values must be in increasing order */
|
||||
static const int cnl_rates[] = {
|
||||
static const int icl_rates[] = {
|
||||
162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
|
||||
};
|
||||
static const int bxt_rates[] = {
|
||||
|
|
@ -295,12 +272,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
|
|||
drm_WARN_ON(&dev_priv->drm,
|
||||
intel_dp->source_rates || intel_dp->num_source_rates);
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
|
||||
source_rates = cnl_rates;
|
||||
size = ARRAY_SIZE(cnl_rates);
|
||||
if (DISPLAY_VER(dev_priv) == 10)
|
||||
max_rate = cnl_max_source_rate(intel_dp);
|
||||
else if (IS_JSL_EHL(dev_priv))
|
||||
if (DISPLAY_VER(dev_priv) >= 11) {
|
||||
source_rates = icl_rates;
|
||||
size = ARRAY_SIZE(icl_rates);
|
||||
if (IS_JSL_EHL(dev_priv))
|
||||
max_rate = ehl_max_source_rate(intel_dp);
|
||||
else
|
||||
max_rate = icl_max_source_rate(intel_dp);
|
||||
|
|
@ -1274,6 +1249,23 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
|
|||
pipe_config->pipe_bpp);
|
||||
pipe_config->dsc.slice_count = dsc_dp_slice_count;
|
||||
}
|
||||
|
||||
/* As of today we support DSC for only RGB */
|
||||
if (intel_dp->force_dsc_bpp) {
|
||||
if (intel_dp->force_dsc_bpp >= 8 &&
|
||||
intel_dp->force_dsc_bpp < pipe_bpp) {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"DSC BPP forced to %d",
|
||||
intel_dp->force_dsc_bpp);
|
||||
pipe_config->dsc.compressed_bpp =
|
||||
intel_dp->force_dsc_bpp;
|
||||
} else {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"Invalid DSC BPP %d",
|
||||
intel_dp->force_dsc_bpp);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
|
||||
* is greater than the maximum Cdclock and if slice count is even
|
||||
|
|
@ -3339,6 +3331,9 @@ static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
|
|||
|
||||
intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
|
||||
|
||||
drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
|
||||
intel_dp->train_set, crtc_state->lane_count);
|
||||
|
||||
drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
|
||||
link_status[DP_DPCD_REV]);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -158,7 +158,6 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
|
|||
/*
|
||||
* Max timeout values:
|
||||
* SKL-GLK: 1.6ms
|
||||
* CNL: 3.2ms
|
||||
* ICL+: 4ms
|
||||
*/
|
||||
ret = DP_AUX_CH_CTL_SEND_BUSY |
|
||||
|
|
|
|||
|
|
@ -348,6 +348,16 @@ static void wait_for_act_sent(struct intel_encoder *encoder,
|
|||
drm_dp_check_act_status(&intel_dp->mst_mgr);
|
||||
}
|
||||
|
||||
static void intel_mst_pre_disable_dp(struct intel_atomic_state *state,
|
||||
struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *old_crtc_state,
|
||||
const struct drm_connector_state *old_conn_state)
|
||||
{
|
||||
if (old_crtc_state->has_audio)
|
||||
intel_audio_codec_disable(encoder, old_crtc_state,
|
||||
old_conn_state);
|
||||
}
|
||||
|
||||
static void intel_mst_disable_dp(struct intel_atomic_state *state,
|
||||
struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *old_crtc_state,
|
||||
|
|
@ -372,9 +382,6 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state,
|
|||
if (ret) {
|
||||
drm_dbg_kms(&i915->drm, "failed to update payload %d\n", ret);
|
||||
}
|
||||
if (old_crtc_state->has_audio)
|
||||
intel_audio_codec_disable(encoder,
|
||||
old_crtc_state, old_conn_state);
|
||||
}
|
||||
|
||||
static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
|
||||
|
|
@ -542,7 +549,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
|
|||
struct intel_digital_port *dig_port = intel_mst->primary;
|
||||
struct intel_dp *intel_dp = &dig_port->dp;
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
u32 val;
|
||||
enum transcoder trans = pipe_config->cpu_transcoder;
|
||||
|
||||
drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
|
||||
|
||||
|
|
@ -550,12 +557,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
|
|||
|
||||
intel_ddi_enable_transcoder_func(encoder, pipe_config);
|
||||
|
||||
val = intel_de_read(dev_priv,
|
||||
TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
|
||||
val |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
|
||||
intel_de_write(dev_priv,
|
||||
TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder),
|
||||
val);
|
||||
intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0,
|
||||
TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm, "active links %d\n",
|
||||
intel_dp->active_mst_links);
|
||||
|
|
@ -564,6 +567,10 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
|
|||
|
||||
drm_dp_update_payload_part2(&intel_dp->mst_mgr);
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable)
|
||||
intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0,
|
||||
FECSTALL_DIS_DPTSTREAM_DPTTG);
|
||||
|
||||
intel_enable_pipe(pipe_config);
|
||||
|
||||
intel_crtc_vblank_on(pipe_config);
|
||||
|
|
@ -903,6 +910,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe
|
|||
|
||||
intel_encoder->compute_config = intel_dp_mst_compute_config;
|
||||
intel_encoder->compute_config_late = intel_dp_mst_compute_config_late;
|
||||
intel_encoder->pre_disable = intel_mst_pre_disable_dp;
|
||||
intel_encoder->disable = intel_mst_disable_dp;
|
||||
intel_encoder->post_disable = intel_mst_post_disable_dp;
|
||||
intel_encoder->update_pipe = intel_ddi_update_pipe;
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
#include "intel_lvds.h"
|
||||
#include "intel_panel.h"
|
||||
#include "intel_sideband.h"
|
||||
#include "display/intel_snps_phy.h"
|
||||
|
||||
struct intel_limit {
|
||||
struct {
|
||||
|
|
@ -923,12 +924,13 @@ static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
|
|||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
struct intel_atomic_state *state =
|
||||
to_intel_atomic_state(crtc_state->uapi.state);
|
||||
struct intel_encoder *encoder =
|
||||
intel_get_crtc_new_encoder(state, crtc_state);
|
||||
|
||||
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
|
||||
DISPLAY_VER(dev_priv) >= 11) {
|
||||
struct intel_encoder *encoder =
|
||||
intel_get_crtc_new_encoder(state, crtc_state);
|
||||
|
||||
if (IS_DG2(dev_priv)) {
|
||||
return intel_mpllb_calc_state(crtc_state, encoder);
|
||||
} else if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
|
||||
DISPLAY_VER(dev_priv) >= 11) {
|
||||
if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"failed to find PLL for pipe %c\n",
|
||||
|
|
|
|||
|
|
@ -168,7 +168,7 @@ intel_combo_pll_enable_reg(struct drm_i915_private *i915,
|
|||
else if (IS_JSL_EHL(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
|
||||
return MG_PLL_ENABLE(0);
|
||||
|
||||
return CNL_DPLL_ENABLE(pll->info->id);
|
||||
return ICL_DPLL_ENABLE(pll->info->id);
|
||||
}
|
||||
|
||||
static i915_reg_t
|
||||
|
|
@ -2346,160 +2346,7 @@ static const struct intel_dpll_mgr bxt_pll_mgr = {
|
|||
.dump_hw_state = bxt_dump_hw_state,
|
||||
};
|
||||
|
||||
static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
|
||||
struct intel_shared_dpll *pll)
|
||||
{
|
||||
const enum intel_dpll_id id = pll->info->id;
|
||||
u32 val;
|
||||
|
||||
/* 1. Enable DPLL power in DPLL_ENABLE. */
|
||||
val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
|
||||
val |= PLL_POWER_ENABLE;
|
||||
intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
|
||||
|
||||
/* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */
|
||||
if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id),
|
||||
PLL_POWER_STATE, 5))
|
||||
drm_err(&dev_priv->drm, "PLL %d Power not enabled\n", id);
|
||||
|
||||
/*
|
||||
* 3. Configure DPLL_CFGCR0 to set SSC enable/disable,
|
||||
* select DP mode, and set DP link rate.
|
||||
*/
|
||||
val = pll->state.hw_state.cfgcr0;
|
||||
intel_de_write(dev_priv, CNL_DPLL_CFGCR0(id), val);
|
||||
|
||||
/* 4. Reab back to ensure writes completed */
|
||||
intel_de_posting_read(dev_priv, CNL_DPLL_CFGCR0(id));
|
||||
|
||||
/* 3. Configure DPLL_CFGCR0 */
|
||||
/* Avoid touch CFGCR1 if HDMI mode is not enabled */
|
||||
if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
|
||||
val = pll->state.hw_state.cfgcr1;
|
||||
intel_de_write(dev_priv, CNL_DPLL_CFGCR1(id), val);
|
||||
/* 4. Reab back to ensure writes completed */
|
||||
intel_de_posting_read(dev_priv, CNL_DPLL_CFGCR1(id));
|
||||
}
|
||||
|
||||
/*
|
||||
* 5. If the frequency will result in a change to the voltage
|
||||
* requirement, follow the Display Voltage Frequency Switching
|
||||
* Sequence Before Frequency Change
|
||||
*
|
||||
* Note: DVFS is actually handled via the cdclk code paths,
|
||||
* hence we do nothing here.
|
||||
*/
|
||||
|
||||
/* 6. Enable DPLL in DPLL_ENABLE. */
|
||||
val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
|
||||
val |= PLL_ENABLE;
|
||||
intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
|
||||
|
||||
/* 7. Wait for PLL lock status in DPLL_ENABLE. */
|
||||
if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5))
|
||||
drm_err(&dev_priv->drm, "PLL %d not locked\n", id);
|
||||
|
||||
/*
|
||||
* 8. If the frequency will result in a change to the voltage
|
||||
* requirement, follow the Display Voltage Frequency Switching
|
||||
* Sequence After Frequency Change
|
||||
*
|
||||
* Note: DVFS is actually handled via the cdclk code paths,
|
||||
* hence we do nothing here.
|
||||
*/
|
||||
|
||||
/*
|
||||
* 9. turn on the clock for the DDI and map the DPLL to the DDI
|
||||
* Done at intel_ddi_clk_select
|
||||
*/
|
||||
}
|
||||
|
||||
static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
|
||||
struct intel_shared_dpll *pll)
|
||||
{
|
||||
const enum intel_dpll_id id = pll->info->id;
|
||||
u32 val;
|
||||
|
||||
/*
|
||||
* 1. Configure DPCLKA_CFGCR0 to turn off the clock for the DDI.
|
||||
* Done at intel_ddi_post_disable
|
||||
*/
|
||||
|
||||
/*
|
||||
* 2. If the frequency will result in a change to the voltage
|
||||
* requirement, follow the Display Voltage Frequency Switching
|
||||
* Sequence Before Frequency Change
|
||||
*
|
||||
* Note: DVFS is actually handled via the cdclk code paths,
|
||||
* hence we do nothing here.
|
||||
*/
|
||||
|
||||
/* 3. Disable DPLL through DPLL_ENABLE. */
|
||||
val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
|
||||
val &= ~PLL_ENABLE;
|
||||
intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
|
||||
|
||||
/* 4. Wait for PLL not locked status in DPLL_ENABLE. */
|
||||
if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5))
|
||||
drm_err(&dev_priv->drm, "PLL %d locked\n", id);
|
||||
|
||||
/*
|
||||
* 5. If the frequency will result in a change to the voltage
|
||||
* requirement, follow the Display Voltage Frequency Switching
|
||||
* Sequence After Frequency Change
|
||||
*
|
||||
* Note: DVFS is actually handled via the cdclk code paths,
|
||||
* hence we do nothing here.
|
||||
*/
|
||||
|
||||
/* 6. Disable DPLL power in DPLL_ENABLE. */
|
||||
val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
|
||||
val &= ~PLL_POWER_ENABLE;
|
||||
intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
|
||||
|
||||
/* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */
|
||||
if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id),
|
||||
PLL_POWER_STATE, 5))
|
||||
drm_err(&dev_priv->drm, "PLL %d Power not disabled\n", id);
|
||||
}
|
||||
|
||||
static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
|
||||
struct intel_shared_dpll *pll,
|
||||
struct intel_dpll_hw_state *hw_state)
|
||||
{
|
||||
const enum intel_dpll_id id = pll->info->id;
|
||||
intel_wakeref_t wakeref;
|
||||
u32 val;
|
||||
bool ret;
|
||||
|
||||
wakeref = intel_display_power_get_if_enabled(dev_priv,
|
||||
POWER_DOMAIN_DISPLAY_CORE);
|
||||
if (!wakeref)
|
||||
return false;
|
||||
|
||||
ret = false;
|
||||
|
||||
val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
|
||||
if (!(val & PLL_ENABLE))
|
||||
goto out;
|
||||
|
||||
val = intel_de_read(dev_priv, CNL_DPLL_CFGCR0(id));
|
||||
hw_state->cfgcr0 = val;
|
||||
|
||||
/* avoid reading back stale values if HDMI mode is not enabled */
|
||||
if (val & DPLL_CFGCR0_HDMI_MODE) {
|
||||
hw_state->cfgcr1 = intel_de_read(dev_priv,
|
||||
CNL_DPLL_CFGCR1(id));
|
||||
}
|
||||
ret = true;
|
||||
|
||||
out:
|
||||
intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void cnl_wrpll_get_multipliers(int bestdiv, int *pdiv,
|
||||
static void icl_wrpll_get_multipliers(int bestdiv, int *pdiv,
|
||||
int *qdiv, int *kdiv)
|
||||
{
|
||||
/* even dividers */
|
||||
|
|
@ -2538,7 +2385,7 @@ static void cnl_wrpll_get_multipliers(int bestdiv, int *pdiv,
|
|||
}
|
||||
}
|
||||
|
||||
static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
|
||||
static void icl_wrpll_params_populate(struct skl_wrpll_params *params,
|
||||
u32 dco_freq, u32 ref_freq,
|
||||
int pdiv, int qdiv, int kdiv)
|
||||
{
|
||||
|
|
@ -2586,86 +2433,6 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
|
|||
params->dco_fraction = dco & 0x7fff;
|
||||
}
|
||||
|
||||
static bool
|
||||
__cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
|
||||
struct skl_wrpll_params *wrpll_params,
|
||||
int ref_clock)
|
||||
{
|
||||
u32 afe_clock = crtc_state->port_clock * 5;
|
||||
u32 dco_min = 7998000;
|
||||
u32 dco_max = 10000000;
|
||||
u32 dco_mid = (dco_min + dco_max) / 2;
|
||||
static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16,
|
||||
18, 20, 24, 28, 30, 32, 36, 40,
|
||||
42, 44, 48, 50, 52, 54, 56, 60,
|
||||
64, 66, 68, 70, 72, 76, 78, 80,
|
||||
84, 88, 90, 92, 96, 98, 100, 102,
|
||||
3, 5, 7, 9, 15, 21 };
|
||||
u32 dco, best_dco = 0, dco_centrality = 0;
|
||||
u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */
|
||||
int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
|
||||
|
||||
for (d = 0; d < ARRAY_SIZE(dividers); d++) {
|
||||
dco = afe_clock * dividers[d];
|
||||
|
||||
if ((dco <= dco_max) && (dco >= dco_min)) {
|
||||
dco_centrality = abs(dco - dco_mid);
|
||||
|
||||
if (dco_centrality < best_dco_centrality) {
|
||||
best_dco_centrality = dco_centrality;
|
||||
best_div = dividers[d];
|
||||
best_dco = dco;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (best_div == 0)
|
||||
return false;
|
||||
|
||||
cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
|
||||
cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock,
|
||||
pdiv, qdiv, kdiv);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool
|
||||
cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
|
||||
struct skl_wrpll_params *wrpll_params)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
|
||||
|
||||
return __cnl_ddi_calculate_wrpll(crtc_state, wrpll_params,
|
||||
i915->dpll.ref_clks.nssc);
|
||||
}
|
||||
|
||||
static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
u32 cfgcr0, cfgcr1;
|
||||
struct skl_wrpll_params wrpll_params = { 0, };
|
||||
|
||||
cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
|
||||
|
||||
if (!cnl_ddi_calculate_wrpll(crtc_state, &wrpll_params))
|
||||
return false;
|
||||
|
||||
cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) |
|
||||
wrpll_params.dco_integer;
|
||||
|
||||
cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(wrpll_params.qdiv_ratio) |
|
||||
DPLL_CFGCR1_QDIV_MODE(wrpll_params.qdiv_mode) |
|
||||
DPLL_CFGCR1_KDIV(wrpll_params.kdiv) |
|
||||
DPLL_CFGCR1_PDIV(wrpll_params.pdiv) |
|
||||
DPLL_CFGCR1_CENTRAL_FREQ;
|
||||
|
||||
memset(&crtc_state->dpll_hw_state, 0,
|
||||
sizeof(crtc_state->dpll_hw_state));
|
||||
|
||||
crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;
|
||||
crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* Display WA #22010492432: ehl, tgl, adl-p
|
||||
* Program half of the nominal DCO divider fraction value.
|
||||
|
|
@ -2679,256 +2446,6 @@ ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
|
|||
i915->dpll.ref_clks.nssc == 38400;
|
||||
}
|
||||
|
||||
static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
|
||||
const struct intel_shared_dpll *pll,
|
||||
const struct intel_dpll_hw_state *pll_state,
|
||||
int ref_clock)
|
||||
{
|
||||
u32 dco_fraction;
|
||||
u32 p0, p1, p2, dco_freq;
|
||||
|
||||
p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
|
||||
p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
|
||||
|
||||
if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
|
||||
p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
|
||||
DPLL_CFGCR1_QDIV_RATIO_SHIFT;
|
||||
else
|
||||
p1 = 1;
|
||||
|
||||
|
||||
switch (p0) {
|
||||
case DPLL_CFGCR1_PDIV_2:
|
||||
p0 = 2;
|
||||
break;
|
||||
case DPLL_CFGCR1_PDIV_3:
|
||||
p0 = 3;
|
||||
break;
|
||||
case DPLL_CFGCR1_PDIV_5:
|
||||
p0 = 5;
|
||||
break;
|
||||
case DPLL_CFGCR1_PDIV_7:
|
||||
p0 = 7;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (p2) {
|
||||
case DPLL_CFGCR1_KDIV_1:
|
||||
p2 = 1;
|
||||
break;
|
||||
case DPLL_CFGCR1_KDIV_2:
|
||||
p2 = 2;
|
||||
break;
|
||||
case DPLL_CFGCR1_KDIV_3:
|
||||
p2 = 3;
|
||||
break;
|
||||
}
|
||||
|
||||
dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
|
||||
ref_clock;
|
||||
|
||||
dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
|
||||
DPLL_CFGCR0_DCO_FRACTION_SHIFT;
|
||||
|
||||
if (ehl_combo_pll_div_frac_wa_needed(dev_priv))
|
||||
dco_fraction *= 2;
|
||||
|
||||
dco_freq += (dco_fraction * ref_clock) / 0x8000;
|
||||
|
||||
if (drm_WARN_ON(&dev_priv->drm, p0 == 0 || p1 == 0 || p2 == 0))
|
||||
return 0;
|
||||
|
||||
return dco_freq / (p0 * p1 * p2 * 5);
|
||||
}
|
||||
|
||||
static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
|
||||
const struct intel_shared_dpll *pll,
|
||||
const struct intel_dpll_hw_state *pll_state)
|
||||
{
|
||||
return __cnl_ddi_wrpll_get_freq(i915, pll, pll_state,
|
||||
i915->dpll.ref_clks.nssc);
|
||||
}
|
||||
|
||||
static bool
|
||||
cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
u32 cfgcr0;
|
||||
|
||||
cfgcr0 = DPLL_CFGCR0_SSC_ENABLE;
|
||||
|
||||
switch (crtc_state->port_clock / 2) {
|
||||
case 81000:
|
||||
cfgcr0 |= DPLL_CFGCR0_LINK_RATE_810;
|
||||
break;
|
||||
case 135000:
|
||||
cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1350;
|
||||
break;
|
||||
case 270000:
|
||||
cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2700;
|
||||
break;
|
||||
/* eDP 1.4 rates */
|
||||
case 162000:
|
||||
cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1620;
|
||||
break;
|
||||
case 108000:
|
||||
cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1080;
|
||||
break;
|
||||
case 216000:
|
||||
cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2160;
|
||||
break;
|
||||
case 324000:
|
||||
/* Some SKUs may require elevated I/O voltage to support this */
|
||||
cfgcr0 |= DPLL_CFGCR0_LINK_RATE_3240;
|
||||
break;
|
||||
case 405000:
|
||||
/* Some SKUs may require elevated I/O voltage to support this */
|
||||
cfgcr0 |= DPLL_CFGCR0_LINK_RATE_4050;
|
||||
break;
|
||||
}
|
||||
|
||||
memset(&crtc_state->dpll_hw_state, 0,
|
||||
sizeof(crtc_state->dpll_hw_state));
|
||||
|
||||
crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static int cnl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
|
||||
const struct intel_shared_dpll *pll,
|
||||
const struct intel_dpll_hw_state *pll_state)
|
||||
{
|
||||
int link_clock = 0;
|
||||
|
||||
switch (pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK) {
|
||||
case DPLL_CFGCR0_LINK_RATE_810:
|
||||
link_clock = 81000;
|
||||
break;
|
||||
case DPLL_CFGCR0_LINK_RATE_1080:
|
||||
link_clock = 108000;
|
||||
break;
|
||||
case DPLL_CFGCR0_LINK_RATE_1350:
|
||||
link_clock = 135000;
|
||||
break;
|
||||
case DPLL_CFGCR0_LINK_RATE_1620:
|
||||
link_clock = 162000;
|
||||
break;
|
||||
case DPLL_CFGCR0_LINK_RATE_2160:
|
||||
link_clock = 216000;
|
||||
break;
|
||||
case DPLL_CFGCR0_LINK_RATE_2700:
|
||||
link_clock = 270000;
|
||||
break;
|
||||
case DPLL_CFGCR0_LINK_RATE_3240:
|
||||
link_clock = 324000;
|
||||
break;
|
||||
case DPLL_CFGCR0_LINK_RATE_4050:
|
||||
link_clock = 405000;
|
||||
break;
|
||||
default:
|
||||
drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
|
||||
break;
|
||||
}
|
||||
|
||||
return link_clock * 2;
|
||||
}
|
||||
|
||||
static bool cnl_get_dpll(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc,
|
||||
struct intel_encoder *encoder)
|
||||
{
|
||||
struct intel_crtc_state *crtc_state =
|
||||
intel_atomic_get_new_crtc_state(state, crtc);
|
||||
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
|
||||
struct intel_shared_dpll *pll;
|
||||
bool bret;
|
||||
|
||||
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
|
||||
bret = cnl_ddi_hdmi_pll_dividers(crtc_state);
|
||||
if (!bret) {
|
||||
drm_dbg_kms(&i915->drm,
|
||||
"Could not get HDMI pll dividers.\n");
|
||||
return false;
|
||||
}
|
||||
} else if (intel_crtc_has_dp_encoder(crtc_state)) {
|
||||
bret = cnl_ddi_dp_set_dpll_hw_state(crtc_state);
|
||||
if (!bret) {
|
||||
drm_dbg_kms(&i915->drm,
|
||||
"Could not set DP dpll HW state.\n");
|
||||
return false;
|
||||
}
|
||||
} else {
|
||||
drm_dbg_kms(&i915->drm,
|
||||
"Skip DPLL setup for output_types 0x%x\n",
|
||||
crtc_state->output_types);
|
||||
return false;
|
||||
}
|
||||
|
||||
pll = intel_find_shared_dpll(state, crtc,
|
||||
&crtc_state->dpll_hw_state,
|
||||
BIT(DPLL_ID_SKL_DPLL2) |
|
||||
BIT(DPLL_ID_SKL_DPLL1) |
|
||||
BIT(DPLL_ID_SKL_DPLL0));
|
||||
if (!pll) {
|
||||
drm_dbg_kms(&i915->drm, "No PLL selected\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
intel_reference_shared_dpll(state, crtc,
|
||||
pll, &crtc_state->dpll_hw_state);
|
||||
|
||||
crtc_state->shared_dpll = pll;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static int cnl_ddi_pll_get_freq(struct drm_i915_private *i915,
|
||||
const struct intel_shared_dpll *pll,
|
||||
const struct intel_dpll_hw_state *pll_state)
|
||||
{
|
||||
if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE)
|
||||
return cnl_ddi_wrpll_get_freq(i915, pll, pll_state);
|
||||
else
|
||||
return cnl_ddi_lcpll_get_freq(i915, pll, pll_state);
|
||||
}
|
||||
|
||||
static void cnl_update_dpll_ref_clks(struct drm_i915_private *i915)
|
||||
{
|
||||
/* No SSC reference */
|
||||
i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
|
||||
}
|
||||
|
||||
static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
|
||||
const struct intel_dpll_hw_state *hw_state)
|
||||
{
|
||||
drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: "
|
||||
"cfgcr0: 0x%x, cfgcr1: 0x%x\n",
|
||||
hw_state->cfgcr0,
|
||||
hw_state->cfgcr1);
|
||||
}
|
||||
|
||||
static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
|
||||
.enable = cnl_ddi_pll_enable,
|
||||
.disable = cnl_ddi_pll_disable,
|
||||
.get_hw_state = cnl_ddi_pll_get_hw_state,
|
||||
.get_freq = cnl_ddi_pll_get_freq,
|
||||
};
|
||||
|
||||
static const struct dpll_info cnl_plls[] = {
|
||||
{ "DPLL 0", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
|
||||
{ "DPLL 1", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
|
||||
{ "DPLL 2", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
|
||||
{ },
|
||||
};
|
||||
|
||||
static const struct intel_dpll_mgr cnl_pll_mgr = {
|
||||
.dpll_info = cnl_plls,
|
||||
.get_dplls = cnl_get_dpll,
|
||||
.put_dplls = intel_put_dpll,
|
||||
.update_ref_clks = cnl_update_dpll_ref_clks,
|
||||
.dump_hw_state = cnl_dump_hw_state,
|
||||
};
|
||||
|
||||
struct icl_combo_pll_params {
|
||||
int clock;
|
||||
struct skl_wrpll_params wrpll;
|
||||
|
|
@ -3105,17 +2622,104 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
|
|||
struct skl_wrpll_params *wrpll_params)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
|
||||
int ref_clock = icl_wrpll_ref_clock(i915);
|
||||
u32 afe_clock = crtc_state->port_clock * 5;
|
||||
u32 dco_min = 7998000;
|
||||
u32 dco_max = 10000000;
|
||||
u32 dco_mid = (dco_min + dco_max) / 2;
|
||||
static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16,
|
||||
18, 20, 24, 28, 30, 32, 36, 40,
|
||||
42, 44, 48, 50, 52, 54, 56, 60,
|
||||
64, 66, 68, 70, 72, 76, 78, 80,
|
||||
84, 88, 90, 92, 96, 98, 100, 102,
|
||||
3, 5, 7, 9, 15, 21 };
|
||||
u32 dco, best_dco = 0, dco_centrality = 0;
|
||||
u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */
|
||||
int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
|
||||
|
||||
return __cnl_ddi_calculate_wrpll(crtc_state, wrpll_params,
|
||||
icl_wrpll_ref_clock(i915));
|
||||
for (d = 0; d < ARRAY_SIZE(dividers); d++) {
|
||||
dco = afe_clock * dividers[d];
|
||||
|
||||
if (dco <= dco_max && dco >= dco_min) {
|
||||
dco_centrality = abs(dco - dco_mid);
|
||||
|
||||
if (dco_centrality < best_dco_centrality) {
|
||||
best_dco_centrality = dco_centrality;
|
||||
best_div = dividers[d];
|
||||
best_dco = dco;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (best_div == 0)
|
||||
return false;
|
||||
|
||||
icl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
|
||||
icl_wrpll_params_populate(wrpll_params, best_dco, ref_clock,
|
||||
pdiv, qdiv, kdiv);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
|
||||
const struct intel_shared_dpll *pll,
|
||||
const struct intel_dpll_hw_state *pll_state)
|
||||
{
|
||||
return __cnl_ddi_wrpll_get_freq(i915, pll, pll_state,
|
||||
icl_wrpll_ref_clock(i915));
|
||||
int ref_clock = icl_wrpll_ref_clock(i915);
|
||||
u32 dco_fraction;
|
||||
u32 p0, p1, p2, dco_freq;
|
||||
|
||||
p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
|
||||
p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
|
||||
|
||||
if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
|
||||
p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
|
||||
DPLL_CFGCR1_QDIV_RATIO_SHIFT;
|
||||
else
|
||||
p1 = 1;
|
||||
|
||||
switch (p0) {
|
||||
case DPLL_CFGCR1_PDIV_2:
|
||||
p0 = 2;
|
||||
break;
|
||||
case DPLL_CFGCR1_PDIV_3:
|
||||
p0 = 3;
|
||||
break;
|
||||
case DPLL_CFGCR1_PDIV_5:
|
||||
p0 = 5;
|
||||
break;
|
||||
case DPLL_CFGCR1_PDIV_7:
|
||||
p0 = 7;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (p2) {
|
||||
case DPLL_CFGCR1_KDIV_1:
|
||||
p2 = 1;
|
||||
break;
|
||||
case DPLL_CFGCR1_KDIV_2:
|
||||
p2 = 2;
|
||||
break;
|
||||
case DPLL_CFGCR1_KDIV_3:
|
||||
p2 = 3;
|
||||
break;
|
||||
}
|
||||
|
||||
dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
|
||||
ref_clock;
|
||||
|
||||
dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
|
||||
DPLL_CFGCR0_DCO_FRACTION_SHIFT;
|
||||
|
||||
if (ehl_combo_pll_div_frac_wa_needed(i915))
|
||||
dco_fraction *= 2;
|
||||
|
||||
dco_freq += (dco_fraction * ref_clock) / 0x8000;
|
||||
|
||||
if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
|
||||
return 0;
|
||||
|
||||
return dco_freq / (p0 * p1 * p2 * 5);
|
||||
}
|
||||
|
||||
static void icl_calc_dpll_state(struct drm_i915_private *i915,
|
||||
|
|
@ -4131,6 +3735,31 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv,
|
|||
drm_err(&dev_priv->drm, "PLL %d not locked\n", pll->info->id);
|
||||
}
|
||||
|
||||
static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct intel_shared_dpll *pll)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
if (!IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
|
||||
pll->info->id != DPLL_ID_ICL_DPLL0)
|
||||
return;
|
||||
/*
|
||||
* Wa_16011069516:adl-p[a0]
|
||||
*
|
||||
* All CMTG regs are unreliable until CMTG clock gating is disabled,
|
||||
* so we can only assume the default TRANS_CMTG_CHICKEN reg value and
|
||||
* sanity check this assumption with a double read, which presumably
|
||||
* returns the correct value even with clock gating on.
|
||||
*
|
||||
* Instead of the usual place for workarounds we apply this one here,
|
||||
* since TRANS_CMTG_CHICKEN is only accessible while DPLL0 is enabled.
|
||||
*/
|
||||
val = intel_de_read(i915, TRANS_CMTG_CHICKEN);
|
||||
val = intel_de_read(i915, TRANS_CMTG_CHICKEN);
|
||||
intel_de_write(i915, TRANS_CMTG_CHICKEN, DISABLE_DPT_CLK_GATING);
|
||||
if (drm_WARN_ON(&i915->drm, val & ~DISABLE_DPT_CLK_GATING))
|
||||
drm_dbg_kms(&i915->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val);
|
||||
}
|
||||
|
||||
static void combo_pll_enable(struct drm_i915_private *dev_priv,
|
||||
struct intel_shared_dpll *pll)
|
||||
{
|
||||
|
|
@ -4160,6 +3789,8 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv,
|
|||
|
||||
icl_pll_enable(dev_priv, pll, enable_reg);
|
||||
|
||||
adlp_cmtg_clock_gating_wa(dev_priv, pll);
|
||||
|
||||
/* DVFS post sequence would be here. See the comment above. */
|
||||
}
|
||||
|
||||
|
|
@ -4462,7 +4093,10 @@ void intel_shared_dpll_init(struct drm_device *dev)
|
|||
const struct dpll_info *dpll_info;
|
||||
int i;
|
||||
|
||||
if (IS_ALDERLAKE_P(dev_priv))
|
||||
if (IS_DG2(dev_priv))
|
||||
/* No shared DPLLs on DG2; port PLLs are part of the PHY */
|
||||
dpll_mgr = NULL;
|
||||
else if (IS_ALDERLAKE_P(dev_priv))
|
||||
dpll_mgr = &adlp_pll_mgr;
|
||||
else if (IS_ALDERLAKE_S(dev_priv))
|
||||
dpll_mgr = &adls_pll_mgr;
|
||||
|
|
@ -4476,8 +4110,6 @@ void intel_shared_dpll_init(struct drm_device *dev)
|
|||
dpll_mgr = &ehl_pll_mgr;
|
||||
else if (DISPLAY_VER(dev_priv) >= 11)
|
||||
dpll_mgr = &icl_pll_mgr;
|
||||
else if (IS_CANNONLAKE(dev_priv))
|
||||
dpll_mgr = &cnl_pll_mgr;
|
||||
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
|
||||
dpll_mgr = &bxt_pll_mgr;
|
||||
else if (DISPLAY_VER(dev_priv) == 9)
|
||||
|
|
@ -4668,7 +4300,12 @@ void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
|
|||
static void sanitize_dpll_state(struct drm_i915_private *i915,
|
||||
struct intel_shared_dpll *pll)
|
||||
{
|
||||
if (!pll->on || pll->active_mask)
|
||||
if (!pll->on)
|
||||
return;
|
||||
|
||||
adlp_cmtg_clock_gating_wa(i915, pll);
|
||||
|
||||
if (pll->active_mask)
|
||||
return;
|
||||
|
||||
drm_dbg_kms(&i915->drm,
|
||||
|
|
|
|||
|
|
@ -204,9 +204,8 @@ struct intel_dpll_hw_state {
|
|||
/* HDMI only, 0 when used for DP */
|
||||
u32 cfgcr1, cfgcr2;
|
||||
|
||||
/* cnl */
|
||||
/* icl */
|
||||
u32 cfgcr0;
|
||||
/* CNL also uses cfgcr1 */
|
||||
|
||||
/* bxt */
|
||||
u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;
|
||||
|
|
|
|||
|
|
@ -912,11 +912,11 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
|
|||
}
|
||||
|
||||
/*
|
||||
* Tigerlake is not supporting FBC with PSR2.
|
||||
* Display 12+ is not supporting FBC with PSR2.
|
||||
* Recommendation is to keep this combination disabled
|
||||
* Bspec: 50422 HSD: 14010260002
|
||||
*/
|
||||
if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) {
|
||||
if (fbc->state_cache.psr2_active && DISPLAY_VER(dev_priv) >= 12) {
|
||||
fbc->no_fbc_reason = "not supported with PSR2";
|
||||
return false;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -600,7 +600,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
|
|||
int i = 0, inc, try = 0;
|
||||
int ret = 0;
|
||||
|
||||
/* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
|
||||
/* Display WA #0868: skl,bxt,kbl,cfl,glk */
|
||||
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
|
||||
bxt_gmbus_clock_gating(dev_priv, false);
|
||||
else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
|
||||
|
|
@ -713,7 +713,7 @@ timeout:
|
|||
ret = -EAGAIN;
|
||||
|
||||
out:
|
||||
/* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
|
||||
/* Display WA #0868: skl,bxt,kbl,cfl,glk */
|
||||
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
|
||||
bxt_gmbus_clock_gating(dev_priv, true);
|
||||
else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@
|
|||
#include "intel_hdmi.h"
|
||||
#include "intel_lspcon.h"
|
||||
#include "intel_panel.h"
|
||||
#include "intel_snps_phy.h"
|
||||
|
||||
static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
|
||||
{
|
||||
|
|
@ -1850,6 +1851,16 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
|
|||
if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
|
||||
return MODE_CLOCK_RANGE;
|
||||
|
||||
/*
|
||||
* SNPS PHYs' MPLLB table-based programming can only handle a fixed
|
||||
* set of link rates.
|
||||
*
|
||||
* FIXME: We will hopefully get an algorithmic way of programming
|
||||
* the MPLLB for HDMI in the future.
|
||||
*/
|
||||
if (IS_DG2(dev_priv))
|
||||
return intel_snps_phy_check_hdmi_link_rate(clock);
|
||||
|
||||
return MODE_OK;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1078,6 +1078,9 @@ void intel_opregion_resume(struct drm_i915_private *i915)
|
|||
opregion->asle->ardy = ASLE_ARDY_READY;
|
||||
}
|
||||
|
||||
/* Some platforms abuse the _DSM to enable MUX */
|
||||
intel_dsm_get_bios_data_funcs_supported(i915);
|
||||
|
||||
intel_opregion_notify_adapter(i915, PCI_D0);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
#include "intel_dp_aux.h"
|
||||
#include "intel_hdmi.h"
|
||||
#include "intel_psr.h"
|
||||
#include "intel_snps_phy.h"
|
||||
#include "intel_sprite.h"
|
||||
#include "skl_universal_plane.h"
|
||||
|
||||
|
|
@ -534,19 +535,21 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
|
|||
static void hsw_activate_psr2(struct intel_dp *intel_dp)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
||||
u32 val;
|
||||
u32 val = EDP_PSR2_ENABLE;
|
||||
|
||||
val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
|
||||
val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
|
||||
|
||||
if (!IS_ALDERLAKE_P(dev_priv))
|
||||
val |= EDP_SU_TRACK_ENABLE;
|
||||
|
||||
val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
|
||||
if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
|
||||
val |= EDP_Y_COORDINATE_ENABLE;
|
||||
|
||||
val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1);
|
||||
val |= intel_psr2_get_tp_time(intel_dp);
|
||||
|
||||
/* Wa_22012278275:adlp */
|
||||
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D1)) {
|
||||
/* Wa_22012278275:adl-p */
|
||||
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
|
||||
static const u8 map[] = {
|
||||
2, /* 5 lines */
|
||||
1, /* 6 lines */
|
||||
|
|
@ -592,9 +595,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
|
|||
val |= EDP_PSR2_SU_SDP_SCANLINE;
|
||||
|
||||
if (intel_dp->psr.psr2_sel_fetch_enabled) {
|
||||
/* WA 1408330847 */
|
||||
if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
|
||||
IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
|
||||
/* Wa_1408330847 */
|
||||
if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
|
||||
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
|
||||
DIS_RAM_BYPASS_PSR2_MAN_TRACK,
|
||||
DIS_RAM_BYPASS_PSR2_MAN_TRACK);
|
||||
|
|
@ -733,8 +735,8 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
|
|||
if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
|
||||
return;
|
||||
|
||||
/* Wa_16011303918:adlp */
|
||||
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
|
||||
/* Wa_16011303918:adl-p */
|
||||
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
|
||||
return;
|
||||
|
||||
/*
|
||||
|
|
@ -781,7 +783,7 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
|
|||
}
|
||||
|
||||
/* Wa_14010254185 Wa_14010103792 */
|
||||
if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) {
|
||||
if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"PSR2 sel fetch not enabled, missing the implementation of WAs\n");
|
||||
return false;
|
||||
|
|
@ -793,6 +795,7 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
|
|||
static bool psr2_granularity_check(struct intel_dp *intel_dp,
|
||||
struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
||||
const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
|
||||
const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
|
||||
u16 y_granularity = 0;
|
||||
|
|
@ -809,10 +812,13 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,
|
|||
return intel_dp->psr.su_y_granularity == 4;
|
||||
|
||||
/*
|
||||
* For SW tracking we can adjust the y to match sink requirement if
|
||||
* multiple of 4
|
||||
* adl_p has 1 line granularity. For other platforms with SW tracking we
|
||||
* can adjust the y coordinates to match sink requirement if multiple of
|
||||
* 4.
|
||||
*/
|
||||
if (intel_dp->psr.su_y_granularity <= 2)
|
||||
if (IS_ALDERLAKE_P(dev_priv))
|
||||
y_granularity = intel_dp->psr.su_y_granularity;
|
||||
else if (intel_dp->psr.su_y_granularity <= 2)
|
||||
y_granularity = 4;
|
||||
else if ((intel_dp->psr.su_y_granularity % 4) == 0)
|
||||
y_granularity = intel_dp->psr.su_y_granularity;
|
||||
|
|
@ -865,7 +871,8 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
|
|||
}
|
||||
|
||||
/* Wa_16011181250 */
|
||||
if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv)) {
|
||||
if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
|
||||
IS_DG2(dev_priv)) {
|
||||
drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this platform\n");
|
||||
return false;
|
||||
}
|
||||
|
|
@ -940,7 +947,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
|
|||
|
||||
/* Wa_2209313811 */
|
||||
if (!crtc_state->enable_psr2_sel_fetch &&
|
||||
IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) {
|
||||
IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
|
||||
drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n");
|
||||
return false;
|
||||
}
|
||||
|
|
@ -965,9 +972,9 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
|
|||
return false;
|
||||
}
|
||||
|
||||
/* Wa_16011303918:adlp */
|
||||
/* Wa_16011303918:adl-p */
|
||||
if (crtc_state->vrr.enable &&
|
||||
IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) {
|
||||
IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"PSR2 not enabled, not compatible with HW stepping + VRR\n");
|
||||
return false;
|
||||
|
|
@ -1160,8 +1167,8 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
|
|||
intel_dp->psr.psr2_sel_fetch_enabled ?
|
||||
IGNORE_PSR2_HW_TRACKING : 0);
|
||||
|
||||
/* Wa_16011168373:adlp */
|
||||
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) &&
|
||||
/* Wa_16011168373:adl-p */
|
||||
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
|
||||
intel_dp->psr.psr2_enabled)
|
||||
intel_de_rmw(dev_priv,
|
||||
TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
|
||||
|
|
@ -1206,6 +1213,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
|
|||
{
|
||||
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
||||
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
||||
enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
|
||||
struct intel_encoder *encoder = &dig_port->base;
|
||||
u32 val;
|
||||
|
||||
|
|
@ -1231,6 +1239,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
|
|||
intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
|
||||
&intel_dp->psr.vsc);
|
||||
intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp->psr.vsc);
|
||||
intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
|
||||
intel_psr_enable_sink(intel_dp);
|
||||
intel_psr_enable_source(intel_dp);
|
||||
intel_dp->psr.enabled = true;
|
||||
|
|
@ -1327,6 +1336,8 @@ static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
|
|||
static void intel_psr_disable_locked(struct intel_dp *intel_dp)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
||||
enum phy phy = intel_port_to_phy(dev_priv,
|
||||
dp_to_dig_port(intel_dp)->base.port);
|
||||
|
||||
lockdep_assert_held(&intel_dp->psr.lock);
|
||||
|
||||
|
|
@ -1339,20 +1350,21 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
|
|||
intel_psr_exit(intel_dp);
|
||||
intel_psr_wait_exit_locked(intel_dp);
|
||||
|
||||
/* WA 1408330847 */
|
||||
/* Wa_1408330847 */
|
||||
if (intel_dp->psr.psr2_sel_fetch_enabled &&
|
||||
(IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
|
||||
IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)))
|
||||
IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
|
||||
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
|
||||
DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
|
||||
|
||||
/* Wa_16011168373:adlp */
|
||||
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) &&
|
||||
/* Wa_16011168373:adl-p */
|
||||
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
|
||||
intel_dp->psr.psr2_enabled)
|
||||
intel_de_rmw(dev_priv,
|
||||
TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
|
||||
TRANS_SET_CONTEXT_LATENCY_MASK, 0);
|
||||
|
||||
intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
|
||||
|
||||
/* Disable PSR on Sink */
|
||||
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
|
||||
|
||||
|
|
@ -1525,21 +1537,32 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
|
|||
static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
|
||||
struct drm_rect *clip, bool full_update)
|
||||
{
|
||||
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
u32 val = PSR2_MAN_TRK_CTL_ENABLE;
|
||||
|
||||
if (full_update) {
|
||||
val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
|
||||
if (IS_ALDERLAKE_P(dev_priv))
|
||||
val |= ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
|
||||
else
|
||||
val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
|
||||
|
||||
goto exit;
|
||||
}
|
||||
|
||||
if (clip->y1 == -1)
|
||||
goto exit;
|
||||
|
||||
drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
|
||||
if (IS_ALDERLAKE_P(dev_priv)) {
|
||||
val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
|
||||
val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2);
|
||||
} else {
|
||||
drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
|
||||
|
||||
val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
|
||||
val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
|
||||
val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
|
||||
val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
|
||||
val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
|
||||
val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
|
||||
}
|
||||
exit:
|
||||
crtc_state->psr2_man_track_ctl = val;
|
||||
}
|
||||
|
|
@ -1563,11 +1586,15 @@ static void clip_area_update(struct drm_rect *overlap_damage_area,
|
|||
static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state,
|
||||
struct drm_rect *pipe_clip)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
|
||||
const u16 y_alignment = crtc_state->su_y_granularity;
|
||||
|
||||
pipe_clip->y1 -= pipe_clip->y1 % y_alignment;
|
||||
if (pipe_clip->y2 % y_alignment)
|
||||
pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment;
|
||||
|
||||
if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable)
|
||||
drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n");
|
||||
}
|
||||
|
||||
int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
|
||||
|
|
@ -1699,6 +1726,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
|
|||
sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
|
||||
sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1;
|
||||
sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1;
|
||||
crtc_state->update_planes |= BIT(plane->id);
|
||||
}
|
||||
|
||||
skip_sel_fetch_set_loop:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,862 @@
|
|||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
* Copyright © 2019 Intel Corporation
|
||||
*/
|
||||
|
||||
#include <linux/util_macros.h>
|
||||
|
||||
#include "intel_de.h"
|
||||
#include "intel_display_types.h"
|
||||
#include "intel_snps_phy.h"
|
||||
|
||||
/**
|
||||
* DOC: Synopsis PHY support
|
||||
*
|
||||
* Synopsis PHYs are primarily programmed by looking up magic register values
|
||||
* in tables rather than calculating the necessary values at runtime.
|
||||
*
|
||||
* Of special note is that the SNPS PHYs include a dedicated port PLL, known as
|
||||
* an "MPLLB." The MPLLB replaces the shared DPLL functionality used on other
|
||||
* platforms and must be programming directly during the modeset sequence
|
||||
* since it is not handled by the shared DPLL framework as on other platforms.
|
||||
*/
|
||||
|
||||
void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
enum phy phy;
|
||||
|
||||
for_each_phy_masked(phy, ~0) {
|
||||
if (!intel_phy_is_snps(dev_priv, phy))
|
||||
continue;
|
||||
|
||||
if (intel_de_wait_for_clear(dev_priv, ICL_PHY_MISC(phy),
|
||||
DG2_PHY_DP_TX_ACK_MASK, 25))
|
||||
DRM_ERROR("SNPS PHY %c failed to calibrate after 25ms.\n",
|
||||
phy);
|
||||
}
|
||||
}
|
||||
|
||||
void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv,
|
||||
enum phy phy, bool enable)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
if (!intel_phy_is_snps(dev_priv, phy))
|
||||
return;
|
||||
|
||||
val = REG_FIELD_PREP(SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR,
|
||||
enable ? 2 : 3);
|
||||
intel_uncore_rmw(&dev_priv->uncore, SNPS_PHY_TX_REQ(phy),
|
||||
SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val);
|
||||
}
|
||||
|
||||
static const u32 dg2_ddi_translations[] = {
|
||||
/* VS 0, pre-emph 0 */
|
||||
REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 26),
|
||||
|
||||
/* VS 0, pre-emph 1 */
|
||||
REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 33) |
|
||||
REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 6),
|
||||
|
||||
/* VS 0, pre-emph 2 */
|
||||
REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 38) |
|
||||
REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 12),
|
||||
|
||||
/* VS 0, pre-emph 3 */
|
||||
REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 43) |
|
||||
REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 19),
|
||||
|
||||
/* VS 1, pre-emph 0 */
|
||||
REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 39),
|
||||
|
||||
/* VS 1, pre-emph 1 */
|
||||
REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 44) |
|
||||
REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 8),
|
||||
|
||||
/* VS 1, pre-emph 2 */
|
||||
REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 47) |
|
||||
REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 15),
|
||||
|
||||
/* VS 2, pre-emph 0 */
|
||||
REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 52),
|
||||
|
||||
/* VS 2, pre-emph 1 */
|
||||
REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 51) |
|
||||
REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 10),
|
||||
|
||||
/* VS 3, pre-emph 0 */
|
||||
REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 62),
|
||||
};
|
||||
|
||||
void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
|
||||
u32 level)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
|
||||
int n_entries, ln;
|
||||
|
||||
n_entries = ARRAY_SIZE(dg2_ddi_translations);
|
||||
if (level >= n_entries)
|
||||
level = n_entries - 1;
|
||||
|
||||
for (ln = 0; ln < 4; ln++)
|
||||
intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy),
|
||||
dg2_ddi_translations[level]);
|
||||
}
|
||||
|
||||
/*
|
||||
* Basic DP link rates with 100 MHz reference clock.
|
||||
*/
|
||||
|
||||
static const struct intel_mpllb_state dg2_dp_rbr_100 = {
|
||||
.clock = 162000,
|
||||
.ref_control =
|
||||
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
||||
.mpllb_cp =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
|
||||
.mpllb_div =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
|
||||
.mpllb_div2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226),
|
||||
.mpllb_fracn1 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
|
||||
.mpllb_fracn2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3),
|
||||
};
|
||||
|
||||
static const struct intel_mpllb_state dg2_dp_hbr1_100 = {
|
||||
.clock = 270000,
|
||||
.ref_control =
|
||||
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
||||
.mpllb_cp =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
|
||||
.mpllb_div =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
||||
.mpllb_div2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184),
|
||||
.mpllb_fracn1 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
|
||||
};
|
||||
|
||||
static const struct intel_mpllb_state dg2_dp_hbr2_100 = {
|
||||
.clock = 540000,
|
||||
.ref_control =
|
||||
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
||||
.mpllb_cp =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
|
||||
.mpllb_div =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
||||
.mpllb_div2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184),
|
||||
.mpllb_fracn1 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
|
||||
};
|
||||
|
||||
static const struct intel_mpllb_state dg2_dp_hbr3_100 = {
|
||||
.clock = 810000,
|
||||
.ref_control =
|
||||
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
||||
.mpllb_cp =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
|
||||
.mpllb_div =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
|
||||
.mpllb_div2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 292),
|
||||
.mpllb_fracn1 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
|
||||
};
|
||||
|
||||
static const struct intel_mpllb_state *dg2_dp_100_tables[] = {
|
||||
&dg2_dp_rbr_100,
|
||||
&dg2_dp_hbr1_100,
|
||||
&dg2_dp_hbr2_100,
|
||||
&dg2_dp_hbr3_100,
|
||||
NULL,
|
||||
};
|
||||
|
||||
/*
|
||||
* Basic DP link rates with 38.4 MHz reference clock.
|
||||
*/
|
||||
|
||||
static const struct intel_mpllb_state dg2_dp_rbr_38_4 = {
|
||||
.clock = 162000,
|
||||
.ref_control =
|
||||
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
|
||||
.mpllb_cp =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
|
||||
.mpllb_div =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
|
||||
.mpllb_div2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 304),
|
||||
.mpllb_fracn1 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
|
||||
.mpllb_fracn2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 49152),
|
||||
};
|
||||
|
||||
static const struct intel_mpllb_state dg2_dp_hbr1_38_4 = {
|
||||
.clock = 270000,
|
||||
.ref_control =
|
||||
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
|
||||
.mpllb_cp =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
|
||||
.mpllb_div =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
||||
.mpllb_div2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248),
|
||||
.mpllb_fracn1 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
|
||||
.mpllb_fracn2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960),
|
||||
};
|
||||
|
||||
static const struct intel_mpllb_state dg2_dp_hbr2_38_4 = {
|
||||
.clock = 540000,
|
||||
.ref_control =
|
||||
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
|
||||
.mpllb_cp =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
|
||||
.mpllb_div =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
||||
.mpllb_div2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248),
|
||||
.mpllb_fracn1 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
|
||||
.mpllb_fracn2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960),
|
||||
};
|
||||
|
||||
static const struct intel_mpllb_state dg2_dp_hbr3_38_4 = {
|
||||
.clock = 810000,
|
||||
.ref_control =
|
||||
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
|
||||
.mpllb_cp =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
|
||||
.mpllb_div =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
|
||||
.mpllb_div2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 388),
|
||||
.mpllb_fracn1 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
|
||||
.mpllb_fracn2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 61440),
|
||||
};
|
||||
|
||||
static const struct intel_mpllb_state *dg2_dp_38_4_tables[] = {
|
||||
&dg2_dp_rbr_38_4,
|
||||
&dg2_dp_hbr1_38_4,
|
||||
&dg2_dp_hbr2_38_4,
|
||||
&dg2_dp_hbr3_38_4,
|
||||
NULL,
|
||||
};
|
||||
|
||||
/*
|
||||
* eDP link rates with 100 MHz reference clock.
|
||||
*/
|
||||
|
||||
static const struct intel_mpllb_state dg2_edp_r216 = {
|
||||
.clock = 216000,
|
||||
.ref_control =
|
||||
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
||||
.mpllb_cp =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
|
||||
.mpllb_div =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
|
||||
.mpllb_div2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312),
|
||||
.mpllb_fracn1 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
|
||||
.mpllb_fracn2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4),
|
||||
.mpllb_sscen =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961),
|
||||
.mpllb_sscstep =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752),
|
||||
};
|
||||
|
||||
static const struct intel_mpllb_state dg2_edp_r243 = {
|
||||
.clock = 243000,
|
||||
.ref_control =
|
||||
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
||||
.mpllb_cp =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
|
||||
.mpllb_div =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
|
||||
.mpllb_div2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 356),
|
||||
.mpllb_fracn1 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
|
||||
.mpllb_fracn2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
|
||||
.mpllb_sscen =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 57331),
|
||||
.mpllb_sscstep =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 73971),
|
||||
};
|
||||
|
||||
static const struct intel_mpllb_state dg2_edp_r324 = {
|
||||
.clock = 324000,
|
||||
.ref_control =
|
||||
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
||||
.mpllb_cp =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
|
||||
.mpllb_div =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
|
||||
.mpllb_div2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226),
|
||||
.mpllb_fracn1 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
|
||||
.mpllb_fracn2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3),
|
||||
.mpllb_sscen =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 38221),
|
||||
.mpllb_sscstep =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 49314),
|
||||
};
|
||||
|
||||
static const struct intel_mpllb_state dg2_edp_r432 = {
|
||||
.clock = 432000,
|
||||
.ref_control =
|
||||
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
||||
.mpllb_cp =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
|
||||
.mpllb_div =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
|
||||
.mpllb_div2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312),
|
||||
.mpllb_fracn1 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
|
||||
.mpllb_fracn2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4),
|
||||
.mpllb_sscen =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961),
|
||||
.mpllb_sscstep =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752),
|
||||
};
|
||||
|
||||
static const struct intel_mpllb_state *dg2_edp_tables[] = {
|
||||
&dg2_dp_rbr_100,
|
||||
&dg2_edp_r216,
|
||||
&dg2_edp_r243,
|
||||
&dg2_dp_hbr1_100,
|
||||
&dg2_edp_r324,
|
||||
&dg2_edp_r432,
|
||||
&dg2_dp_hbr2_100,
|
||||
&dg2_dp_hbr3_100,
|
||||
NULL,
|
||||
};
|
||||
|
||||
/*
|
||||
* HDMI link rates with 100 MHz reference clock.
|
||||
*/
|
||||
|
||||
static const struct intel_mpllb_state dg2_hdmi_25_175 = {
|
||||
.clock = 25175,
|
||||
.ref_control =
|
||||
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
||||
.mpllb_cp =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
||||
.mpllb_div =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
|
||||
.mpllb_div2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
||||
.mpllb_fracn1 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 143),
|
||||
.mpllb_fracn2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36663) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 71),
|
||||
.mpllb_sscen =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
||||
};
|
||||
|
||||
static const struct intel_mpllb_state dg2_hdmi_27_0 = {
|
||||
.clock = 27000,
|
||||
.ref_control =
|
||||
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
||||
.mpllb_cp =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
||||
.mpllb_div =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
|
||||
.mpllb_div2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
||||
.mpllb_fracn1 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
|
||||
.mpllb_fracn2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
|
||||
.mpllb_sscen =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
||||
};
|
||||
|
||||
static const struct intel_mpllb_state dg2_hdmi_74_25 = {
|
||||
.clock = 74250,
|
||||
.ref_control =
|
||||
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
||||
.mpllb_cp =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
||||
.mpllb_div =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
||||
.mpllb_div2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
||||
.mpllb_fracn1 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
|
||||
.mpllb_fracn2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
|
||||
.mpllb_sscen =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
||||
};
|
||||
|
||||
static const struct intel_mpllb_state dg2_hdmi_148_5 = {
|
||||
.clock = 148500,
|
||||
.ref_control =
|
||||
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
||||
.mpllb_cp =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
||||
.mpllb_div =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
||||
.mpllb_div2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
||||
.mpllb_fracn1 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
|
||||
.mpllb_fracn2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
|
||||
.mpllb_sscen =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
||||
};
|
||||
|
||||
static const struct intel_mpllb_state dg2_hdmi_594 = {
|
||||
.clock = 594000,
|
||||
.ref_control =
|
||||
REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
|
||||
.mpllb_cp =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
|
||||
.mpllb_div =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
|
||||
.mpllb_div2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
|
||||
.mpllb_fracn1 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
|
||||
.mpllb_fracn2 =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
|
||||
.mpllb_sscen =
|
||||
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
|
||||
};
|
||||
|
||||
static const struct intel_mpllb_state *dg2_hdmi_tables[] = {
|
||||
&dg2_hdmi_25_175,
|
||||
&dg2_hdmi_27_0,
|
||||
&dg2_hdmi_74_25,
|
||||
&dg2_hdmi_148_5,
|
||||
&dg2_hdmi_594,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static const struct intel_mpllb_state **
|
||||
intel_mpllb_tables_get(struct intel_crtc_state *crtc_state,
|
||||
struct intel_encoder *encoder)
|
||||
{
|
||||
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
|
||||
return dg2_edp_tables;
|
||||
} else if (intel_crtc_has_dp_encoder(crtc_state)) {
|
||||
/*
|
||||
* FIXME: Initially we're just enabling the "combo" outputs on
|
||||
* port A-D. The MPLLB for those ports takes an input from the
|
||||
* "Display Filter PLL" which always has an output frequency
|
||||
* of 100 MHz, hence the use of the _100 tables below.
|
||||
*
|
||||
* Once we enable port TC1 it will either use the same 100 MHz
|
||||
* "Display Filter PLL" (when strapped to support a native
|
||||
* display connection) or different 38.4 MHz "Filter PLL" when
|
||||
* strapped to support a USB connection, so we'll need to check
|
||||
* that to determine which table to use.
|
||||
*/
|
||||
if (0)
|
||||
return dg2_dp_38_4_tables;
|
||||
else
|
||||
return dg2_dp_100_tables;
|
||||
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
|
||||
return dg2_hdmi_tables;
|
||||
}
|
||||
|
||||
MISSING_CASE(encoder->type);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
|
||||
struct intel_encoder *encoder)
|
||||
{
|
||||
const struct intel_mpllb_state **tables;
|
||||
int i;
|
||||
|
||||
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
|
||||
if (intel_snps_phy_check_hdmi_link_rate(crtc_state->port_clock)
|
||||
!= MODE_OK) {
|
||||
/*
|
||||
* FIXME: Can only support fixed HDMI frequencies
|
||||
* until we have a proper algorithm under a valid
|
||||
* license.
|
||||
*/
|
||||
DRM_DEBUG_KMS("Can't support HDMI link rate %d\n",
|
||||
crtc_state->port_clock);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
tables = intel_mpllb_tables_get(crtc_state, encoder);
|
||||
if (!tables)
|
||||
return -EINVAL;
|
||||
|
||||
for (i = 0; tables[i]; i++) {
|
||||
if (crtc_state->port_clock <= tables[i]->clock) {
|
||||
crtc_state->mpllb_state = *tables[i];
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
void intel_mpllb_enable(struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
const struct intel_mpllb_state *pll_state = &crtc_state->mpllb_state;
|
||||
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
|
||||
i915_reg_t enable_reg = (phy <= PHY_D ?
|
||||
DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
|
||||
|
||||
/*
|
||||
* 3. Software programs the following PLL registers for the desired
|
||||
* frequency.
|
||||
*/
|
||||
intel_de_write(dev_priv, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp);
|
||||
intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div);
|
||||
intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2);
|
||||
intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen);
|
||||
intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep);
|
||||
intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1);
|
||||
intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2);
|
||||
|
||||
/*
|
||||
* 4. If the frequency will result in a change to the voltage
|
||||
* requirement, follow the Display Voltage Frequency Switching -
|
||||
* Sequence Before Frequency Change.
|
||||
*
|
||||
* We handle this step in bxt_set_cdclk().
|
||||
*/
|
||||
|
||||
/* 5. Software sets DPLL_ENABLE [PLL Enable] to "1". */
|
||||
intel_uncore_rmw(&dev_priv->uncore, enable_reg, 0, PLL_ENABLE);
|
||||
|
||||
/*
|
||||
* 9. Software sets SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "1". This
|
||||
* will keep the PLL running during the DDI lane programming and any
|
||||
* typeC DP cable disconnect. Do not set the force before enabling the
|
||||
* PLL because that will start the PLL before it has sampled the
|
||||
* divider values.
|
||||
*/
|
||||
intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy),
|
||||
pll_state->mpllb_div | SNPS_PHY_MPLLB_FORCE_EN);
|
||||
|
||||
/*
|
||||
* 10. Software polls on register DPLL_ENABLE [PLL Lock] to confirm PLL
|
||||
* is locked at new settings. This register bit is sampling PHY
|
||||
* dp_mpllb_state interface signal.
|
||||
*/
|
||||
if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 5))
|
||||
DRM_ERROR("Port %c PLL not locked\n", phy_name(phy));
|
||||
|
||||
/*
|
||||
* 11. If the frequency will result in a change to the voltage
|
||||
* requirement, follow the Display Voltage Frequency Switching -
|
||||
* Sequence After Frequency Change.
|
||||
*
|
||||
* We handle this step in bxt_set_cdclk().
|
||||
*/
|
||||
}
|
||||
|
||||
void intel_mpllb_disable(struct intel_encoder *encoder)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
|
||||
i915_reg_t enable_reg = (phy <= PHY_D ?
|
||||
DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
|
||||
|
||||
/*
|
||||
* 1. If the frequency will result in a change to the voltage
|
||||
* requirement, follow the Display Voltage Frequency Switching -
|
||||
* Sequence Before Frequency Change.
|
||||
*
|
||||
* We handle this step in bxt_set_cdclk().
|
||||
*/
|
||||
|
||||
/* 2. Software programs DPLL_ENABLE [PLL Enable] to "0" */
|
||||
intel_uncore_rmw(&dev_priv->uncore, enable_reg, PLL_ENABLE, 0);
|
||||
|
||||
/*
|
||||
* 4. Software programs SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "0".
|
||||
* This will allow the PLL to stop running.
|
||||
*/
|
||||
intel_uncore_rmw(&dev_priv->uncore, SNPS_PHY_MPLLB_DIV(phy),
|
||||
SNPS_PHY_MPLLB_FORCE_EN, 0);
|
||||
|
||||
/*
|
||||
* 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment
|
||||
* (dp_txX_ack) that the new transmitter setting request is completed.
|
||||
*/
|
||||
if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_LOCK, 5))
|
||||
DRM_ERROR("Port %c PLL not locked\n", phy_name(phy));
|
||||
|
||||
/*
|
||||
* 6. If the frequency will result in a change to the voltage
|
||||
* requirement, follow the Display Voltage Frequency Switching -
|
||||
* Sequence After Frequency Change.
|
||||
*
|
||||
* We handle this step in bxt_set_cdclk().
|
||||
*/
|
||||
}
|
||||
|
||||
int intel_mpllb_calc_port_clock(struct intel_encoder *encoder,
|
||||
const struct intel_mpllb_state *pll_state)
|
||||
{
|
||||
unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
|
||||
unsigned int multiplier, tx_clk_div, refclk;
|
||||
bool frac_en;
|
||||
|
||||
if (0)
|
||||
refclk = 38400;
|
||||
else
|
||||
refclk = 100000;
|
||||
|
||||
refclk >>= REG_FIELD_GET(SNPS_PHY_MPLLB_REF_CLK_DIV, pll_state->mpllb_div2) - 1;
|
||||
|
||||
frac_en = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_EN, pll_state->mpllb_fracn1);
|
||||
|
||||
if (frac_en) {
|
||||
frac_quot = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_QUOT, pll_state->mpllb_fracn2);
|
||||
frac_rem = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_REM, pll_state->mpllb_fracn2);
|
||||
frac_den = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_DEN, pll_state->mpllb_fracn1);
|
||||
}
|
||||
|
||||
multiplier = REG_FIELD_GET(SNPS_PHY_MPLLB_MULTIPLIER, pll_state->mpllb_div2) / 2 + 16;
|
||||
|
||||
tx_clk_div = REG_FIELD_GET(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_state->mpllb_div);
|
||||
|
||||
return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
|
||||
DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
|
||||
10 << (tx_clk_div + 16));
|
||||
}
|
||||
|
||||
void intel_mpllb_readout_hw_state(struct intel_encoder *encoder,
|
||||
struct intel_mpllb_state *pll_state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
|
||||
|
||||
pll_state->mpllb_cp = intel_de_read(dev_priv, SNPS_PHY_MPLLB_CP(phy));
|
||||
pll_state->mpllb_div = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV(phy));
|
||||
pll_state->mpllb_div2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV2(phy));
|
||||
pll_state->mpllb_sscen = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy));
|
||||
pll_state->mpllb_sscstep = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy));
|
||||
pll_state->mpllb_fracn1 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy));
|
||||
pll_state->mpllb_fracn2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy));
|
||||
|
||||
/*
|
||||
* REF_CONTROL is under firmware control and never programmed by the
|
||||
* driver; we read it only for sanity checking purposes. The bspec
|
||||
* only tells us the expected value for one field in this register,
|
||||
* so we'll only read out those specific bits here.
|
||||
*/
|
||||
pll_state->ref_control = intel_de_read(dev_priv, SNPS_PHY_REF_CONTROL(phy)) &
|
||||
SNPS_PHY_REF_CONTROL_REF_RANGE;
|
||||
|
||||
/*
|
||||
* MPLLB_DIV is programmed twice, once with the software-computed
|
||||
* state, then again with the MPLLB_FORCE_EN bit added. Drop that
|
||||
* extra bit during readout so that we return the actual expected
|
||||
* software state.
|
||||
*/
|
||||
pll_state->mpllb_div &= ~SNPS_PHY_MPLLB_FORCE_EN;
|
||||
}
|
||||
|
||||
int intel_snps_phy_check_hdmi_link_rate(int clock)
|
||||
{
|
||||
const struct intel_mpllb_state **tables = dg2_hdmi_tables;
|
||||
int i;
|
||||
|
||||
for (i = 0; tables[i]; i++) {
|
||||
if (clock == tables[i]->clock)
|
||||
return MODE_OK;
|
||||
}
|
||||
|
||||
return MODE_CLOCK_RANGE;
|
||||
}
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/* SPDX-License-Identifier: MIT */
|
||||
/*
|
||||
* Copyright © 2019 Intel Corporation
|
||||
*/
|
||||
|
||||
#ifndef __INTEL_SNPS_PHY_H__
|
||||
#define __INTEL_SNPS_PHY_H__
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct drm_i915_private;
|
||||
struct intel_encoder;
|
||||
struct intel_crtc_state;
|
||||
struct intel_mpllb_state;
|
||||
enum phy;
|
||||
|
||||
void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv);
|
||||
void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv,
|
||||
enum phy phy, bool enable);
|
||||
|
||||
int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
|
||||
struct intel_encoder *encoder);
|
||||
void intel_mpllb_enable(struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *crtc_state);
|
||||
void intel_mpllb_disable(struct intel_encoder *encoder);
|
||||
void intel_mpllb_readout_hw_state(struct intel_encoder *encoder,
|
||||
struct intel_mpllb_state *pll_state);
|
||||
int intel_mpllb_calc_port_clock(struct intel_encoder *encoder,
|
||||
const struct intel_mpllb_state *pll_state);
|
||||
|
||||
int intel_snps_phy_check_hdmi_link_rate(int clock);
|
||||
void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
|
||||
u32 level);
|
||||
|
||||
#endif /* __INTEL_SNPS_PHY_H__ */
|
||||
|
|
@ -1856,7 +1856,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
|
|||
zpos = sprite + 1;
|
||||
drm_plane_create_zpos_immutable_property(&plane->base, zpos);
|
||||
|
||||
drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
|
||||
intel_plane_helper_add(plane);
|
||||
|
||||
return plane;
|
||||
|
||||
|
|
|
|||
|
|
@ -456,7 +456,7 @@ struct child_device_config {
|
|||
u16 dp_gpio_pin_num; /* 195 */
|
||||
u8 dp_iboost_level:4; /* 196 */
|
||||
u8 hdmi_iboost_level:4; /* 196 */
|
||||
u8 dp_max_link_rate:3; /* 216/230 CNL+ */
|
||||
u8 dp_max_link_rate:3; /* 216/230 GLK+ */
|
||||
u8 dp_max_link_rate_reserved:5; /* 216/230 */
|
||||
} __packed;
|
||||
|
||||
|
|
|
|||
|
|
@ -348,7 +348,10 @@ bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
|
|||
if (DISPLAY_VER(i915) >= 12)
|
||||
return true;
|
||||
|
||||
if ((DISPLAY_VER(i915) >= 11 || IS_CANNONLAKE(i915)) && (pipe != PIPE_A || (cpu_transcoder == TRANSCODER_EDP || cpu_transcoder == TRANSCODER_DSI_0 || cpu_transcoder == TRANSCODER_DSI_1)))
|
||||
if (DISPLAY_VER(i915) >= 11 &&
|
||||
(pipe != PIPE_A || cpu_transcoder == TRANSCODER_EDP ||
|
||||
cpu_transcoder == TRANSCODER_DSI_0 ||
|
||||
cpu_transcoder == TRANSCODER_DSI_1))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
|
|
|
|||
|
|
@ -294,12 +294,12 @@ int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int cnl_coef_tap(int i)
|
||||
static int glk_coef_tap(int i)
|
||||
{
|
||||
return i % 7;
|
||||
}
|
||||
|
||||
static u16 cnl_nearest_filter_coef(int t)
|
||||
static u16 glk_nearest_filter_coef(int t)
|
||||
{
|
||||
return t == 3 ? 0x0800 : 0x3000;
|
||||
}
|
||||
|
|
@ -341,29 +341,29 @@ static u16 cnl_nearest_filter_coef(int t)
|
|||
*
|
||||
*/
|
||||
|
||||
static void cnl_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
|
||||
static void glk_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
|
||||
enum pipe pipe, int id, int set)
|
||||
{
|
||||
int i;
|
||||
|
||||
intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set),
|
||||
intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set),
|
||||
PS_COEE_INDEX_AUTO_INC);
|
||||
|
||||
for (i = 0; i < 17 * 7; i += 2) {
|
||||
u32 tmp;
|
||||
int t;
|
||||
|
||||
t = cnl_coef_tap(i);
|
||||
tmp = cnl_nearest_filter_coef(t);
|
||||
t = glk_coef_tap(i);
|
||||
tmp = glk_nearest_filter_coef(t);
|
||||
|
||||
t = cnl_coef_tap(i + 1);
|
||||
tmp |= cnl_nearest_filter_coef(t) << 16;
|
||||
t = glk_coef_tap(i + 1);
|
||||
tmp |= glk_nearest_filter_coef(t) << 16;
|
||||
|
||||
intel_de_write_fw(dev_priv, CNL_PS_COEF_DATA_SET(pipe, id, set),
|
||||
intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(pipe, id, set),
|
||||
tmp);
|
||||
}
|
||||
|
||||
intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set), 0);
|
||||
intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0);
|
||||
}
|
||||
|
||||
static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set)
|
||||
|
|
@ -386,7 +386,7 @@ static void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe
|
|||
case DRM_SCALING_FILTER_DEFAULT:
|
||||
break;
|
||||
case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
|
||||
cnl_program_nearest_filter_coefs(dev_priv, pipe, id, set);
|
||||
glk_program_nearest_filter_coefs(dev_priv, pipe, id, set);
|
||||
break;
|
||||
default:
|
||||
MISSING_CASE(filter);
|
||||
|
|
|
|||
|
|
@ -835,7 +835,7 @@ static u32 skl_plane_ctl_rotate(unsigned int rotate)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static u32 cnl_plane_ctl_flip(unsigned int reflect)
|
||||
static u32 icl_plane_ctl_flip(unsigned int reflect)
|
||||
{
|
||||
switch (reflect) {
|
||||
case 0:
|
||||
|
|
@ -917,8 +917,8 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
|
|||
plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
|
||||
plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
|
||||
plane_ctl |= cnl_plane_ctl_flip(rotation &
|
||||
if (DISPLAY_VER(dev_priv) >= 11)
|
||||
plane_ctl |= icl_plane_ctl_flip(rotation &
|
||||
DRM_MODE_REFLECT_MASK);
|
||||
|
||||
if (key->flags & I915_SET_COLORKEY_DESTINATION)
|
||||
|
|
@ -926,7 +926,7 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
|
|||
else if (key->flags & I915_SET_COLORKEY_SOURCE)
|
||||
plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
|
||||
|
||||
/* Wa_22012358565:adlp */
|
||||
/* Wa_22012358565:adl-p */
|
||||
if (DISPLAY_VER(dev_priv) == 13)
|
||||
plane_ctl |= adlp_plane_ctl_arb_slots(plane_state);
|
||||
|
||||
|
|
@ -1270,7 +1270,7 @@ static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_s
|
|||
int pipe_src_w = crtc_state->pipe_src_w;
|
||||
|
||||
/*
|
||||
* Display WA #1175: cnl,glk
|
||||
* Display WA #1175: glk
|
||||
* Planes other than the cursor may cause FIFO underflow and display
|
||||
* corruption if starting less than 4 pixels from the right edge of
|
||||
* the screen.
|
||||
|
|
@ -1828,7 +1828,7 @@ static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
|
|||
if (plane_id == PLANE_CURSOR)
|
||||
return false;
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
|
||||
if (DISPLAY_VER(dev_priv) >= 11)
|
||||
return true;
|
||||
|
||||
if (IS_GEMINILAKE(dev_priv))
|
||||
|
|
@ -1910,11 +1910,11 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
|
|||
{
|
||||
/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
|
||||
if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
|
||||
IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
|
||||
IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D0))
|
||||
return false;
|
||||
|
||||
/* Wa_22011186057 */
|
||||
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
|
||||
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
|
||||
return false;
|
||||
|
||||
return plane_id < PLANE_SPRITE4;
|
||||
|
|
@ -1938,7 +1938,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
|
|||
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
|
||||
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
|
||||
/* Wa_22011186057 */
|
||||
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
|
||||
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
|
||||
return false;
|
||||
break;
|
||||
default:
|
||||
|
|
@ -1995,7 +1995,7 @@ static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv,
|
|||
enum plane_id plane_id)
|
||||
{
|
||||
/* Wa_22011186057 */
|
||||
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
|
||||
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
|
||||
return adlp_step_a_plane_format_modifiers;
|
||||
else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
|
||||
return gen12_plane_format_modifiers_mc_ccs;
|
||||
|
|
@ -2144,7 +2144,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
|
|||
DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
|
||||
DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
|
||||
if (DISPLAY_VER(dev_priv) >= 11)
|
||||
supported_rotations |= DRM_MODE_REFLECT_X;
|
||||
|
||||
drm_plane_create_rotation_property(&plane->base,
|
||||
|
|
@ -2174,12 +2174,12 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
|
|||
if (DISPLAY_VER(dev_priv) >= 12)
|
||||
drm_plane_enable_fb_damage_clips(&plane->base);
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
|
||||
if (DISPLAY_VER(dev_priv) >= 11)
|
||||
drm_plane_create_scaling_filter_property(&plane->base,
|
||||
BIT(DRM_SCALING_FILTER_DEFAULT) |
|
||||
BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
|
||||
|
||||
drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
|
||||
intel_plane_helper_add(plane);
|
||||
|
||||
return plane;
|
||||
|
||||
|
|
@ -2295,7 +2295,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
|
|||
break;
|
||||
}
|
||||
|
||||
if ((DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) && val & PLANE_CTL_FLIP_HORIZONTAL)
|
||||
if (DISPLAY_VER(dev_priv) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL)
|
||||
plane_config->rotation |= DRM_MODE_REFLECT_X;
|
||||
|
||||
/* 90/270 degree rotation would require extra work */
|
||||
|
|
|
|||
|
|
@ -447,7 +447,6 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem)
|
|||
break;
|
||||
case 8:
|
||||
case 9:
|
||||
case 10:
|
||||
if (IS_LP(i915))
|
||||
chv_get_stolen_reserved(i915, uncore,
|
||||
&reserved_base, &reserved_size);
|
||||
|
|
|
|||
|
|
@ -1055,7 +1055,7 @@ static bool vgpu_ips_enabled(struct intel_vgpu *vgpu)
|
|||
{
|
||||
struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
|
||||
|
||||
if (GRAPHICS_VER(dev_priv) == 9 || GRAPHICS_VER(dev_priv) == 10) {
|
||||
if (GRAPHICS_VER(dev_priv) == 9) {
|
||||
u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &
|
||||
GAMW_ECO_ENABLE_64K_IPS_FIELD;
|
||||
|
||||
|
|
|
|||
|
|
@ -538,20 +538,20 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
|
|||
max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
|
||||
rp_state_cap >> 16) & 0xff;
|
||||
max_freq *= (IS_GEN9_BC(dev_priv) ||
|
||||
GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
|
||||
GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1);
|
||||
seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
|
||||
intel_gpu_freq(rps, max_freq));
|
||||
|
||||
max_freq = (rp_state_cap & 0xff00) >> 8;
|
||||
max_freq *= (IS_GEN9_BC(dev_priv) ||
|
||||
GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
|
||||
GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1);
|
||||
seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
|
||||
intel_gpu_freq(rps, max_freq));
|
||||
|
||||
max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
|
||||
rp_state_cap >> 0) & 0xff;
|
||||
max_freq *= (IS_GEN9_BC(dev_priv) ||
|
||||
GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
|
||||
GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1);
|
||||
seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
|
||||
intel_gpu_freq(rps, max_freq));
|
||||
seq_printf(m, "Max overclocked frequency: %dMHz\n",
|
||||
|
|
|
|||
|
|
@ -620,7 +620,9 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
|
|||
|
||||
intel_opregion_setup(dev_priv);
|
||||
|
||||
intel_pcode_init(dev_priv);
|
||||
ret = intel_pcode_init(dev_priv);
|
||||
if (ret)
|
||||
goto err_msi;
|
||||
|
||||
/*
|
||||
* Fill the dram structure to get the system dram info. This will be
|
||||
|
|
@ -1231,6 +1233,10 @@ static int i915_drm_resume(struct drm_device *dev)
|
|||
|
||||
disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
|
||||
|
||||
ret = intel_pcode_init(dev_priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
sanitize_gpu(dev_priv);
|
||||
|
||||
ret = i915_ggtt_enable_hw(dev_priv);
|
||||
|
|
|
|||
|
|
@ -633,6 +633,9 @@ i915_fence_timeout(const struct drm_i915_private *i915)
|
|||
|
||||
#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
|
||||
|
||||
/* Amount of PSF GV points, BSpec precisely defines this */
|
||||
#define I915_NUM_PSF_GV_POINTS 3
|
||||
|
||||
struct ddi_vbt_port_info {
|
||||
/* Non-NULL if port present. */
|
||||
struct intel_bios_encoder_data *devdata;
|
||||
|
|
@ -1146,12 +1149,16 @@ struct drm_i915_private {
|
|||
INTEL_DRAM_LPDDR5,
|
||||
} type;
|
||||
u8 num_qgv_points;
|
||||
u8 num_psf_gv_points;
|
||||
} dram_info;
|
||||
|
||||
struct intel_bw_info {
|
||||
/* for each QGV point */
|
||||
unsigned int deratedbw[I915_NUM_QGV_POINTS];
|
||||
/* for each PSF GV point */
|
||||
unsigned int psf_bw[I915_NUM_PSF_GV_POINTS];
|
||||
u8 num_qgv_points;
|
||||
u8 num_psf_gv_points;
|
||||
u8 num_planes;
|
||||
} max_bw[6];
|
||||
|
||||
|
|
@ -1296,7 +1303,7 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
|
|||
|
||||
#define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
|
||||
|
||||
#define IP_VER(ver, rel) ((ver) << 8 | (rel))
|
||||
#define IP_VER(ver, rel) ((ver) << 8 | (rel))
|
||||
|
||||
#define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics_ver)
|
||||
#define GRAPHICS_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->graphics_ver, \
|
||||
|
|
@ -1323,7 +1330,7 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
|
|||
|
||||
#define IS_DISPLAY_STEP(__i915, since, until) \
|
||||
(drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
|
||||
INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) <= (until))
|
||||
INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
|
||||
|
||||
#define IS_GT_STEP(__i915, since, until) \
|
||||
(drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \
|
||||
|
|
@ -1426,7 +1433,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
|
|||
#define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
|
||||
#define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
|
||||
#define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
|
||||
#define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
|
||||
#define IS_CANNONLAKE(dev_priv) 0
|
||||
#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
|
||||
#define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
|
||||
IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
|
||||
|
|
@ -1492,8 +1499,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
|
|||
#define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \
|
||||
INTEL_INFO(dev_priv)->gt == 2)
|
||||
|
||||
#define IS_CNL_WITH_PORT_F(dev_priv) \
|
||||
IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
|
||||
#define IS_ICL_WITH_PORT_F(dev_priv) \
|
||||
IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
|
||||
|
||||
|
|
@ -1613,8 +1618,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
|
|||
#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
|
||||
(INTEL_INFO(dev_priv)->has_logical_ring_elsq)
|
||||
|
||||
#define HAS_MASTER_UNIT_IRQ(dev_priv) (INTEL_INFO(dev_priv)->has_master_unit_irq)
|
||||
|
||||
#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
|
||||
|
||||
#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
|
||||
|
|
@ -1640,12 +1643,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
|
|||
|
||||
/* WaRsDisableCoarsePowerGating:skl,cnl */
|
||||
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
|
||||
(IS_CANNONLAKE(dev_priv) || \
|
||||
IS_SKL_GT3(dev_priv) || \
|
||||
IS_SKL_GT4(dev_priv))
|
||||
(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
|
||||
|
||||
#define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
|
||||
#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 10 || \
|
||||
#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11 || \
|
||||
IS_GEMINILAKE(dev_priv) || \
|
||||
IS_KABYLAKE(dev_priv))
|
||||
|
||||
|
|
@ -1665,6 +1666,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
|
|||
|
||||
#define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
|
||||
|
||||
#define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
|
||||
#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
|
||||
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
|
||||
#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
|
||||
|
|
|
|||
|
|
@ -207,7 +207,7 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
|
|||
(!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
|
||||
return;
|
||||
|
||||
if (HAS_PCH_DG1(dev_priv))
|
||||
if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
|
||||
hpd->pch_hpd = hpd_sde_dg1;
|
||||
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
|
||||
hpd->pch_hpd = hpd_icp;
|
||||
|
|
@ -2297,11 +2297,10 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
|
|||
GEN9_AUX_CHANNEL_C |
|
||||
GEN9_AUX_CHANNEL_D;
|
||||
|
||||
if (IS_CNL_WITH_PORT_F(dev_priv) || DISPLAY_VER(dev_priv) == 11)
|
||||
mask |= CNL_AUX_CHANNEL_F;
|
||||
|
||||
if (DISPLAY_VER(dev_priv) == 11)
|
||||
if (DISPLAY_VER(dev_priv) == 11) {
|
||||
mask |= ICL_AUX_CHANNEL_F;
|
||||
mask |= ICL_AUX_CHANNEL_E;
|
||||
}
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
|
@ -2698,11 +2697,9 @@ gen11_display_irq_handler(struct drm_i915_private *i915)
|
|||
enable_rpm_wakeref_asserts(&i915->runtime_pm);
|
||||
}
|
||||
|
||||
static __always_inline irqreturn_t
|
||||
__gen11_irq_handler(struct drm_i915_private * const i915,
|
||||
u32 (*intr_disable)(void __iomem * const regs),
|
||||
void (*intr_enable)(void __iomem * const regs))
|
||||
static irqreturn_t gen11_irq_handler(int irq, void *arg)
|
||||
{
|
||||
struct drm_i915_private *i915 = arg;
|
||||
void __iomem * const regs = i915->uncore.regs;
|
||||
struct intel_gt *gt = &i915->gt;
|
||||
u32 master_ctl;
|
||||
|
|
@ -2711,9 +2708,9 @@ __gen11_irq_handler(struct drm_i915_private * const i915,
|
|||
if (!intel_irqs_enabled(i915))
|
||||
return IRQ_NONE;
|
||||
|
||||
master_ctl = intr_disable(regs);
|
||||
master_ctl = gen11_master_intr_disable(regs);
|
||||
if (!master_ctl) {
|
||||
intr_enable(regs);
|
||||
gen11_master_intr_enable(regs);
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
|
|
@ -2726,7 +2723,7 @@ __gen11_irq_handler(struct drm_i915_private * const i915,
|
|||
|
||||
gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
|
||||
|
||||
intr_enable(regs);
|
||||
gen11_master_intr_enable(regs);
|
||||
|
||||
gen11_gu_misc_irq_handler(gt, gu_misc_iir);
|
||||
|
||||
|
|
@ -2735,51 +2732,69 @@ __gen11_irq_handler(struct drm_i915_private * const i915,
|
|||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t gen11_irq_handler(int irq, void *arg)
|
||||
{
|
||||
return __gen11_irq_handler(arg,
|
||||
gen11_master_intr_disable,
|
||||
gen11_master_intr_enable);
|
||||
}
|
||||
|
||||
static u32 dg1_master_intr_disable_and_ack(void __iomem * const regs)
|
||||
static inline u32 dg1_master_intr_disable(void __iomem * const regs)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* First disable interrupts */
|
||||
raw_reg_write(regs, DG1_MSTR_UNIT_INTR, 0);
|
||||
raw_reg_write(regs, DG1_MSTR_TILE_INTR, 0);
|
||||
|
||||
/* Get the indication levels and ack the master unit */
|
||||
val = raw_reg_read(regs, DG1_MSTR_UNIT_INTR);
|
||||
val = raw_reg_read(regs, DG1_MSTR_TILE_INTR);
|
||||
if (unlikely(!val))
|
||||
return 0;
|
||||
|
||||
raw_reg_write(regs, DG1_MSTR_UNIT_INTR, val);
|
||||
|
||||
/*
|
||||
* Now with master disabled, get a sample of level indications
|
||||
* for this interrupt and ack them right away - we keep GEN11_MASTER_IRQ
|
||||
* out as this bit doesn't exist anymore for DG1
|
||||
*/
|
||||
val = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ) & ~GEN11_MASTER_IRQ;
|
||||
if (unlikely(!val))
|
||||
return 0;
|
||||
|
||||
raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, val);
|
||||
raw_reg_write(regs, DG1_MSTR_TILE_INTR, val);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline void dg1_master_intr_enable(void __iomem * const regs)
|
||||
{
|
||||
raw_reg_write(regs, DG1_MSTR_UNIT_INTR, DG1_MSTR_IRQ);
|
||||
raw_reg_write(regs, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
|
||||
}
|
||||
|
||||
static irqreturn_t dg1_irq_handler(int irq, void *arg)
|
||||
{
|
||||
return __gen11_irq_handler(arg,
|
||||
dg1_master_intr_disable_and_ack,
|
||||
dg1_master_intr_enable);
|
||||
struct drm_i915_private * const i915 = arg;
|
||||
struct intel_gt *gt = &i915->gt;
|
||||
void __iomem * const regs = i915->uncore.regs;
|
||||
u32 master_tile_ctl, master_ctl;
|
||||
u32 gu_misc_iir;
|
||||
|
||||
if (!intel_irqs_enabled(i915))
|
||||
return IRQ_NONE;
|
||||
|
||||
master_tile_ctl = dg1_master_intr_disable(regs);
|
||||
if (!master_tile_ctl) {
|
||||
dg1_master_intr_enable(regs);
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
/* FIXME: we only support tile 0 for now. */
|
||||
if (master_tile_ctl & DG1_MSTR_TILE(0)) {
|
||||
master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
|
||||
raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl);
|
||||
} else {
|
||||
DRM_ERROR("Tile not supported: 0x%08x\n", master_tile_ctl);
|
||||
dg1_master_intr_enable(regs);
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
gen11_gt_irq_handler(gt, master_ctl);
|
||||
|
||||
if (master_ctl & GEN11_DISPLAY_IRQ)
|
||||
gen11_display_irq_handler(i915);
|
||||
|
||||
gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
|
||||
|
||||
dg1_master_intr_enable(regs);
|
||||
|
||||
gen11_gu_misc_irq_handler(gt, gu_misc_iir);
|
||||
|
||||
pmu_irq_stats(i915, IRQ_HANDLED);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/* Called from drm generic code, passed 'crtc' which
|
||||
|
|
@ -3167,10 +3182,20 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv)
|
|||
{
|
||||
struct intel_uncore *uncore = &dev_priv->uncore;
|
||||
|
||||
if (HAS_MASTER_UNIT_IRQ(dev_priv))
|
||||
dg1_master_intr_disable_and_ack(dev_priv->uncore.regs);
|
||||
else
|
||||
gen11_master_intr_disable(dev_priv->uncore.regs);
|
||||
gen11_master_intr_disable(dev_priv->uncore.regs);
|
||||
|
||||
gen11_gt_irq_reset(&dev_priv->gt);
|
||||
gen11_display_irq_reset(dev_priv);
|
||||
|
||||
GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
|
||||
GEN3_IRQ_RESET(uncore, GEN8_PCU_);
|
||||
}
|
||||
|
||||
static void dg1_irq_reset(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct intel_uncore *uncore = &dev_priv->uncore;
|
||||
|
||||
dg1_master_intr_disable(dev_priv->uncore.regs);
|
||||
|
||||
gen11_gt_irq_reset(&dev_priv->gt);
|
||||
gen11_display_irq_reset(dev_priv);
|
||||
|
|
@ -3862,13 +3887,28 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
|
|||
|
||||
GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
|
||||
|
||||
if (HAS_MASTER_UNIT_IRQ(dev_priv)) {
|
||||
dg1_master_intr_enable(uncore->regs);
|
||||
intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_UNIT_INTR);
|
||||
} else {
|
||||
gen11_master_intr_enable(uncore->regs);
|
||||
intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ);
|
||||
gen11_master_intr_enable(uncore->regs);
|
||||
intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ);
|
||||
}
|
||||
|
||||
static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct intel_uncore *uncore = &dev_priv->uncore;
|
||||
u32 gu_misc_masked = GEN11_GU_MISC_GSE;
|
||||
|
||||
gen11_gt_irq_postinstall(&dev_priv->gt);
|
||||
|
||||
GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
|
||||
|
||||
if (HAS_DISPLAY(dev_priv)) {
|
||||
icp_irq_postinstall(dev_priv);
|
||||
gen8_de_irq_postinstall(dev_priv);
|
||||
intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL,
|
||||
GEN11_DISPLAY_IRQ_ENABLE);
|
||||
}
|
||||
|
||||
dg1_master_intr_enable(dev_priv->uncore.regs);
|
||||
intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_TILE_INTR);
|
||||
}
|
||||
|
||||
static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
|
||||
|
|
@ -4407,9 +4447,9 @@ static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
|
|||
else
|
||||
return i8xx_irq_handler;
|
||||
} else {
|
||||
if (HAS_MASTER_UNIT_IRQ(dev_priv))
|
||||
if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))
|
||||
return dg1_irq_handler;
|
||||
if (GRAPHICS_VER(dev_priv) >= 11)
|
||||
else if (GRAPHICS_VER(dev_priv) >= 11)
|
||||
return gen11_irq_handler;
|
||||
else if (GRAPHICS_VER(dev_priv) >= 8)
|
||||
return gen8_irq_handler;
|
||||
|
|
@ -4432,7 +4472,9 @@ static void intel_irq_reset(struct drm_i915_private *dev_priv)
|
|||
else
|
||||
i8xx_irq_reset(dev_priv);
|
||||
} else {
|
||||
if (GRAPHICS_VER(dev_priv) >= 11)
|
||||
if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))
|
||||
dg1_irq_reset(dev_priv);
|
||||
else if (GRAPHICS_VER(dev_priv) >= 11)
|
||||
gen11_irq_reset(dev_priv);
|
||||
else if (GRAPHICS_VER(dev_priv) >= 8)
|
||||
gen8_irq_reset(dev_priv);
|
||||
|
|
@ -4455,7 +4497,9 @@ static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
|
|||
else
|
||||
i8xx_irq_postinstall(dev_priv);
|
||||
} else {
|
||||
if (GRAPHICS_VER(dev_priv) >= 11)
|
||||
if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))
|
||||
dg1_irq_postinstall(dev_priv);
|
||||
else if (GRAPHICS_VER(dev_priv) >= 11)
|
||||
gen11_irq_postinstall(dev_priv);
|
||||
else if (GRAPHICS_VER(dev_priv) >= 8)
|
||||
gen8_irq_postinstall(dev_priv);
|
||||
|
|
|
|||
|
|
@ -782,27 +782,13 @@ static const struct intel_device_info cml_gt2_info = {
|
|||
.gt = 2,
|
||||
};
|
||||
|
||||
#define GEN10_FEATURES \
|
||||
GEN9_FEATURES, \
|
||||
GEN(10), \
|
||||
.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ \
|
||||
.display.has_dsc = 1, \
|
||||
.has_coherent_ggtt = false, \
|
||||
GLK_COLORS
|
||||
|
||||
static const struct intel_device_info cnl_info = {
|
||||
GEN10_FEATURES,
|
||||
PLATFORM(INTEL_CANNONLAKE),
|
||||
.gt = 2,
|
||||
};
|
||||
|
||||
#define GEN11_DEFAULT_PAGE_SIZES \
|
||||
.page_sizes = I915_GTT_PAGE_SIZE_4K | \
|
||||
I915_GTT_PAGE_SIZE_64K | \
|
||||
I915_GTT_PAGE_SIZE_2M
|
||||
|
||||
#define GEN11_FEATURES \
|
||||
GEN10_FEATURES, \
|
||||
GEN9_FEATURES, \
|
||||
GEN11_DEFAULT_PAGE_SIZES, \
|
||||
.abox_mask = BIT(0), \
|
||||
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
|
||||
|
|
@ -825,10 +811,12 @@ static const struct intel_device_info cnl_info = {
|
|||
[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
|
||||
}, \
|
||||
GEN(11), \
|
||||
.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }, \
|
||||
.dbuf.size = 2048, \
|
||||
.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
|
||||
.has_logical_ring_elsq = 1, \
|
||||
.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
|
||||
.display.has_dsc = 1, \
|
||||
.has_coherent_ggtt = false, \
|
||||
.has_logical_ring_elsq = 1
|
||||
|
||||
static const struct intel_device_info icl_info = {
|
||||
GEN11_FEATURES,
|
||||
|
|
@ -902,7 +890,6 @@ static const struct intel_device_info rkl_info = {
|
|||
|
||||
#define DGFX_FEATURES \
|
||||
.memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
|
||||
.has_master_unit_irq = 1, \
|
||||
.has_llc = 0, \
|
||||
.has_snoop = 1, \
|
||||
.is_dgfx = 1
|
||||
|
|
@ -910,6 +897,7 @@ static const struct intel_device_info rkl_info = {
|
|||
static const struct intel_device_info dg1_info __maybe_unused = {
|
||||
GEN12_FEATURES,
|
||||
DGFX_FEATURES,
|
||||
.graphics_rel = 10,
|
||||
PLATFORM(INTEL_DG1),
|
||||
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
|
||||
.require_force_probe = 1,
|
||||
|
|
@ -942,7 +930,7 @@ static const struct intel_device_info adl_s_info = {
|
|||
|
||||
#define XE_LPD_FEATURES \
|
||||
.abox_mask = GENMASK(1, 0), \
|
||||
.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }, \
|
||||
.color = { .degamma_lut_size = 0, .gamma_lut_size = 0 }, \
|
||||
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
|
||||
BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
|
||||
.dbuf.size = 4096, \
|
||||
|
|
@ -979,8 +967,8 @@ static const struct intel_device_info adl_p_info = {
|
|||
GEN12_FEATURES,
|
||||
XE_LPD_FEATURES,
|
||||
PLATFORM(INTEL_ALDERLAKE_P),
|
||||
.has_cdclk_crawl = 1,
|
||||
.require_force_probe = 1,
|
||||
.display.has_cdclk_crawl = 1,
|
||||
.display.has_modular_fia = 1,
|
||||
.display.has_psr_hw_tracking = 0,
|
||||
.platform_engine_mask =
|
||||
|
|
@ -1120,7 +1108,6 @@ static const struct pci_device_id pciidlist[] = {
|
|||
INTEL_CML_GT2_IDS(&cml_gt2_info),
|
||||
INTEL_CML_U_GT1_IDS(&cml_gt1_info),
|
||||
INTEL_CML_U_GT2_IDS(&cml_gt2_info),
|
||||
INTEL_CNL_IDS(&cnl_info),
|
||||
INTEL_ICL_11_IDS(&icl_info),
|
||||
INTEL_EHL_IDS(&ehl_info),
|
||||
INTEL_JSL_IDS(&jsl_info),
|
||||
|
|
|
|||
|
|
@ -1256,7 +1256,6 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
|
|||
|
||||
case 8:
|
||||
case 9:
|
||||
case 10:
|
||||
if (intel_engine_uses_guc(ce->engine)) {
|
||||
/*
|
||||
* When using GuC, the context descriptor we write in
|
||||
|
|
@ -2589,7 +2588,7 @@ static void gen8_disable_metric_set(struct i915_perf_stream *stream)
|
|||
intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);
|
||||
}
|
||||
|
||||
static void gen10_disable_metric_set(struct i915_perf_stream *stream)
|
||||
static void gen11_disable_metric_set(struct i915_perf_stream *stream)
|
||||
{
|
||||
struct intel_uncore *uncore = stream->uncore;
|
||||
|
||||
|
|
@ -3896,7 +3895,7 @@ static bool gen8_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
|
|||
REG_IN_RANGE(addr, RPM_CONFIG0, NOA_CONFIG(8));
|
||||
}
|
||||
|
||||
static bool gen10_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
|
||||
static bool gen11_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
|
||||
{
|
||||
return gen8_is_valid_mux_addr(perf, addr) ||
|
||||
REG_EQUAL(addr, GEN10_NOA_WRITE_HIGH) ||
|
||||
|
|
@ -4319,7 +4318,6 @@ static void oa_init_supported_formats(struct i915_perf *perf)
|
|||
case INTEL_GEMINILAKE:
|
||||
case INTEL_COFFEELAKE:
|
||||
case INTEL_COMETLAKE:
|
||||
case INTEL_CANNONLAKE:
|
||||
case INTEL_ICELAKE:
|
||||
case INTEL_ELKHARTLAKE:
|
||||
case INTEL_JASPERLAKE:
|
||||
|
|
@ -4404,27 +4402,23 @@ void i915_perf_init(struct drm_i915_private *i915)
|
|||
|
||||
perf->gen8_valid_ctx_bit = BIT(16);
|
||||
}
|
||||
} else if (IS_GRAPHICS_VER(i915, 10, 11)) {
|
||||
} else if (GRAPHICS_VER(i915) == 11) {
|
||||
perf->ops.is_valid_b_counter_reg =
|
||||
gen7_is_valid_b_counter_addr;
|
||||
perf->ops.is_valid_mux_reg =
|
||||
gen10_is_valid_mux_addr;
|
||||
gen11_is_valid_mux_addr;
|
||||
perf->ops.is_valid_flex_reg =
|
||||
gen8_is_valid_flex_addr;
|
||||
|
||||
perf->ops.oa_enable = gen8_oa_enable;
|
||||
perf->ops.oa_disable = gen8_oa_disable;
|
||||
perf->ops.enable_metric_set = gen8_enable_metric_set;
|
||||
perf->ops.disable_metric_set = gen10_disable_metric_set;
|
||||
perf->ops.disable_metric_set = gen11_disable_metric_set;
|
||||
perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
|
||||
|
||||
if (GRAPHICS_VER(i915) == 10) {
|
||||
perf->ctx_oactxctrl_offset = 0x128;
|
||||
perf->ctx_flexeu0_offset = 0x3de;
|
||||
} else {
|
||||
perf->ctx_oactxctrl_offset = 0x124;
|
||||
perf->ctx_flexeu0_offset = 0x78e;
|
||||
}
|
||||
perf->ctx_oactxctrl_offset = 0x124;
|
||||
perf->ctx_flexeu0_offset = 0x78e;
|
||||
|
||||
perf->gen8_valid_ctx_bit = BIT(16);
|
||||
} else if (GRAPHICS_VER(i915) == 12) {
|
||||
perf->ops.is_valid_b_counter_reg =
|
||||
|
|
|
|||
|
|
@ -430,7 +430,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
|
|||
#define GEN12_HCP_SFC_LOCK_ACK_BIT REG_BIT(1)
|
||||
#define GEN12_HCP_SFC_USAGE_BIT REG_BIT(0)
|
||||
|
||||
#define GEN12_SFC_DONE(n) _MMIO(0x1cc00 + (n) * 0x100)
|
||||
#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
|
||||
#define GEN12_SFC_DONE_MAX 4
|
||||
|
||||
#define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)
|
||||
|
|
@ -1885,7 +1885,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
|
|||
#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
|
||||
|
||||
/*
|
||||
* CNL/ICL Port/COMBO-PHY Registers
|
||||
* ICL Port/COMBO-PHY Registers
|
||||
*/
|
||||
#define _ICL_COMBOPHY_A 0x162000
|
||||
#define _ICL_COMBOPHY_B 0x6C000
|
||||
|
|
@ -1899,11 +1899,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
|
|||
_RKL_COMBOPHY_D, \
|
||||
_ADL_COMBOPHY_E)
|
||||
|
||||
/* CNL/ICL Port CL_DW registers */
|
||||
/* ICL Port CL_DW registers */
|
||||
#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
|
||||
4 * (dw))
|
||||
|
||||
#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
|
||||
#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
|
||||
#define CL_POWER_DOWN_ENABLE (1 << 4)
|
||||
#define SUS_CLOCK_CONFIG (3 << 0)
|
||||
|
|
@ -1928,19 +1927,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
|
|||
#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
|
||||
#define ICL_LANE_ENABLE_AUX (1 << 0)
|
||||
|
||||
/* CNL/ICL Port COMP_DW registers */
|
||||
/* ICL Port COMP_DW registers */
|
||||
#define _ICL_PORT_COMP 0x100
|
||||
#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
|
||||
_ICL_PORT_COMP + 4 * (dw))
|
||||
|
||||
#define CNL_PORT_COMP_DW0 _MMIO(0x162100)
|
||||
#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
|
||||
#define COMP_INIT (1 << 31)
|
||||
|
||||
#define CNL_PORT_COMP_DW1 _MMIO(0x162104)
|
||||
#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
|
||||
|
||||
#define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
|
||||
#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
|
||||
#define PROCESS_INFO_DOT_0 (0 << 26)
|
||||
#define PROCESS_INFO_DOT_1 (1 << 26)
|
||||
|
|
@ -1956,38 +1952,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
|
|||
#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
|
||||
#define IREFGEN (1 << 24)
|
||||
|
||||
#define CNL_PORT_COMP_DW9 _MMIO(0x162124)
|
||||
#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
|
||||
|
||||
#define CNL_PORT_COMP_DW10 _MMIO(0x162128)
|
||||
#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
|
||||
|
||||
/* CNL/ICL Port PCS registers */
|
||||
#define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
|
||||
#define _CNL_PORT_PCS_DW1_GRP_B 0x162384
|
||||
#define _CNL_PORT_PCS_DW1_GRP_C 0x162B04
|
||||
#define _CNL_PORT_PCS_DW1_GRP_D 0x162B84
|
||||
#define _CNL_PORT_PCS_DW1_GRP_F 0x162A04
|
||||
#define _CNL_PORT_PCS_DW1_LN0_AE 0x162404
|
||||
#define _CNL_PORT_PCS_DW1_LN0_B 0x162604
|
||||
#define _CNL_PORT_PCS_DW1_LN0_C 0x162C04
|
||||
#define _CNL_PORT_PCS_DW1_LN0_D 0x162E04
|
||||
#define _CNL_PORT_PCS_DW1_LN0_F 0x162804
|
||||
#define CNL_PORT_PCS_DW1_GRP(phy) _MMIO(_PICK(phy, \
|
||||
_CNL_PORT_PCS_DW1_GRP_AE, \
|
||||
_CNL_PORT_PCS_DW1_GRP_B, \
|
||||
_CNL_PORT_PCS_DW1_GRP_C, \
|
||||
_CNL_PORT_PCS_DW1_GRP_D, \
|
||||
_CNL_PORT_PCS_DW1_GRP_AE, \
|
||||
_CNL_PORT_PCS_DW1_GRP_F))
|
||||
#define CNL_PORT_PCS_DW1_LN0(phy) _MMIO(_PICK(phy, \
|
||||
_CNL_PORT_PCS_DW1_LN0_AE, \
|
||||
_CNL_PORT_PCS_DW1_LN0_B, \
|
||||
_CNL_PORT_PCS_DW1_LN0_C, \
|
||||
_CNL_PORT_PCS_DW1_LN0_D, \
|
||||
_CNL_PORT_PCS_DW1_LN0_AE, \
|
||||
_CNL_PORT_PCS_DW1_LN0_F))
|
||||
|
||||
/* ICL Port PCS registers */
|
||||
#define _ICL_PORT_PCS_AUX 0x300
|
||||
#define _ICL_PORT_PCS_GRP 0x600
|
||||
#define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
|
||||
|
|
@ -2006,34 +1975,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
|
|||
#define LATENCY_OPTIM_MASK (0x3 << 2)
|
||||
#define LATENCY_OPTIM_VAL(x) ((x) << 2)
|
||||
|
||||
/* CNL/ICL Port TX registers */
|
||||
#define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340
|
||||
#define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0
|
||||
#define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40
|
||||
#define _CNL_PORT_TX_D_GRP_OFFSET 0x162BC0
|
||||
#define _CNL_PORT_TX_F_GRP_OFFSET 0x162A40
|
||||
#define _CNL_PORT_TX_AE_LN0_OFFSET 0x162440
|
||||
#define _CNL_PORT_TX_B_LN0_OFFSET 0x162640
|
||||
#define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40
|
||||
#define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40
|
||||
#define _CNL_PORT_TX_F_LN0_OFFSET 0x162840
|
||||
#define _CNL_PORT_TX_DW_GRP(dw, port) (_PICK((port), \
|
||||
_CNL_PORT_TX_AE_GRP_OFFSET, \
|
||||
_CNL_PORT_TX_B_GRP_OFFSET, \
|
||||
_CNL_PORT_TX_B_GRP_OFFSET, \
|
||||
_CNL_PORT_TX_D_GRP_OFFSET, \
|
||||
_CNL_PORT_TX_AE_GRP_OFFSET, \
|
||||
_CNL_PORT_TX_F_GRP_OFFSET) + \
|
||||
4 * (dw))
|
||||
#define _CNL_PORT_TX_DW_LN0(dw, port) (_PICK((port), \
|
||||
_CNL_PORT_TX_AE_LN0_OFFSET, \
|
||||
_CNL_PORT_TX_B_LN0_OFFSET, \
|
||||
_CNL_PORT_TX_B_LN0_OFFSET, \
|
||||
_CNL_PORT_TX_D_LN0_OFFSET, \
|
||||
_CNL_PORT_TX_AE_LN0_OFFSET, \
|
||||
_CNL_PORT_TX_F_LN0_OFFSET) + \
|
||||
4 * (dw))
|
||||
|
||||
/* ICL Port TX registers */
|
||||
#define _ICL_PORT_TX_AUX 0x380
|
||||
#define _ICL_PORT_TX_GRP 0x680
|
||||
#define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
|
||||
|
|
@ -2045,8 +1987,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
|
|||
#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
|
||||
_ICL_PORT_TX_LN(ln) + 4 * (dw))
|
||||
|
||||
#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port))
|
||||
#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port))
|
||||
#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
|
||||
#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
|
||||
#define ICL_PORT_TX_DW2_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
|
||||
|
|
@ -2059,13 +1999,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
|
|||
#define RCOMP_SCALAR(x) ((x) << 0)
|
||||
#define RCOMP_SCALAR_MASK (0xFF << 0)
|
||||
|
||||
#define _CNL_PORT_TX_DW4_LN0_AE 0x162450
|
||||
#define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
|
||||
#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))
|
||||
#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))
|
||||
#define CNL_PORT_TX_DW4_LN(ln, port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
|
||||
((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
|
||||
_CNL_PORT_TX_DW4_LN0_AE)))
|
||||
#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
|
||||
#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
|
||||
#define ICL_PORT_TX_DW4_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
|
||||
|
|
@ -2078,8 +2011,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
|
|||
#define CURSOR_COEFF(x) ((x) << 0)
|
||||
#define CURSOR_COEFF_MASK (0x3F << 0)
|
||||
|
||||
#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port))
|
||||
#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port))
|
||||
#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
|
||||
#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
|
||||
#define ICL_PORT_TX_DW5_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
|
||||
|
|
@ -2091,8 +2022,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
|
|||
#define RTERM_SELECT(x) ((x) << 3)
|
||||
#define RTERM_SELECT_MASK (0x7 << 3)
|
||||
|
||||
#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
|
||||
#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
|
||||
#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
|
||||
#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
|
||||
#define ICL_PORT_TX_DW7_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
|
||||
|
|
@ -2286,6 +2215,68 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
|
|||
#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
|
||||
#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
|
||||
|
||||
/*
|
||||
* DG2 SNPS PHY registers (TC1 = PHY_E)
|
||||
*/
|
||||
#define _SNPS_PHY_A_BASE 0x168000
|
||||
#define _SNPS_PHY_B_BASE 0x169000
|
||||
#define _SNPS_PHY(phy) _PHY(phy, \
|
||||
_SNPS_PHY_A_BASE, \
|
||||
_SNPS_PHY_B_BASE)
|
||||
#define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \
|
||||
_SNPS_PHY_A_BASE + (reg))
|
||||
#define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg))
|
||||
#define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \
|
||||
(reg) + (ln) * 0x10))
|
||||
|
||||
#define SNPS_PHY_MPLLB_CP(phy) _MMIO_SNPS(phy, 0x168000)
|
||||
#define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25)
|
||||
#define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17)
|
||||
#define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9)
|
||||
#define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1)
|
||||
|
||||
#define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004)
|
||||
#define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
|
||||
#define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
|
||||
#define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
|
||||
#define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
|
||||
#define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
|
||||
#define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
|
||||
|
||||
#define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008)
|
||||
#define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
|
||||
#define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)
|
||||
#define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0)
|
||||
|
||||
#define SNPS_PHY_MPLLB_FRACN2(phy) _MMIO_SNPS(phy, 0x16800C)
|
||||
#define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16)
|
||||
#define SNPS_PHY_MPLLB_FRACN_QUOT REG_GENMASK(15, 0)
|
||||
|
||||
#define SNPS_PHY_MPLLB_SSCEN(phy) _MMIO_SNPS(phy, 0x168014)
|
||||
#define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)
|
||||
#define SNPS_PHY_MPLLB_SSC_UP_SPREAD REG_BIT(30)
|
||||
#define SNPS_PHY_MPLLB_SSC_PEAK REG_GENMASK(29, 10)
|
||||
|
||||
#define SNPS_PHY_MPLLB_SSCSTEP(phy) _MMIO_SNPS(phy, 0x168018)
|
||||
#define SNPS_PHY_MPLLB_SSC_STEPSIZE REG_GENMASK(31, 11)
|
||||
|
||||
#define SNPS_PHY_MPLLB_DIV2(phy) _MMIO_SNPS(phy, 0x16801C)
|
||||
#define SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV REG_GENMASK(19, 18)
|
||||
#define SNPS_PHY_MPLLB_HDMI_DIV REG_GENMASK(17, 15)
|
||||
#define SNPS_PHY_MPLLB_REF_CLK_DIV REG_GENMASK(14, 12)
|
||||
#define SNPS_PHY_MPLLB_MULTIPLIER REG_GENMASK(11, 0)
|
||||
|
||||
#define SNPS_PHY_REF_CONTROL(phy) _MMIO_SNPS(phy, 0x168188)
|
||||
#define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27)
|
||||
|
||||
#define SNPS_PHY_TX_REQ(phy) _MMIO_SNPS(phy, 0x168200)
|
||||
#define SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR REG_GENMASK(31, 30)
|
||||
|
||||
#define SNPS_PHY_TX_EQ(ln, phy) _MMIO_SNPS_LN(ln, phy, 0x168300)
|
||||
#define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18)
|
||||
#define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10)
|
||||
#define SNPS_PHY_TX_EQ_PRE REG_GENMASK(7, 2)
|
||||
|
||||
/* The spec defines this only for BXT PHY0, but lets assume that this
|
||||
* would exist for PHY1 too if it had a second channel.
|
||||
*/
|
||||
|
|
@ -4626,7 +4617,7 @@ enum {
|
|||
#define _PSR2_CTL_EDP 0x6f900
|
||||
#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A)
|
||||
#define EDP_PSR2_ENABLE (1 << 31)
|
||||
#define EDP_SU_TRACK_ENABLE (1 << 30)
|
||||
#define EDP_SU_TRACK_ENABLE (1 << 30) /* up to adl-p */
|
||||
#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28)
|
||||
#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28)
|
||||
#define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */
|
||||
|
|
@ -4695,17 +4686,23 @@ enum {
|
|||
#define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
|
||||
#define PSR2_SU_STATUS_FRAMES 8
|
||||
|
||||
#define _PSR2_MAN_TRK_CTL_A 0x60910
|
||||
#define _PSR2_MAN_TRK_CTL_EDP 0x6f910
|
||||
#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
|
||||
#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
|
||||
#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)
|
||||
#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
|
||||
#define _PSR2_MAN_TRK_CTL_A 0x60910
|
||||
#define _PSR2_MAN_TRK_CTL_EDP 0x6f910
|
||||
#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
|
||||
#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
|
||||
#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)
|
||||
#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
|
||||
#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11)
|
||||
#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
|
||||
#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
|
||||
#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
|
||||
#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
|
||||
#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
|
||||
#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
|
||||
#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
|
||||
#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16)
|
||||
#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
|
||||
#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0)
|
||||
#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
|
||||
#define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14)
|
||||
#define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
|
||||
|
||||
/* Icelake DSC Rate Control Range Parameter Registers */
|
||||
#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
|
||||
|
|
@ -7754,11 +7751,11 @@ enum {
|
|||
#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
|
||||
_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
|
||||
_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
|
||||
#define CNL_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \
|
||||
#define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \
|
||||
_ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
|
||||
_ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)
|
||||
|
||||
#define CNL_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
|
||||
#define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
|
||||
_ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
|
||||
_ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
|
||||
/* legacy palette */
|
||||
|
|
@ -7973,7 +7970,7 @@ enum {
|
|||
#define DSI1_NON_TE (1 << 31)
|
||||
#define DSI0_NON_TE (1 << 30)
|
||||
#define ICL_AUX_CHANNEL_E (1 << 29)
|
||||
#define CNL_AUX_CHANNEL_F (1 << 28)
|
||||
#define ICL_AUX_CHANNEL_F (1 << 28)
|
||||
#define GEN9_AUX_CHANNEL_D (1 << 27)
|
||||
#define GEN9_AUX_CHANNEL_C (1 << 26)
|
||||
#define GEN9_AUX_CHANNEL_B (1 << 25)
|
||||
|
|
@ -8025,9 +8022,9 @@ enum {
|
|||
#define GEN11_GT_DW1_IRQ (1 << 1)
|
||||
#define GEN11_GT_DW0_IRQ (1 << 0)
|
||||
|
||||
#define DG1_MSTR_UNIT_INTR _MMIO(0x190008)
|
||||
#define DG1_MSTR_TILE_INTR _MMIO(0x190008)
|
||||
#define DG1_MSTR_IRQ REG_BIT(31)
|
||||
#define DG1_MSTR_UNIT(u) REG_BIT(u)
|
||||
#define DG1_MSTR_TILE(t) REG_BIT(t)
|
||||
|
||||
#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
|
||||
#define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
|
||||
|
|
@ -8166,7 +8163,6 @@ enum {
|
|||
#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
|
||||
|
||||
#define CHICKEN_MISC_2 _MMIO(0x42084)
|
||||
#define CNL_COMP_PWR_DOWN (1 << 23)
|
||||
#define KBL_ARB_FILL_SPARE_14 REG_BIT(14)
|
||||
#define KBL_ARB_FILL_SPARE_13 REG_BIT(13)
|
||||
#define GLK_CL2_PWR_DOWN (1 << 12)
|
||||
|
|
@ -8204,15 +8200,16 @@ enum {
|
|||
[TRANSCODER_B] = _CHICKEN_TRANS_B, \
|
||||
[TRANSCODER_C] = _CHICKEN_TRANS_C, \
|
||||
[TRANSCODER_D] = _CHICKEN_TRANS_D))
|
||||
#define HSW_FRAME_START_DELAY_MASK (3 << 27)
|
||||
#define HSW_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
|
||||
#define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
|
||||
#define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
|
||||
#define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
|
||||
#define DDIE_TRAINING_OVERRIDE_ENABLE (1 << 17) /* CHICKEN_TRANS_A only */
|
||||
#define DDIE_TRAINING_OVERRIDE_VALUE (1 << 16) /* CHICKEN_TRANS_A only */
|
||||
#define PSR2_ADD_VERTICAL_LINE_COUNT (1 << 15)
|
||||
#define PSR2_VSC_ENABLE_PROG_HEADER (1 << 12)
|
||||
#define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
|
||||
#define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
|
||||
#define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
|
||||
#define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
|
||||
#define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
|
||||
#define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
|
||||
#define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
|
||||
#define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
|
||||
#define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
|
||||
#define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
|
||||
|
||||
#define DISP_ARB_CTL _MMIO(0x45000)
|
||||
#define DISP_FBC_MEMORY_WAKE (1 << 31)
|
||||
|
|
@ -8270,9 +8267,8 @@ enum {
|
|||
|
||||
#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
|
||||
#define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30)
|
||||
#define CNL_DELAY_PMRSP (1 << 22)
|
||||
#define ICL_DELAY_PMRSP (1 << 22)
|
||||
#define MASK_WAKEMEM (1 << 13)
|
||||
#define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
|
||||
|
||||
#define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
|
||||
#define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
|
||||
|
|
@ -8293,10 +8289,9 @@ enum {
|
|||
#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
|
||||
#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
|
||||
#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
|
||||
#define CNL_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
|
||||
#define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
|
||||
|
||||
#define SKL_DSSM _MMIO(0x51004)
|
||||
#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
|
||||
#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
|
||||
#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
|
||||
#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
|
||||
|
|
@ -8395,7 +8390,6 @@ enum {
|
|||
|
||||
/* GEN8 chicken */
|
||||
#define HDC_CHICKEN0 _MMIO(0x7300)
|
||||
#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
|
||||
#define ICL_HDC_MODE _MMIO(0xE5F4)
|
||||
#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15)
|
||||
#define HDC_FENCE_DEST_SLM_DISABLE (1 << 14)
|
||||
|
|
@ -8429,7 +8423,8 @@ enum {
|
|||
#define _PIPEC_CHICKEN 0x72038
|
||||
#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
|
||||
_PIPEB_CHICKEN)
|
||||
#define UNDERRUN_RECOVERY_DISABLE REG_BIT(30)
|
||||
#define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30)
|
||||
#define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30)
|
||||
#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
|
||||
#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
|
||||
|
||||
|
|
@ -9411,9 +9406,13 @@ enum {
|
|||
#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
|
||||
#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
|
||||
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
|
||||
#define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
|
||||
#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
|
||||
#define ICL_PCODE_POINTS_RESTRICTED 0x0
|
||||
#define ICL_PCODE_POINTS_RESTRICTED_MASK 0x1
|
||||
#define ICL_PCODE_POINTS_RESTRICTED_MASK 0xf
|
||||
#define ADLS_PSF_PT_SHIFT 8
|
||||
#define ADLS_QGV_PT_MASK REG_GENMASK(7, 0)
|
||||
#define ADLS_PSF_PT_MASK REG_GENMASK(10, 8)
|
||||
#define GEN6_PCODE_READ_D_COMP 0x10
|
||||
#define GEN6_PCODE_WRITE_D_COMP 0x11
|
||||
#define ICL_PCODE_EXIT_TCCOLD 0x12
|
||||
|
|
@ -9573,7 +9572,6 @@ enum {
|
|||
#define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
|
||||
#define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
|
||||
#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
|
||||
#define CNL_FAST_ANISO_L1_BANKING_FIX (1 << 4)
|
||||
#define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1)
|
||||
|
||||
#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
|
||||
|
|
@ -9754,15 +9752,12 @@ enum {
|
|||
/* HSW/BDW power well */
|
||||
#define HSW_PW_CTL_IDX_GLOBAL 15
|
||||
|
||||
/* SKL/BXT/GLK/CNL power wells */
|
||||
/* SKL/BXT/GLK power wells */
|
||||
#define SKL_PW_CTL_IDX_PW_2 15
|
||||
#define SKL_PW_CTL_IDX_PW_1 14
|
||||
#define CNL_PW_CTL_IDX_AUX_F 12
|
||||
#define CNL_PW_CTL_IDX_AUX_D 11
|
||||
#define GLK_PW_CTL_IDX_AUX_C 10
|
||||
#define GLK_PW_CTL_IDX_AUX_B 9
|
||||
#define GLK_PW_CTL_IDX_AUX_A 8
|
||||
#define CNL_PW_CTL_IDX_DDI_F 6
|
||||
#define SKL_PW_CTL_IDX_DDI_D 4
|
||||
#define SKL_PW_CTL_IDX_DDI_C 3
|
||||
#define SKL_PW_CTL_IDX_DDI_B 2
|
||||
|
|
@ -9861,19 +9856,6 @@ enum skl_power_gate {
|
|||
((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
|
||||
#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
|
||||
|
||||
#define _CNL_AUX_REG_IDX(pw_idx) ((pw_idx) - GLK_PW_CTL_IDX_AUX_B)
|
||||
#define _CNL_AUX_ANAOVRD1_B 0x162250
|
||||
#define _CNL_AUX_ANAOVRD1_C 0x162210
|
||||
#define _CNL_AUX_ANAOVRD1_D 0x1622D0
|
||||
#define _CNL_AUX_ANAOVRD1_F 0x162A90
|
||||
#define CNL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \
|
||||
_CNL_AUX_ANAOVRD1_B, \
|
||||
_CNL_AUX_ANAOVRD1_C, \
|
||||
_CNL_AUX_ANAOVRD1_D, \
|
||||
_CNL_AUX_ANAOVRD1_F))
|
||||
#define CNL_AUX_ANAOVRD1_ENABLE (1 << 16)
|
||||
#define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23)
|
||||
|
||||
#define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
|
||||
#define _ICL_AUX_ANAOVRD1_A 0x162398
|
||||
#define _ICL_AUX_ANAOVRD1_B 0x6C398
|
||||
|
|
@ -10173,11 +10155,11 @@ enum skl_power_gate {
|
|||
#define TRANS_DDI_BPC_10 (1 << 20)
|
||||
#define TRANS_DDI_BPC_6 (2 << 20)
|
||||
#define TRANS_DDI_BPC_12 (3 << 20)
|
||||
#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) /* bdw-cnl */
|
||||
#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18)
|
||||
#define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x))
|
||||
#define TRANS_DDI_PVSYNC (1 << 17)
|
||||
#define TRANS_DDI_PHSYNC (1 << 16)
|
||||
#define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) /* bdw-cnl */
|
||||
#define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15)
|
||||
#define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
|
||||
#define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
|
||||
#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
|
||||
|
|
@ -10210,6 +10192,9 @@ enum skl_power_gate {
|
|||
#define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
|
||||
#define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
|
||||
|
||||
#define TRANS_CMTG_CHICKEN _MMIO(0x6fa90)
|
||||
#define DISABLE_DPT_CLK_GATING REG_BIT(1)
|
||||
|
||||
/* DisplayPort Transport Control */
|
||||
#define _DP_TP_CTL_A 0x64040
|
||||
#define _DP_TP_CTL_B 0x64140
|
||||
|
|
@ -10533,17 +10518,6 @@ enum skl_power_gate {
|
|||
#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
|
||||
#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
|
||||
|
||||
/*
|
||||
* CNL Clocks
|
||||
*/
|
||||
#define DPCLKA_CFGCR0 _MMIO(0x6C200)
|
||||
#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
|
||||
(port) + 10))
|
||||
#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
|
||||
(port) * 2)
|
||||
#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
|
||||
#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
|
||||
|
||||
/* ICL Clocks */
|
||||
#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
|
||||
#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5))
|
||||
|
|
@ -10599,7 +10573,7 @@ enum skl_power_gate {
|
|||
ADLS_DPCLKA_DDIJ_SEL_MASK, \
|
||||
ADLS_DPCLKA_DDIK_SEL_MASK)
|
||||
|
||||
/* CNL PLL */
|
||||
/* ICL PLL */
|
||||
#define DPLL0_ENABLE 0x46010
|
||||
#define DPLL1_ENABLE 0x46014
|
||||
#define _ADLS_DPLL2_ENABLE 0x46018
|
||||
|
|
@ -10608,9 +10582,14 @@ enum skl_power_gate {
|
|||
#define PLL_LOCK (1 << 30)
|
||||
#define PLL_POWER_ENABLE (1 << 27)
|
||||
#define PLL_POWER_STATE (1 << 26)
|
||||
#define CNL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
|
||||
#define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
|
||||
_ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
|
||||
|
||||
#define _DG2_PLL3_ENABLE 0x4601C
|
||||
|
||||
#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
|
||||
_ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE)
|
||||
|
||||
#define TBT_PLL_ENABLE _MMIO(0x46020)
|
||||
|
||||
#define _MG_PLL1_ENABLE 0x46030
|
||||
|
|
@ -10776,60 +10755,52 @@ enum skl_power_gate {
|
|||
_MG_PLL_TDC_COLDST_BIAS_PORT1, \
|
||||
_MG_PLL_TDC_COLDST_BIAS_PORT2)
|
||||
|
||||
#define _CNL_DPLL0_CFGCR0 0x6C000
|
||||
#define _CNL_DPLL1_CFGCR0 0x6C080
|
||||
#define DPLL_CFGCR0_HDMI_MODE (1 << 30)
|
||||
#define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
|
||||
#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
|
||||
#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
|
||||
#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
|
||||
#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
|
||||
#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
|
||||
#define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
|
||||
|
||||
#define _CNL_DPLL0_CFGCR1 0x6C004
|
||||
#define _CNL_DPLL1_CFGCR1 0x6C084
|
||||
#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
|
||||
#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
|
||||
#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
|
||||
#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
|
||||
#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
|
||||
#define DPLL_CFGCR1_KDIV_MASK (7 << 6)
|
||||
#define DPLL_CFGCR1_KDIV_SHIFT (6)
|
||||
#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
|
||||
#define DPLL_CFGCR1_KDIV_1 (1 << 6)
|
||||
#define DPLL_CFGCR1_KDIV_2 (2 << 6)
|
||||
#define DPLL_CFGCR1_KDIV_3 (4 << 6)
|
||||
#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
|
||||
#define DPLL_CFGCR1_PDIV_SHIFT (2)
|
||||
#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
|
||||
#define DPLL_CFGCR1_PDIV_2 (1 << 2)
|
||||
#define DPLL_CFGCR1_PDIV_3 (2 << 2)
|
||||
#define DPLL_CFGCR1_PDIV_5 (4 << 2)
|
||||
#define DPLL_CFGCR1_PDIV_7 (8 << 2)
|
||||
#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
|
||||
#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
|
||||
#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
|
||||
#define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
|
||||
|
||||
#define _ICL_DPLL0_CFGCR0 0x164000
|
||||
#define _ICL_DPLL1_CFGCR0 0x164080
|
||||
#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
|
||||
_ICL_DPLL1_CFGCR0)
|
||||
#define DPLL_CFGCR0_HDMI_MODE (1 << 30)
|
||||
#define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
|
||||
#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
|
||||
#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
|
||||
#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
|
||||
#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
|
||||
#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
|
||||
|
||||
#define _ICL_DPLL0_CFGCR1 0x164004
|
||||
#define _ICL_DPLL1_CFGCR1 0x164084
|
||||
#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
|
||||
_ICL_DPLL1_CFGCR1)
|
||||
#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
|
||||
#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
|
||||
#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
|
||||
#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
|
||||
#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
|
||||
#define DPLL_CFGCR1_KDIV_MASK (7 << 6)
|
||||
#define DPLL_CFGCR1_KDIV_SHIFT (6)
|
||||
#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
|
||||
#define DPLL_CFGCR1_KDIV_1 (1 << 6)
|
||||
#define DPLL_CFGCR1_KDIV_2 (2 << 6)
|
||||
#define DPLL_CFGCR1_KDIV_3 (4 << 6)
|
||||
#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
|
||||
#define DPLL_CFGCR1_PDIV_SHIFT (2)
|
||||
#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
|
||||
#define DPLL_CFGCR1_PDIV_2 (1 << 2)
|
||||
#define DPLL_CFGCR1_PDIV_3 (2 << 2)
|
||||
#define DPLL_CFGCR1_PDIV_5 (4 << 2)
|
||||
#define DPLL_CFGCR1_PDIV_7 (8 << 2)
|
||||
#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
|
||||
#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
|
||||
#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
|
||||
|
||||
#define _TGL_DPLL0_CFGCR0 0x164284
|
||||
#define _TGL_DPLL1_CFGCR0 0x16428C
|
||||
|
|
@ -11049,8 +11020,8 @@ enum skl_power_gate {
|
|||
#define BXT_DE_PLL_LOCK (1 << 30)
|
||||
#define BXT_DE_PLL_FREQ_REQ (1 << 23)
|
||||
#define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22)
|
||||
#define CNL_CDCLK_PLL_RATIO(x) (x)
|
||||
#define CNL_CDCLK_PLL_RATIO_MASK 0xff
|
||||
#define ICL_CDCLK_PLL_RATIO(x) (x)
|
||||
#define ICL_CDCLK_PLL_RATIO_MASK 0xff
|
||||
|
||||
/* GEN9 DC */
|
||||
#define DC_STATE_EN _MMIO(0x45504)
|
||||
|
|
@ -11105,6 +11076,7 @@ enum skl_power_gate {
|
|||
#define SKL_MEMORY_FREQ_MULTIPLIER_HZ 266666666
|
||||
#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
|
||||
#define SKL_REQ_DATA_MASK (0xF << 0)
|
||||
#define DG1_GEAR_TYPE REG_BIT(16)
|
||||
|
||||
#define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
|
||||
#define SKL_DRAM_DDR_TYPE_MASK (0x3 << 0)
|
||||
|
|
@ -11127,18 +11099,29 @@ enum skl_power_gate {
|
|||
#define SKL_DRAM_RANK_1 (0x0 << 10)
|
||||
#define SKL_DRAM_RANK_2 (0x1 << 10)
|
||||
#define SKL_DRAM_RANK_MASK (0x1 << 10)
|
||||
#define CNL_DRAM_SIZE_MASK 0x7F
|
||||
#define CNL_DRAM_WIDTH_MASK (0x3 << 7)
|
||||
#define CNL_DRAM_WIDTH_SHIFT 7
|
||||
#define CNL_DRAM_WIDTH_X8 (0x0 << 7)
|
||||
#define CNL_DRAM_WIDTH_X16 (0x1 << 7)
|
||||
#define CNL_DRAM_WIDTH_X32 (0x2 << 7)
|
||||
#define CNL_DRAM_RANK_MASK (0x3 << 9)
|
||||
#define CNL_DRAM_RANK_SHIFT 9
|
||||
#define CNL_DRAM_RANK_1 (0x0 << 9)
|
||||
#define CNL_DRAM_RANK_2 (0x1 << 9)
|
||||
#define CNL_DRAM_RANK_3 (0x2 << 9)
|
||||
#define CNL_DRAM_RANK_4 (0x3 << 9)
|
||||
#define ICL_DRAM_SIZE_MASK 0x7F
|
||||
#define ICL_DRAM_WIDTH_MASK (0x3 << 7)
|
||||
#define ICL_DRAM_WIDTH_SHIFT 7
|
||||
#define ICL_DRAM_WIDTH_X8 (0x0 << 7)
|
||||
#define ICL_DRAM_WIDTH_X16 (0x1 << 7)
|
||||
#define ICL_DRAM_WIDTH_X32 (0x2 << 7)
|
||||
#define ICL_DRAM_RANK_MASK (0x3 << 9)
|
||||
#define ICL_DRAM_RANK_SHIFT 9
|
||||
#define ICL_DRAM_RANK_1 (0x0 << 9)
|
||||
#define ICL_DRAM_RANK_2 (0x1 << 9)
|
||||
#define ICL_DRAM_RANK_3 (0x2 << 9)
|
||||
#define ICL_DRAM_RANK_4 (0x3 << 9)
|
||||
|
||||
#define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
|
||||
#define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2)
|
||||
#define DG1_QCLK_REFERENCE REG_BIT(10)
|
||||
|
||||
#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)
|
||||
#define DG1_DRAM_T_RDPRE_MASK REG_GENMASK(16, 11)
|
||||
#define DG1_DRAM_T_RP_MASK REG_GENMASK(6, 0)
|
||||
#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4004)
|
||||
#define DG1_DRAM_T_RCD_MASK REG_GENMASK(15, 9)
|
||||
#define DG1_DRAM_T_RAS_MASK REG_GENMASK(8, 1)
|
||||
|
||||
/*
|
||||
* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
|
||||
|
|
@ -12389,6 +12372,7 @@ enum skl_power_gate {
|
|||
_ICL_PHY_MISC_B)
|
||||
#define ICL_PHY_MISC_MUX_DDID (1 << 28)
|
||||
#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
|
||||
#define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20)
|
||||
|
||||
/* Icelake Display Stream Compression Registers */
|
||||
#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
|
||||
|
|
|
|||
|
|
@ -59,7 +59,6 @@ static const char * const platform_names[] = {
|
|||
PLATFORM_NAME(GEMINILAKE),
|
||||
PLATFORM_NAME(COFFEELAKE),
|
||||
PLATFORM_NAME(COMETLAKE),
|
||||
PLATFORM_NAME(CANNONLAKE),
|
||||
PLATFORM_NAME(ICELAKE),
|
||||
PLATFORM_NAME(ELKHARTLAKE),
|
||||
PLATFORM_NAME(JASPERLAKE),
|
||||
|
|
@ -175,7 +174,6 @@ static const u16 subplatform_ulx_ids[] = {
|
|||
};
|
||||
|
||||
static const u16 subplatform_portf_ids[] = {
|
||||
INTEL_CNL_PORT_F_IDS(0),
|
||||
INTEL_ICL_PORT_F_IDS(0),
|
||||
};
|
||||
|
||||
|
|
@ -263,14 +261,14 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
|
|||
struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
|
||||
enum pipe pipe;
|
||||
|
||||
/* Wa_14011765242: adl-s A0 */
|
||||
if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
|
||||
/* Wa_14011765242: adl-s A0,A1 */
|
||||
if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
|
||||
for_each_pipe(dev_priv, pipe)
|
||||
runtime->num_scalers[pipe] = 0;
|
||||
else if (GRAPHICS_VER(dev_priv) >= 10) {
|
||||
else if (DISPLAY_VER(dev_priv) >= 11) {
|
||||
for_each_pipe(dev_priv, pipe)
|
||||
runtime->num_scalers[pipe] = 2;
|
||||
} else if (GRAPHICS_VER(dev_priv) == 9) {
|
||||
} else if (DISPLAY_VER(dev_priv) >= 9) {
|
||||
runtime->num_scalers[PIPE_A] = 2;
|
||||
runtime->num_scalers[PIPE_B] = 2;
|
||||
runtime->num_scalers[PIPE_C] = 1;
|
||||
|
|
@ -281,10 +279,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
|
|||
if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
|
||||
for_each_pipe(dev_priv, pipe)
|
||||
runtime->num_sprites[pipe] = 4;
|
||||
else if (GRAPHICS_VER(dev_priv) >= 11)
|
||||
else if (DISPLAY_VER(dev_priv) >= 11)
|
||||
for_each_pipe(dev_priv, pipe)
|
||||
runtime->num_sprites[pipe] = 6;
|
||||
else if (GRAPHICS_VER(dev_priv) == 10 || IS_GEMINILAKE(dev_priv))
|
||||
else if (DISPLAY_VER(dev_priv) == 10)
|
||||
for_each_pipe(dev_priv, pipe)
|
||||
runtime->num_sprites[pipe] = 3;
|
||||
else if (IS_BROXTON(dev_priv)) {
|
||||
|
|
@ -303,7 +301,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
|
|||
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
|
||||
for_each_pipe(dev_priv, pipe)
|
||||
runtime->num_sprites[pipe] = 2;
|
||||
} else if (GRAPHICS_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
|
||||
} else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
|
||||
for_each_pipe(dev_priv, pipe)
|
||||
runtime->num_sprites[pipe] = 1;
|
||||
}
|
||||
|
|
@ -335,7 +333,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
|
|||
info->pipe_mask &= ~BIT(PIPE_C);
|
||||
info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
|
||||
}
|
||||
} else if (HAS_DISPLAY(dev_priv) && GRAPHICS_VER(dev_priv) >= 9) {
|
||||
} else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
|
||||
u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
|
||||
|
||||
if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
|
||||
|
|
@ -350,7 +348,8 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
|
|||
info->pipe_mask &= ~BIT(PIPE_C);
|
||||
info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
|
||||
}
|
||||
if (GRAPHICS_VER(dev_priv) >= 12 &&
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 12 &&
|
||||
(dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
|
||||
info->pipe_mask &= ~BIT(PIPE_D);
|
||||
info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
|
||||
|
|
@ -362,11 +361,11 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
|
|||
if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
|
||||
info->display.has_fbc = 0;
|
||||
|
||||
if (GRAPHICS_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
|
||||
if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
|
||||
info->display.has_dmc = 0;
|
||||
|
||||
if (GRAPHICS_VER(dev_priv) >= 10 &&
|
||||
(dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
|
||||
if (DISPLAY_VER(dev_priv) >= 10 &&
|
||||
(dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
|
||||
info->display.has_dsc = 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -76,8 +76,6 @@ enum intel_platform {
|
|||
INTEL_GEMINILAKE,
|
||||
INTEL_COFFEELAKE,
|
||||
INTEL_COMETLAKE,
|
||||
/* gen10 */
|
||||
INTEL_CANNONLAKE,
|
||||
/* gen11 */
|
||||
INTEL_ICELAKE,
|
||||
INTEL_ELKHARTLAKE,
|
||||
|
|
@ -105,7 +103,7 @@ enum intel_platform {
|
|||
#define INTEL_SUBPLATFORM_ULT (0)
|
||||
#define INTEL_SUBPLATFORM_ULX (1)
|
||||
|
||||
/* CNL/ICL */
|
||||
/* ICL */
|
||||
#define INTEL_SUBPLATFORM_PORTF (0)
|
||||
|
||||
/* DG2 */
|
||||
|
|
@ -133,7 +131,6 @@ enum intel_ppgtt_type {
|
|||
func(has_llc); \
|
||||
func(has_logical_ring_contexts); \
|
||||
func(has_logical_ring_elsq); \
|
||||
func(has_master_unit_irq); \
|
||||
func(has_mslices); \
|
||||
func(has_pooled_eu); \
|
||||
func(has_rc6); \
|
||||
|
|
@ -148,6 +145,7 @@ enum intel_ppgtt_type {
|
|||
#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
|
||||
/* Keep in alphabetical order */ \
|
||||
func(cursor_needs_physical); \
|
||||
func(has_cdclk_crawl); \
|
||||
func(has_dmc); \
|
||||
func(has_ddi); \
|
||||
func(has_dp_mst); \
|
||||
|
|
@ -195,8 +193,6 @@ struct intel_device_info {
|
|||
|
||||
u8 abox_mask;
|
||||
|
||||
u8 has_cdclk_crawl; /* does support CDCLK crawling */
|
||||
|
||||
#define DEFINE_FLAG(name) u8 name:1
|
||||
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
|
||||
#undef DEFINE_FLAG
|
||||
|
|
|
|||
|
|
@ -77,21 +77,21 @@ static int skl_get_dimm_ranks(u16 val)
|
|||
}
|
||||
|
||||
/* Returns total Gb for the whole DIMM */
|
||||
static int cnl_get_dimm_size(u16 val)
|
||||
static int icl_get_dimm_size(u16 val)
|
||||
{
|
||||
return (val & CNL_DRAM_SIZE_MASK) * 8 / 2;
|
||||
return (val & ICL_DRAM_SIZE_MASK) * 8 / 2;
|
||||
}
|
||||
|
||||
static int cnl_get_dimm_width(u16 val)
|
||||
static int icl_get_dimm_width(u16 val)
|
||||
{
|
||||
if (cnl_get_dimm_size(val) == 0)
|
||||
if (icl_get_dimm_size(val) == 0)
|
||||
return 0;
|
||||
|
||||
switch (val & CNL_DRAM_WIDTH_MASK) {
|
||||
case CNL_DRAM_WIDTH_X8:
|
||||
case CNL_DRAM_WIDTH_X16:
|
||||
case CNL_DRAM_WIDTH_X32:
|
||||
val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
|
||||
switch (val & ICL_DRAM_WIDTH_MASK) {
|
||||
case ICL_DRAM_WIDTH_X8:
|
||||
case ICL_DRAM_WIDTH_X16:
|
||||
case ICL_DRAM_WIDTH_X32:
|
||||
val = (val & ICL_DRAM_WIDTH_MASK) >> ICL_DRAM_WIDTH_SHIFT;
|
||||
return 8 << val;
|
||||
default:
|
||||
MISSING_CASE(val);
|
||||
|
|
@ -99,12 +99,12 @@ static int cnl_get_dimm_width(u16 val)
|
|||
}
|
||||
}
|
||||
|
||||
static int cnl_get_dimm_ranks(u16 val)
|
||||
static int icl_get_dimm_ranks(u16 val)
|
||||
{
|
||||
if (cnl_get_dimm_size(val) == 0)
|
||||
if (icl_get_dimm_size(val) == 0)
|
||||
return 0;
|
||||
|
||||
val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
|
||||
val = (val & ICL_DRAM_RANK_MASK) >> ICL_DRAM_RANK_SHIFT;
|
||||
|
||||
return val + 1;
|
||||
}
|
||||
|
|
@ -121,10 +121,10 @@ skl_dram_get_dimm_info(struct drm_i915_private *i915,
|
|||
struct dram_dimm_info *dimm,
|
||||
int channel, char dimm_name, u16 val)
|
||||
{
|
||||
if (GRAPHICS_VER(i915) >= 10) {
|
||||
dimm->size = cnl_get_dimm_size(val);
|
||||
dimm->width = cnl_get_dimm_width(val);
|
||||
dimm->ranks = cnl_get_dimm_ranks(val);
|
||||
if (GRAPHICS_VER(i915) >= 11) {
|
||||
dimm->size = icl_get_dimm_size(val);
|
||||
dimm->width = icl_get_dimm_width(val);
|
||||
dimm->ranks = icl_get_dimm_ranks(val);
|
||||
} else {
|
||||
dimm->size = skl_get_dimm_size(val);
|
||||
dimm->width = skl_get_dimm_width(val);
|
||||
|
|
@ -468,6 +468,7 @@ static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv)
|
|||
|
||||
dram_info->num_channels = (val & 0xf0) >> 4;
|
||||
dram_info->num_qgv_points = (val & 0xf00) >> 8;
|
||||
dram_info->num_psf_gv_points = (val & 0x3000) >> 12;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -494,15 +495,15 @@ void intel_dram_detect(struct drm_i915_private *i915)
|
|||
struct dram_info *dram_info = &i915->dram_info;
|
||||
int ret;
|
||||
|
||||
if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915))
|
||||
return;
|
||||
|
||||
/*
|
||||
* Assume level 0 watermark latency adjustment is needed until proven
|
||||
* otherwise, this w/a is not needed by bxt/glk.
|
||||
*/
|
||||
dram_info->wm_lv_0_adjust_needed = !IS_GEN9_LP(i915);
|
||||
|
||||
if (GRAPHICS_VER(i915) < 9 || !HAS_DISPLAY(i915))
|
||||
return;
|
||||
|
||||
if (GRAPHICS_VER(i915) >= 12)
|
||||
ret = gen12_get_dram_info(i915);
|
||||
else if (GRAPHICS_VER(i915) >= 11)
|
||||
|
|
|
|||
|
|
@ -81,7 +81,6 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
|
|||
case INTEL_PCH_CNP_DEVICE_ID_TYPE:
|
||||
drm_dbg_kms(&dev_priv->drm, "Found Cannon Lake PCH (CNP)\n");
|
||||
drm_WARN_ON(&dev_priv->drm,
|
||||
!IS_CANNONLAKE(dev_priv) &&
|
||||
!IS_COFFEELAKE(dev_priv) &&
|
||||
!IS_COMETLAKE(dev_priv));
|
||||
return PCH_CNP;
|
||||
|
|
@ -89,7 +88,6 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
|
|||
drm_dbg_kms(&dev_priv->drm,
|
||||
"Found Cannon Lake LP PCH (CNP-LP)\n");
|
||||
drm_WARN_ON(&dev_priv->drm,
|
||||
!IS_CANNONLAKE(dev_priv) &&
|
||||
!IS_COFFEELAKE(dev_priv) &&
|
||||
!IS_COMETLAKE(dev_priv));
|
||||
return PCH_CNP;
|
||||
|
|
@ -171,8 +169,7 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv,
|
|||
id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
|
||||
else if (IS_ICELAKE(dev_priv))
|
||||
id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
|
||||
else if (IS_CANNONLAKE(dev_priv) ||
|
||||
IS_COFFEELAKE(dev_priv) ||
|
||||
else if (IS_COFFEELAKE(dev_priv) ||
|
||||
IS_COMETLAKE(dev_priv))
|
||||
id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
|
||||
else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv))
|
||||
|
|
@ -211,6 +208,9 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
|
|||
if (IS_DG1(dev_priv)) {
|
||||
dev_priv->pch_type = PCH_DG1;
|
||||
return;
|
||||
} else if (IS_DG2(dev_priv)) {
|
||||
dev_priv->pch_type = PCH_DG2;
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@ enum intel_pch {
|
|||
|
||||
/* Fake PCHs, functionality handled on the same PCI dev */
|
||||
PCH_DG1 = 1024,
|
||||
PCH_DG2,
|
||||
};
|
||||
|
||||
#define INTEL_PCH_DEVICE_ID_MASK 0xff80
|
||||
|
|
@ -62,6 +63,7 @@ enum intel_pch {
|
|||
|
||||
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
|
||||
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
|
||||
#define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
|
||||
#define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
|
||||
#define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
|
||||
#define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
|
||||
|
|
|
|||
|
|
@ -4584,6 +4584,117 @@ static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] =
|
|||
{}
|
||||
};
|
||||
|
||||
static const struct dbuf_slice_conf_entry dg2_allowed_dbufs[] = {
|
||||
{
|
||||
.active_pipes = BIT(PIPE_A),
|
||||
.dbuf_mask = {
|
||||
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
|
||||
},
|
||||
},
|
||||
{
|
||||
.active_pipes = BIT(PIPE_B),
|
||||
.dbuf_mask = {
|
||||
[PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
|
||||
},
|
||||
},
|
||||
{
|
||||
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
|
||||
.dbuf_mask = {
|
||||
[PIPE_A] = BIT(DBUF_S1),
|
||||
[PIPE_B] = BIT(DBUF_S2),
|
||||
},
|
||||
},
|
||||
{
|
||||
.active_pipes = BIT(PIPE_C),
|
||||
.dbuf_mask = {
|
||||
[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
|
||||
},
|
||||
},
|
||||
{
|
||||
.active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
|
||||
.dbuf_mask = {
|
||||
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
|
||||
[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
|
||||
},
|
||||
},
|
||||
{
|
||||
.active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
|
||||
.dbuf_mask = {
|
||||
[PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
|
||||
[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
|
||||
},
|
||||
},
|
||||
{
|
||||
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
|
||||
.dbuf_mask = {
|
||||
[PIPE_A] = BIT(DBUF_S1),
|
||||
[PIPE_B] = BIT(DBUF_S2),
|
||||
[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
|
||||
},
|
||||
},
|
||||
{
|
||||
.active_pipes = BIT(PIPE_D),
|
||||
.dbuf_mask = {
|
||||
[PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
|
||||
},
|
||||
},
|
||||
{
|
||||
.active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
|
||||
.dbuf_mask = {
|
||||
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
|
||||
[PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
|
||||
},
|
||||
},
|
||||
{
|
||||
.active_pipes = BIT(PIPE_B) | BIT(PIPE_D),
|
||||
.dbuf_mask = {
|
||||
[PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
|
||||
[PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
|
||||
},
|
||||
},
|
||||
{
|
||||
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
|
||||
.dbuf_mask = {
|
||||
[PIPE_A] = BIT(DBUF_S1),
|
||||
[PIPE_B] = BIT(DBUF_S2),
|
||||
[PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
|
||||
},
|
||||
},
|
||||
{
|
||||
.active_pipes = BIT(PIPE_C) | BIT(PIPE_D),
|
||||
.dbuf_mask = {
|
||||
[PIPE_C] = BIT(DBUF_S3),
|
||||
[PIPE_D] = BIT(DBUF_S4),
|
||||
},
|
||||
},
|
||||
{
|
||||
.active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
|
||||
.dbuf_mask = {
|
||||
[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
|
||||
[PIPE_C] = BIT(DBUF_S3),
|
||||
[PIPE_D] = BIT(DBUF_S4),
|
||||
},
|
||||
},
|
||||
{
|
||||
.active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
|
||||
.dbuf_mask = {
|
||||
[PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
|
||||
[PIPE_C] = BIT(DBUF_S3),
|
||||
[PIPE_D] = BIT(DBUF_S4),
|
||||
},
|
||||
},
|
||||
{
|
||||
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
|
||||
.dbuf_mask = {
|
||||
[PIPE_A] = BIT(DBUF_S1),
|
||||
[PIPE_B] = BIT(DBUF_S2),
|
||||
[PIPE_C] = BIT(DBUF_S3),
|
||||
[PIPE_D] = BIT(DBUF_S4),
|
||||
},
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct dbuf_slice_conf_entry adlp_allowed_dbufs[] = {
|
||||
{
|
||||
.active_pipes = BIT(PIPE_A),
|
||||
|
|
@ -4759,12 +4870,19 @@ static u32 adlp_compute_dbuf_slices(enum pipe pipe, u32 active_pipes)
|
|||
return compute_dbuf_slices(pipe, active_pipes, adlp_allowed_dbufs);
|
||||
}
|
||||
|
||||
static u32 dg2_compute_dbuf_slices(enum pipe pipe, u32 active_pipes)
|
||||
{
|
||||
return compute_dbuf_slices(pipe, active_pipes, dg2_allowed_dbufs);
|
||||
}
|
||||
|
||||
static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
enum pipe pipe = crtc->pipe;
|
||||
|
||||
if (IS_ALDERLAKE_P(dev_priv))
|
||||
if (IS_DG2(dev_priv))
|
||||
return dg2_compute_dbuf_slices(pipe, active_pipes);
|
||||
else if (IS_ALDERLAKE_P(dev_priv))
|
||||
return adlp_compute_dbuf_slices(pipe, active_pipes);
|
||||
else if (DISPLAY_VER(dev_priv) == 12)
|
||||
return tgl_compute_dbuf_slices(pipe, active_pipes);
|
||||
|
|
@ -7347,7 +7465,7 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
|
|||
|
||||
/*Wa_14010594013:icl, ehl */
|
||||
intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
|
||||
0, CNL_DELAY_PMRSP);
|
||||
0, ICL_DELAY_PMRSP);
|
||||
}
|
||||
|
||||
static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
|
||||
|
|
@ -7359,7 +7477,7 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
|
|||
ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
|
||||
|
||||
/* Wa_1409825376:tgl (pre-prod)*/
|
||||
if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1))
|
||||
if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
|
||||
intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
|
||||
TGL_VRH_GATING_DIS);
|
||||
|
||||
|
|
@ -7397,43 +7515,6 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
|
|||
CNP_PWM_CGE_GATING_DISABLE);
|
||||
}
|
||||
|
||||
static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
u32 val;
|
||||
cnp_init_clock_gating(dev_priv);
|
||||
|
||||
/* This is not an Wa. Enable for better image quality */
|
||||
intel_uncore_write(&dev_priv->uncore, _3D_CHICKEN3,
|
||||
_MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
|
||||
|
||||
/* WaEnableChickenDCPR:cnl */
|
||||
intel_uncore_write(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
|
||||
intel_uncore_read(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
|
||||
|
||||
/*
|
||||
* WaFbcWakeMemOn:cnl
|
||||
* Display WA #0859: cnl
|
||||
*/
|
||||
intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
|
||||
DISP_FBC_MEMORY_WAKE);
|
||||
|
||||
val = intel_uncore_read(&dev_priv->uncore, SLICE_UNIT_LEVEL_CLKGATE);
|
||||
/* ReadHitWriteOnlyDisable:cnl */
|
||||
val |= RCCUNIT_CLKGATE_DIS;
|
||||
intel_uncore_write(&dev_priv->uncore, SLICE_UNIT_LEVEL_CLKGATE, val);
|
||||
|
||||
/* Wa_2201832410:cnl */
|
||||
val = intel_uncore_read(&dev_priv->uncore, SUBSLICE_UNIT_LEVEL_CLKGATE);
|
||||
val |= GWUNIT_CLKGATE_DIS;
|
||||
intel_uncore_write(&dev_priv->uncore, SUBSLICE_UNIT_LEVEL_CLKGATE, val);
|
||||
|
||||
/* WaDisableVFclkgate:cnl */
|
||||
/* WaVFUnitClockGatingDisable:cnl */
|
||||
val = intel_uncore_read(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE);
|
||||
val |= VFUNIT_CLKGATE_DIS;
|
||||
intel_uncore_write(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE, val);
|
||||
}
|
||||
|
||||
static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
cnp_init_clock_gating(dev_priv);
|
||||
|
|
@ -7862,8 +7943,6 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
|
|||
dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
|
||||
else if (GRAPHICS_VER(dev_priv) == 11)
|
||||
dev_priv->display.init_clock_gating = icl_init_clock_gating;
|
||||
else if (IS_CANNONLAKE(dev_priv))
|
||||
dev_priv->display.init_clock_gating = cnl_init_clock_gating;
|
||||
else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
|
||||
dev_priv->display.init_clock_gating = cfl_init_clock_gating;
|
||||
else if (IS_SKYLAKE(dev_priv))
|
||||
|
|
|
|||
|
|
@ -556,17 +556,22 @@ out:
|
|||
#undef COND
|
||||
}
|
||||
|
||||
void intel_pcode_init(struct drm_i915_private *i915)
|
||||
int intel_pcode_init(struct drm_i915_private *i915)
|
||||
{
|
||||
int ret;
|
||||
int ret = 0;
|
||||
|
||||
if (!IS_DGFX(i915))
|
||||
return;
|
||||
return ret;
|
||||
|
||||
ret = skl_pcode_request(i915, DG1_PCODE_STATUS,
|
||||
DG1_UNCORE_GET_INIT_STATUS,
|
||||
DG1_UNCORE_INIT_STATUS_COMPLETE,
|
||||
DG1_UNCORE_INIT_STATUS_COMPLETE, 50);
|
||||
DG1_UNCORE_INIT_STATUS_COMPLETE, 180000);
|
||||
|
||||
drm_dbg(&i915->drm, "PCODE init status %d\n", ret);
|
||||
|
||||
if (ret)
|
||||
drm_err(&i915->drm, "Pcode did not report uncore initialization completion!\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -138,6 +138,6 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
|
|||
int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
|
||||
u32 reply_mask, u32 reply, int timeout_base_ms);
|
||||
|
||||
void intel_pcode_init(struct drm_i915_private *i915);
|
||||
int intel_pcode_init(struct drm_i915_private *i915);
|
||||
|
||||
#endif /* _INTEL_SIDEBAND_H */
|
||||
|
|
|
|||
|
|
@ -118,6 +118,7 @@ static const struct intel_step_info dg2_g10_revid_step_tbl[] = {
|
|||
static const struct intel_step_info dg2_g11_revid_step_tbl[] = {
|
||||
[0x0] = { .gt_step = STEP_A0, .display_step = STEP_B0 },
|
||||
[0x4] = { .gt_step = STEP_B0, .display_step = STEP_C0 },
|
||||
[0x5] = { .gt_step = STEP_B1, .display_step = STEP_C0 },
|
||||
};
|
||||
|
||||
void intel_step_init(struct drm_i915_private *i915)
|
||||
|
|
@ -210,3 +211,17 @@ void intel_step_init(struct drm_i915_private *i915)
|
|||
|
||||
RUNTIME_INFO(i915)->step = step;
|
||||
}
|
||||
|
||||
#define STEP_NAME_CASE(name) \
|
||||
case STEP_##name: \
|
||||
return #name;
|
||||
|
||||
const char *intel_step_name(enum intel_step step)
|
||||
{
|
||||
switch (step) {
|
||||
STEP_NAME_LIST(STEP_NAME_CASE);
|
||||
|
||||
default:
|
||||
return "**";
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -15,31 +15,39 @@ struct intel_step_info {
|
|||
u8 display_step;
|
||||
};
|
||||
|
||||
#define STEP_ENUM_VAL(name) STEP_##name,
|
||||
|
||||
#define STEP_NAME_LIST(func) \
|
||||
func(A0) \
|
||||
func(A1) \
|
||||
func(A2) \
|
||||
func(B0) \
|
||||
func(B1) \
|
||||
func(B2) \
|
||||
func(C0) \
|
||||
func(C1) \
|
||||
func(D0) \
|
||||
func(D1) \
|
||||
func(E0) \
|
||||
func(F0) \
|
||||
func(G0) \
|
||||
func(H0) \
|
||||
func(I0) \
|
||||
func(I1) \
|
||||
func(J0)
|
||||
|
||||
/*
|
||||
* Symbolic steppings that do not match the hardware. These are valid both as gt
|
||||
* and display steppings as symbolic names.
|
||||
*/
|
||||
enum intel_step {
|
||||
STEP_NONE = 0,
|
||||
STEP_A0,
|
||||
STEP_A1,
|
||||
STEP_A2,
|
||||
STEP_B0,
|
||||
STEP_B1,
|
||||
STEP_C0,
|
||||
STEP_D0,
|
||||
STEP_D1,
|
||||
STEP_E0,
|
||||
STEP_F0,
|
||||
STEP_G0,
|
||||
STEP_H0,
|
||||
STEP_I0,
|
||||
STEP_I1,
|
||||
STEP_J0,
|
||||
STEP_NAME_LIST(STEP_ENUM_VAL)
|
||||
STEP_FUTURE,
|
||||
STEP_FOREVER,
|
||||
};
|
||||
|
||||
void intel_step_init(struct drm_i915_private *i915);
|
||||
const char *intel_step_name(enum intel_step step);
|
||||
|
||||
#endif /* __INTEL_STEP_H__ */
|
||||
|
|
|
|||
|
|
@ -56,8 +56,8 @@
|
|||
|
||||
/* 24KB at the end of WOPCM is reserved for RC6 CTX on BXT. */
|
||||
#define BXT_WOPCM_RC6_CTX_RESERVED (SZ_16K + SZ_8K)
|
||||
/* 36KB WOPCM reserved at the end of WOPCM on CNL. */
|
||||
#define CNL_WOPCM_HW_CTX_RESERVED (SZ_32K + SZ_4K)
|
||||
/* 36KB WOPCM reserved at the end of WOPCM on ICL. */
|
||||
#define ICL_WOPCM_HW_CTX_RESERVED (SZ_32K + SZ_4K)
|
||||
|
||||
/* 128KB from GUC_WOPCM_RESERVED is reserved for FW on Gen9. */
|
||||
#define GEN9_GUC_FW_RESERVED SZ_128K
|
||||
|
|
@ -93,8 +93,8 @@ static u32 context_reserved_size(struct drm_i915_private *i915)
|
|||
{
|
||||
if (IS_GEN9_LP(i915))
|
||||
return BXT_WOPCM_RC6_CTX_RESERVED;
|
||||
else if (GRAPHICS_VER(i915) >= 10)
|
||||
return CNL_WOPCM_HW_CTX_RESERVED;
|
||||
else if (GRAPHICS_VER(i915) >= 11)
|
||||
return ICL_WOPCM_HW_CTX_RESERVED;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -126,7 +126,7 @@ static bool gen9_check_huc_fw_fits(struct drm_i915_private *i915,
|
|||
u32 guc_wopcm_size, u32 huc_fw_size)
|
||||
{
|
||||
/*
|
||||
* On Gen9 & CNL A0, hardware requires the total available GuC WOPCM
|
||||
* On Gen9, hardware requires the total available GuC WOPCM
|
||||
* size to be larger than or equal to HuC firmware size. Otherwise,
|
||||
* firmware uploading would fail.
|
||||
*/
|
||||
|
|
|
|||
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