ASoC: fsl: Add S/PDIF CPU DAI driver
This patch implements a device-tree-only CPU DAI driver for Freescale S/PDIF controller that supports stereo playback and record feature. Signed-off-by: Nicolin Chen <b42378@freescale.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org>
This commit is contained in:
Nicolin Chen
Mark Brown
Родитель
0783e64898
Коммит
a2388a498a
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Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
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The Freescale S/PDIF audio block is a stereo transceiver that allows the
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processor to receive and transmit digital audio via an coaxial cable or
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a fibre cable.
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Required properties:
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- compatible : Compatible list, must contain "fsl,imx35-spdif".
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- reg : Offset and length of the register set for the device.
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- interrupts : Contains the spdif interrupt.
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- dmas : Generic dma devicetree binding as described in
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Documentation/devicetree/bindings/dma/dma.txt.
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- dma-names : Two dmas have to be defined, "tx" and "rx".
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- clocks : Contains an entry for each entry in clock-names.
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- clock-names : Includes the following entries:
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"core" The core clock of spdif controller
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"rxtx<0-7>" Clock source list for tx and rx clock.
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This clock list should be identical to
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the source list connecting to the spdif
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clock mux in "SPDIF Transceiver Clock
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Diagram" of SoC reference manual. It
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can also be referred to TxClk_Source
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bit of register SPDIF_STC.
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Example:
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spdif: spdif@02004000 {
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compatible = "fsl,imx35-spdif";
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reg = <0x02004000 0x4000>;
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interrupts = <0 52 0x04>;
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dmas = <&sdma 14 18 0>,
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<&sdma 15 18 0>;
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dma-names = "rx", "tx";
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clocks = <&clks 197>, <&clks 3>,
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<&clks 197>, <&clks 107>,
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<&clks 0>, <&clks 118>,
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<&clks 62>, <&clks 139>,
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<&clks 0>;
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clock-names = "core", "rxtx0",
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"rxtx1", "rxtx2",
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"rxtx3", "rxtx4",
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"rxtx5", "rxtx6",
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"rxtx7";
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status = "okay";
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};
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@ -1,6 +1,9 @@
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config SND_SOC_FSL_SSI
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tristate
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config SND_SOC_FSL_SPDIF
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tristate
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config SND_SOC_FSL_UTILS
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tristate
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@ -12,9 +12,11 @@ obj-$(CONFIG_SND_SOC_P1022_RDK) += snd-soc-p1022-rdk.o
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# Freescale PowerPC SSI/DMA Platform Support
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snd-soc-fsl-ssi-objs := fsl_ssi.o
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snd-soc-fsl-spdif-objs := fsl_spdif.o
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snd-soc-fsl-utils-objs := fsl_utils.o
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snd-soc-fsl-dma-objs := fsl_dma.o
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obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
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obj-$(CONFIG_SND_SOC_FSL_SPDIF) += snd-soc-fsl-spdif.o
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obj-$(CONFIG_SND_SOC_FSL_UTILS) += snd-soc-fsl-utils.o
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obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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/*
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* fsl_spdif.h - ALSA S/PDIF interface for the Freescale i.MX SoC
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*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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*
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* Author: Nicolin Chen <b42378@freescale.com>
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*
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* Based on fsl_ssi.h
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* Author: Timur Tabi <timur@freescale.com>
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* Copyright 2007-2008 Freescale Semiconductor, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#ifndef _FSL_SPDIF_DAI_H
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#define _FSL_SPDIF_DAI_H
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/* S/PDIF Register Map */
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#define REG_SPDIF_SCR 0x0 /* SPDIF Configuration Register */
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#define REG_SPDIF_SRCD 0x4 /* CDText Control Register */
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#define REG_SPDIF_SRPC 0x8 /* PhaseConfig Register */
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#define REG_SPDIF_SIE 0xc /* InterruptEn Register */
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#define REG_SPDIF_SIS 0x10 /* InterruptStat Register */
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#define REG_SPDIF_SIC 0x10 /* InterruptClear Register */
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#define REG_SPDIF_SRL 0x14 /* SPDIFRxLeft Register */
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#define REG_SPDIF_SRR 0x18 /* SPDIFRxRight Register */
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#define REG_SPDIF_SRCSH 0x1c /* SPDIFRxCChannel_h Register */
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#define REG_SPDIF_SRCSL 0x20 /* SPDIFRxCChannel_l Register */
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#define REG_SPDIF_SRU 0x24 /* UchannelRx Register */
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#define REG_SPDIF_SRQ 0x28 /* QchannelRx Register */
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#define REG_SPDIF_STL 0x2C /* SPDIFTxLeft Register */
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#define REG_SPDIF_STR 0x30 /* SPDIFTxRight Register */
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#define REG_SPDIF_STCSCH 0x34 /* SPDIFTxCChannelCons_h Register */
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#define REG_SPDIF_STCSCL 0x38 /* SPDIFTxCChannelCons_l Register */
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#define REG_SPDIF_SRFM 0x44 /* FreqMeas Register */
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#define REG_SPDIF_STC 0x50 /* SPDIFTxClk Register */
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/* SPDIF Configuration register */
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#define SCR_RXFIFO_CTL_OFFSET 23
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#define SCR_RXFIFO_CTL_MASK (1 << SCR_RXFIFO_CTL_OFFSET)
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#define SCR_RXFIFO_CTL_ZERO (1 << SCR_RXFIFO_CTL_OFFSET)
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#define SCR_RXFIFO_OFF_OFFSET 22
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#define SCR_RXFIFO_OFF_MASK (1 << SCR_RXFIFO_OFF_OFFSET)
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#define SCR_RXFIFO_OFF (1 << SCR_RXFIFO_OFF_OFFSET)
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#define SCR_RXFIFO_RST_OFFSET 21
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#define SCR_RXFIFO_RST_MASK (1 << SCR_RXFIFO_RST_OFFSET)
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#define SCR_RXFIFO_RST (1 << SCR_RXFIFO_RST_OFFSET)
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#define SCR_RXFIFO_FSEL_OFFSET 19
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#define SCR_RXFIFO_FSEL_MASK (0x3 << SCR_RXFIFO_FSEL_OFFSET)
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#define SCR_RXFIFO_FSEL_IF0 (0x0 << SCR_RXFIFO_FSEL_OFFSET)
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#define SCR_RXFIFO_FSEL_IF4 (0x1 << SCR_RXFIFO_FSEL_OFFSET)
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#define SCR_RXFIFO_FSEL_IF8 (0x2 << SCR_RXFIFO_FSEL_OFFSET)
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#define SCR_RXFIFO_FSEL_IF12 (0x3 << SCR_RXFIFO_FSEL_OFFSET)
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#define SCR_RXFIFO_AUTOSYNC_OFFSET 18
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#define SCR_RXFIFO_AUTOSYNC_MASK (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
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#define SCR_RXFIFO_AUTOSYNC (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
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#define SCR_TXFIFO_AUTOSYNC_OFFSET 17
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#define SCR_TXFIFO_AUTOSYNC_MASK (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
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#define SCR_TXFIFO_AUTOSYNC (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
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#define SCR_TXFIFO_FSEL_OFFSET 15
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#define SCR_TXFIFO_FSEL_MASK (0x3 << SCR_TXFIFO_FSEL_OFFSET)
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#define SCR_TXFIFO_FSEL_IF0 (0x0 << SCR_TXFIFO_FSEL_OFFSET)
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#define SCR_TXFIFO_FSEL_IF4 (0x1 << SCR_TXFIFO_FSEL_OFFSET)
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#define SCR_TXFIFO_FSEL_IF8 (0x2 << SCR_TXFIFO_FSEL_OFFSET)
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#define SCR_TXFIFO_FSEL_IF12 (0x3 << SCR_TXFIFO_FSEL_OFFSET)
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#define SCR_LOW_POWER (1 << 13)
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#define SCR_SOFT_RESET (1 << 12)
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#define SCR_TXFIFO_CTRL_OFFSET 10
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#define SCR_TXFIFO_CTRL_MASK (0x3 << SCR_TXFIFO_CTRL_OFFSET)
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#define SCR_TXFIFO_CTRL_ZERO (0x0 << SCR_TXFIFO_CTRL_OFFSET)
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#define SCR_TXFIFO_CTRL_NORMAL (0x1 << SCR_TXFIFO_CTRL_OFFSET)
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#define SCR_TXFIFO_CTRL_ONESAMPLE (0x2 << SCR_TXFIFO_CTRL_OFFSET)
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#define SCR_DMA_RX_EN_OFFSET 9
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#define SCR_DMA_RX_EN_MASK (1 << SCR_DMA_RX_EN_OFFSET)
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#define SCR_DMA_RX_EN (1 << SCR_DMA_RX_EN_OFFSET)
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#define SCR_DMA_TX_EN_OFFSET 8
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#define SCR_DMA_TX_EN_MASK (1 << SCR_DMA_TX_EN_OFFSET)
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#define SCR_DMA_TX_EN (1 << SCR_DMA_TX_EN_OFFSET)
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#define SCR_VAL_OFFSET 5
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#define SCR_VAL_MASK (1 << SCR_VAL_OFFSET)
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#define SCR_VAL_CLEAR (1 << SCR_VAL_OFFSET)
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#define SCR_TXSEL_OFFSET 2
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#define SCR_TXSEL_MASK (0x7 << SCR_TXSEL_OFFSET)
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#define SCR_TXSEL_OFF (0 << SCR_TXSEL_OFFSET)
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#define SCR_TXSEL_RX (1 << SCR_TXSEL_OFFSET)
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#define SCR_TXSEL_NORMAL (0x5 << SCR_TXSEL_OFFSET)
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#define SCR_USRC_SEL_OFFSET 0x0
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#define SCR_USRC_SEL_MASK (0x3 << SCR_USRC_SEL_OFFSET)
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#define SCR_USRC_SEL_NONE (0x0 << SCR_USRC_SEL_OFFSET)
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#define SCR_USRC_SEL_RECV (0x1 << SCR_USRC_SEL_OFFSET)
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#define SCR_USRC_SEL_CHIP (0x3 << SCR_USRC_SEL_OFFSET)
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/* SPDIF CDText control */
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#define SRCD_CD_USER_OFFSET 1
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#define SRCD_CD_USER (1 << SRCD_CD_USER_OFFSET)
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/* SPDIF Phase Configuration register */
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#define SRPC_DPLL_LOCKED (1 << 6)
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#define SRPC_CLKSRC_SEL_OFFSET 7
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#define SRPC_CLKSRC_SEL_MASK (0xf << SRPC_CLKSRC_SEL_OFFSET)
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#define SRPC_CLKSRC_SEL_SET(x) ((x << SRPC_CLKSRC_SEL_OFFSET) & SRPC_CLKSRC_SEL_MASK)
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#define SRPC_CLKSRC_SEL_LOCKED_OFFSET1 5
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#define SRPC_CLKSRC_SEL_LOCKED_OFFSET2 2
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#define SRPC_GAINSEL_OFFSET 3
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#define SRPC_GAINSEL_MASK (0x7 << SRPC_GAINSEL_OFFSET)
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#define SRPC_GAINSEL_SET(x) ((x << SRPC_GAINSEL_OFFSET) & SRPC_GAINSEL_MASK)
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#define SRPC_CLKSRC_MAX 16
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enum spdif_gainsel {
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GAINSEL_MULTI_24 = 0,
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GAINSEL_MULTI_16,
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GAINSEL_MULTI_12,
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GAINSEL_MULTI_8,
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GAINSEL_MULTI_6,
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GAINSEL_MULTI_4,
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GAINSEL_MULTI_3,
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};
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#define GAINSEL_MULTI_MAX (GAINSEL_MULTI_3 + 1)
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#define SPDIF_DEFAULT_GAINSEL GAINSEL_MULTI_8
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/* SPDIF interrupt mask define */
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#define INT_DPLL_LOCKED (1 << 20)
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#define INT_TXFIFO_UNOV (1 << 19)
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#define INT_TXFIFO_RESYNC (1 << 18)
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#define INT_CNEW (1 << 17)
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#define INT_VAL_NOGOOD (1 << 16)
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#define INT_SYM_ERR (1 << 15)
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#define INT_BIT_ERR (1 << 14)
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#define INT_URX_FUL (1 << 10)
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#define INT_URX_OV (1 << 9)
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#define INT_QRX_FUL (1 << 8)
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#define INT_QRX_OV (1 << 7)
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#define INT_UQ_SYNC (1 << 6)
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#define INT_UQ_ERR (1 << 5)
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#define INT_RXFIFO_UNOV (1 << 4)
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#define INT_RXFIFO_RESYNC (1 << 3)
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#define INT_LOSS_LOCK (1 << 2)
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#define INT_TX_EM (1 << 1)
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#define INT_RXFIFO_FUL (1 << 0)
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/* SPDIF Clock register */
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#define STC_SYSCLK_DIV_OFFSET 11
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#define STC_SYSCLK_DIV_MASK (0x1ff << STC_TXCLK_SRC_OFFSET)
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#define STC_SYSCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) & STC_SYSCLK_DIV_MASK)
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#define STC_TXCLK_SRC_OFFSET 8
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#define STC_TXCLK_SRC_MASK (0x7 << STC_TXCLK_SRC_OFFSET)
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#define STC_TXCLK_SRC_SET(x) ((x << STC_TXCLK_SRC_OFFSET) & STC_TXCLK_SRC_MASK)
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#define STC_TXCLK_ALL_EN_OFFSET 7
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#define STC_TXCLK_ALL_EN_MASK (1 << STC_TXCLK_ALL_EN_OFFSET)
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#define STC_TXCLK_ALL_EN (1 << STC_TXCLK_ALL_EN_OFFSET)
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#define STC_TXCLK_DIV_OFFSET 0
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#define STC_TXCLK_DIV_MASK (0x7ff << STC_TXCLK_DIV_OFFSET)
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#define STC_TXCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) & STC_TXCLK_DIV_MASK)
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#define STC_TXCLK_SRC_MAX 8
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/* SPDIF tx rate */
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enum spdif_txrate {
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SPDIF_TXRATE_32000 = 0,
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SPDIF_TXRATE_44100,
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SPDIF_TXRATE_48000,
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};
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#define SPDIF_TXRATE_MAX (SPDIF_TXRATE_48000 + 1)
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#define SPDIF_CSTATUS_BYTE 6
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#define SPDIF_UBITS_SIZE 96
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#define SPDIF_QSUB_SIZE (SPDIF_UBITS_SIZE / 8)
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#define FSL_SPDIF_RATES_PLAYBACK (SNDRV_PCM_RATE_32000 | \
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SNDRV_PCM_RATE_44100 | \
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SNDRV_PCM_RATE_48000)
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#define FSL_SPDIF_RATES_CAPTURE (SNDRV_PCM_RATE_16000 | \
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SNDRV_PCM_RATE_32000 | \
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SNDRV_PCM_RATE_44100 | \
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SNDRV_PCM_RATE_48000 | \
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SNDRV_PCM_RATE_64000 | \
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SNDRV_PCM_RATE_96000)
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#define FSL_SPDIF_FORMATS_PLAYBACK (SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S20_3LE | \
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SNDRV_PCM_FMTBIT_S24_LE)
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#define FSL_SPDIF_FORMATS_CAPTURE (SNDRV_PCM_FMTBIT_S24_LE)
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#endif /* _FSL_SPDIF_DAI_H */
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