clk: tegra: Add flags to tegra_clk_periph()
We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag, most notably mselect, which is a bridge between AXI and most peripherals. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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c1d1939c51
Коммит
a26a029893
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@ -173,14 +173,15 @@ const struct clk_ops tegra_clk_periph_nodiv_ops = {
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static struct clk *_tegra_clk_register_periph(const char *name,
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const char **parent_names, int num_parents,
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struct tegra_clk_periph *periph,
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void __iomem *clk_base, u32 offset, bool div)
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void __iomem *clk_base, u32 offset, bool div,
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unsigned long flags)
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{
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struct clk *clk;
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struct clk_init_data init;
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init.name = name;
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init.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops;
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init.flags = div ? 0 : CLK_SET_RATE_PARENT;
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init.flags = flags;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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@ -205,10 +206,10 @@ static struct clk *_tegra_clk_register_periph(const char *name,
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struct clk *tegra_clk_register_periph(const char *name,
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const char **parent_names, int num_parents,
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struct tegra_clk_periph *periph, void __iomem *clk_base,
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u32 offset)
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u32 offset, unsigned long flags)
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{
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return _tegra_clk_register_periph(name, parent_names, num_parents,
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periph, clk_base, offset, true);
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periph, clk_base, offset, true, flags);
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}
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struct clk *tegra_clk_register_periph_nodiv(const char *name,
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@ -217,5 +218,5 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
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u32 offset)
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{
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return _tegra_clk_register_periph(name, parent_names, num_parents,
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periph, clk_base, offset, false);
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periph, clk_base, offset, false, CLK_SET_RATE_PARENT);
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}
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@ -1019,7 +1019,7 @@ static void __init tegra20_periph_clk_init(void)
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data = &tegra_periph_clk_list[i];
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clk = tegra_clk_register_periph(data->name, data->parent_names,
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data->num_parents, &data->periph,
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clk_base, data->offset);
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clk_base, data->offset, data->flags);
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clk_register_clkdev(clk, data->con_id, data->dev_id);
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clks[data->clk_id] = clk;
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}
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@ -1668,7 +1668,7 @@ static void __init tegra30_periph_clk_init(void)
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data = &tegra_periph_clk_list[i];
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clk = tegra_clk_register_periph(data->name, data->parent_names,
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data->num_parents, &data->periph,
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clk_base, data->offset);
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clk_base, data->offset, data->flags);
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clk_register_clkdev(clk, data->con_id, data->dev_id);
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clks[data->clk_id] = clk;
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}
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@ -417,7 +417,7 @@ extern const struct clk_ops tegra_clk_periph_ops;
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struct clk *tegra_clk_register_periph(const char *name,
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const char **parent_names, int num_parents,
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struct tegra_clk_periph *periph, void __iomem *clk_base,
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u32 offset);
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u32 offset, unsigned long flags);
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struct clk *tegra_clk_register_periph_nodiv(const char *name,
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const char **parent_names, int num_parents,
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struct tegra_clk_periph *periph, void __iomem *clk_base,
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@ -460,12 +460,14 @@ struct tegra_periph_init_data {
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u32 offset;
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const char *con_id;
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const char *dev_id;
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unsigned long flags;
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};
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#define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
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_mux_shift, _mux_mask, _mux_flags, _div_shift, \
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_div_width, _div_frac_width, _div_flags, _regs, \
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_clk_num, _enb_refcnt, _gate_flags, _clk_id, _table) \
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_clk_num, _enb_refcnt, _gate_flags, _clk_id, _table,\
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_flags) \
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{ \
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.name = _name, \
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.clk_id = _clk_id, \
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@ -480,6 +482,7 @@ struct tegra_periph_init_data {
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.offset = _offset, \
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.con_id = _con_id, \
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.dev_id = _dev_id, \
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.flags = _flags \
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}
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#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\
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@ -490,7 +493,7 @@ struct tegra_periph_init_data {
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_mux_shift, BIT(_mux_width) - 1, _mux_flags, \
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_div_shift, _div_width, _div_frac_width, _div_flags, \
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_regs, _clk_num, _enb_refcnt, _gate_flags, _clk_id,\
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NULL)
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NULL, 0)
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/**
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* struct clk_super_mux - super clock
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