ARM: dts: rockchip: Add rk3288 vop and display-subsystem
Add devicetree nodes for rk3288 VOP (Video Output Processors), and the top level display-subsystem root node. Later patches add endpoints (eDP, HDMI, LVDS, etc) that attach to the VOPs' output ports. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Mark yao <mark.yao@rock-chips.com> Reviewed-by: Stephane Marchesin <marcheu@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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@ -149,6 +149,11 @@
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clock-frequency = <24000000>;
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};
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display-subsystem {
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compatible = "rockchip,display-subsystem";
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ports = <&vopl_out>, <&vopb_out>;
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};
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sdmmc: dwmmc@ff0c0000 {
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compatible = "rockchip,rk3288-dw-mshc";
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clock-freq-min-max = <400000 150000000>;
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@ -566,6 +571,23 @@
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status = "disabled";
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};
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vopb: vop@ff930000 {
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compatible = "rockchip,rk3288-vop";
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reg = <0xff930000 0x19c>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
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clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
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resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
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reset-names = "axi", "ahb", "dclk";
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iommus = <&vopb_mmu>;
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status = "disabled";
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vopb_out: port {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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vopb_mmu: iommu@ff930300 {
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compatible = "rockchip,iommu";
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reg = <0xff930300 0x100>;
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@ -575,6 +597,23 @@
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status = "disabled";
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};
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vopl: vop@ff940000 {
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compatible = "rockchip,rk3288-vop";
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reg = <0xff940000 0x19c>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
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clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
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resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
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reset-names = "axi", "ahb", "dclk";
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iommus = <&vopl_mmu>;
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status = "disabled";
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vopl_out: port {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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vopl_mmu: iommu@ff940300 {
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compatible = "rockchip,iommu";
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reg = <0xff940300 0x100>;
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