ARM: __io abuse cleanup
Several platforms incorrectly use __io() for casting to 'void __iomem *'. This converts all of those uses to use the common IOMEM macro. Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Anton Vorontsov <cbouatmailru@gmail.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: linux-sh@vger.kernel.org Acked-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Rob Herring
Родитель
6f6f6a7029
Коммит
a2a47ca366
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@ -72,13 +72,13 @@ void __init cns3xxx_map_io(void)
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/* used by entry-macro.S */
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void __init cns3xxx_init_irq(void)
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{
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gic_init(0, 29, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
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__io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
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gic_init(0, 29, IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
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IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
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}
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void cns3xxx_power_off(void)
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{
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u32 __iomem *pm_base = __io(CNS3XXX_PM_BASE_VIRT);
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u32 __iomem *pm_base = IOMEM(CNS3XXX_PM_BASE_VIRT);
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u32 clkctrl;
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printk(KERN_INFO "powering system down...\n");
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@ -237,7 +237,7 @@ static void __init __cns3xxx_timer_init(unsigned int timer_irq)
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static void __init cns3xxx_timer_init(void)
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{
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cns3xxx_tmr1 = __io(CNS3XXX_TIMER1_2_3_BASE_VIRT);
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cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT);
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__cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0);
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}
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@ -98,7 +98,7 @@ static struct platform_device cns3xxx_sdhci_pdev = {
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void __init cns3xxx_sdhci_init(void)
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{
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u32 __iomem *gpioa = __io(CNS3XXX_MISC_BASE_VIRT + 0x0014);
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u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
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u32 gpioa_pins = __raw_readl(gpioa);
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/* MMC/SD pins share with GPIOA */
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@ -168,7 +168,7 @@ void __init netx_init_irq(void)
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{
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int irq;
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vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0);
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vic_init(io_p2v(NETX_PA_VIC), 0, ~0, 0);
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for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
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irq_set_chip_and_handler(irq, &netx_hif_chip,
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@ -33,7 +33,7 @@
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#define XMAC_MEM_SIZE 0x1000
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#define SRAM_MEM_SIZE 0x8000
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#define io_p2v(x) ((x) - NETX_IO_PHYS + NETX_IO_VIRT)
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#define io_p2v(x) IOMEM((x) - NETX_IO_PHYS + NETX_IO_VIRT)
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#define io_v2p(x) ((x) - NETX_IO_VIRT + NETX_IO_PHYS)
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#endif
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@ -115,7 +115,7 @@
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*********************************/
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/* Registers */
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#define NETX_SYSTEM_REG(ofs) __io(NETX_VA_SYSTEM + (ofs))
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#define NETX_SYSTEM_REG(ofs) IOMEM(NETX_VA_SYSTEM + (ofs))
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#define NETX_SYSTEM_BOO_SR NETX_SYSTEM_REG(0x00)
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#define NETX_SYSTEM_IOC_CR NETX_SYSTEM_REG(0x04)
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#define NETX_SYSTEM_IOC_MR NETX_SYSTEM_REG(0x08)
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@ -185,7 +185,7 @@
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*******************************/
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/* Registers */
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#define NETX_GPIO_REG(ofs) __io(NETX_VA_GPIO + (ofs))
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#define NETX_GPIO_REG(ofs) IOMEM(NETX_VA_GPIO + (ofs))
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#define NETX_GPIO_CFG(gpio) NETX_GPIO_REG(0x0 + ((gpio)<<2))
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#define NETX_GPIO_THRESHOLD_CAPTURE(gpio) NETX_GPIO_REG(0x40 + ((gpio)<<2))
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#define NETX_GPIO_COUNTER_CTRL(counter) NETX_GPIO_REG(0x80 + ((counter)<<2))
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@ -230,7 +230,7 @@
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*******************************/
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/* Registers */
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#define NETX_PIO_REG(ofs) __io(NETX_VA_PIO + (ofs))
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#define NETX_PIO_REG(ofs) IOMEM(NETX_VA_PIO + (ofs))
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#define NETX_PIO_INPIO NETX_PIO_REG(0x0)
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#define NETX_PIO_OUTPIO NETX_PIO_REG(0x4)
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#define NETX_PIO_OEPIO NETX_PIO_REG(0x8)
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@ -240,7 +240,7 @@
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*******************************/
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/* Registers */
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#define NETX_MIIMU __io(NETX_VA_MIIMU)
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#define NETX_MIIMU IOMEM(NETX_VA_MIIMU)
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/* Bits */
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#define MIIMU_SNRDY (1<<0)
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@ -317,7 +317,7 @@
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*******************************/
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/* Registers */
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#define NETX_PFIFO_REG(ofs) __io(NETX_VA_PFIFO + (ofs))
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#define NETX_PFIFO_REG(ofs) IOMEM(NETX_VA_PFIFO + (ofs))
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#define NETX_PFIFO_BASE(pfifo) NETX_PFIFO_REG(0x00 + ((pfifo)<<2))
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#define NETX_PFIFO_BORDER_BASE(pfifo) NETX_PFIFO_REG(0x80 + ((pfifo)<<2))
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#define NETX_PFIFO_RESET NETX_PFIFO_REG(0x100)
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@ -334,7 +334,7 @@
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*******************************/
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/* Registers */
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#define NETX_MEMCR_REG(ofs) __io(NETX_VA_MEMCR + (ofs))
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#define NETX_MEMCR_REG(ofs) IOMEM(NETX_VA_MEMCR + (ofs))
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#define NETX_MEMCR_SRAM_CTRL(cs) NETX_MEMCR_REG(0x0 + 4 * (cs)) /* SRAM for CS 0..2 */
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#define NETX_MEMCR_SDRAM_CFG_CTRL NETX_MEMCR_REG(0x40)
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#define NETX_MEMCR_SDRAM_TIMING_CTRL NETX_MEMCR_REG(0x44)
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@ -355,7 +355,7 @@
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*******************************/
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/* Registers */
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#define NETX_DPMAS_REG(ofs) __io(NETX_VA_DPMAS + (ofs))
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#define NETX_DPMAS_REG(ofs) IOMEM(NETX_VA_DPMAS + (ofs))
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#define NETX_DPMAS_SYS_STAT NETX_DPMAS_REG(0x4d8)
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#define NETX_DPMAS_INT_STAT NETX_DPMAS_REG(0x4e0)
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#define NETX_DPMAS_INT_EN NETX_DPMAS_REG(0x4f0)
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@ -425,7 +425,7 @@
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/*******************************
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* I2C *
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*******************************/
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#define NETX_I2C_REG(ofs) __io(NETX_VA_I2C, (ofs))
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#define NETX_I2C_REG(ofs) IOMEM(NETX_VA_I2C, (ofs))
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#define NETX_I2C_CTRL NETX_I2C_REG(0x0)
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#define NETX_I2C_DATA NETX_I2C_REG(0x4)
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@ -37,6 +37,6 @@
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#else
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#define IO_ADDRESS(x) (x)
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#endif
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#define __io_address(n) __io(IO_ADDRESS(n))
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#define __io_address(n) IOMEM(IO_ADDRESS(n))
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#endif
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@ -615,7 +615,7 @@ static void __init ag5evm_init(void)
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#ifdef CONFIG_CACHE_L2X0
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/* Shared attribute override enable, 64K*8way */
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l2x0_init(__io(0xf0100000), 0x00460000, 0xc2000fff);
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l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff);
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#endif
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sh73a0_add_standard_devices();
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platform_add_devices(ag5evm_devices, ARRAY_SIZE(ag5evm_devices));
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@ -394,7 +394,7 @@ static void __init bonito_init(void)
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#ifdef CONFIG_CACHE_L2X0
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/* Early BRESP enable, Shared attribute override enable, 32K*8way */
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l2x0_init(__io(0xf0002000), 0x40440000, 0x82000fff);
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l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
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#endif
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r8a7740_add_standard_devices();
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@ -530,7 +530,7 @@ static void __init kota2_init(void)
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#ifdef CONFIG_CACHE_L2X0
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/* Early BRESP enable, Shared attribute override enable, 64K*8way */
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l2x0_init(__io(0xf0100000), 0x40460000, 0x82000fff);
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l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
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#endif
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sh73a0_add_standard_devices();
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platform_add_devices(kota2_devices, ARRAY_SIZE(kota2_devices));
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@ -42,8 +42,8 @@ static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
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void __init r8a7779_init_irq(void)
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{
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void __iomem *gic_dist_base = __io(0xf0001000);
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void __iomem *gic_cpu_base = __io(0xf0000100);
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void __iomem *gic_dist_base = IOMEM(0xf0001000);
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void __iomem *gic_cpu_base = IOMEM(0xf0000100);
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/* use GIC to handle interrupts */
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gic_init(0, 29, gic_dist_base, gic_cpu_base);
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@ -419,8 +419,8 @@ static irqreturn_t sh73a0_pint1_demux(int irq, void *dev_id)
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void __init sh73a0_init_irq(void)
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{
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void __iomem *gic_dist_base = __io(0xf0001000);
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void __iomem *gic_cpu_base = __io(0xf0000100);
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void __iomem *gic_dist_base = IOMEM(0xf0001000);
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void __iomem *gic_cpu_base = IOMEM(0xf0000100);
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void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
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int k, n;
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@ -30,7 +30,7 @@
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#include <asm/smp_twd.h>
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#include <asm/hardware/gic.h>
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#define AVECR 0xfe700040
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#define AVECR IOMEM(0xfe700040)
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static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
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.chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
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@ -140,7 +140,7 @@ void __init r8a7779_smp_prepare_cpus(void)
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scu_enable(scu_base_addr());
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/* Map the reset vector (in headsmp.S) */
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__raw_writel(__pa(shmobile_secondary_vector), __io(AVECR));
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__raw_writel(__pa(shmobile_secondary_vector), AVECR);
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/* enable cache coherency on CPU0 */
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modify_scu_cpu_psr(0, 3 << (cpu * 8));
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@ -28,11 +28,11 @@
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#include <asm/smp_twd.h>
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#include <asm/hardware/gic.h>
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#define WUPCR 0xe6151010
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#define SRESCR 0xe6151018
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#define PSTR 0xe6151040
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#define SBAR 0xe6180020
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#define APARMBAREA 0xe6f10020
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#define WUPCR IOMEM(0xe6151010)
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#define SRESCR IOMEM(0xe6151018)
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#define PSTR IOMEM(0xe6151040)
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#define SBAR IOMEM(0xe6180020)
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#define APARMBAREA IOMEM(0xe6f10020)
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static void __iomem *scu_base_addr(void)
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{
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@ -80,10 +80,10 @@ int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
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/* enable cache coherency */
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modify_scu_cpu_psr(0, 3 << (cpu * 8));
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if (((__raw_readw(__io(PSTR)) >> (4 * cpu)) & 3) == 3)
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__raw_writel(1 << cpu, __io(WUPCR)); /* wake up */
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if (((__raw_readw(PSTR) >> (4 * cpu)) & 3) == 3)
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__raw_writel(1 << cpu, WUPCR); /* wake up */
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else
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__raw_writel(1 << cpu, __io(SRESCR)); /* reset */
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__raw_writel(1 << cpu, SRESCR); /* reset */
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return 0;
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}
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@ -95,8 +95,8 @@ void __init sh73a0_smp_prepare_cpus(void)
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scu_enable(scu_base_addr());
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/* Map the reset vector (in headsmp.S) */
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__raw_writel(0, __io(APARMBAREA)); /* 4k */
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__raw_writel(__pa(shmobile_secondary_vector), __io(SBAR));
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__raw_writel(0, APARMBAREA); /* 4k */
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__raw_writel(__pa(shmobile_secondary_vector), SBAR);
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/* enable cache coherency on CPU0 */
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modify_scu_cpu_psr(0, 3 << (cpu * 8));
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@ -23,7 +23,7 @@
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(((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
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/* typesafe io address */
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#define __io_address(n) __io(IO_ADDRESS(n))
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#define __io_address(n) IOMEM(IO_ADDRESS(n))
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/* Used by some plat-nomadik code */
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#define io_p2v(n) __io_address(n)
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