powerpc fixes for 4.3 #4
- Revert "Use the POWER8 Micro Partition Prefetch Engine in KVM HV on POWER8" from Paul - Handle irq_happened flag correctly in off-line loop from Paul - Validate rtas.entry before calling enter_rtas() from Vasant -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWKakXAAoJEFHr6jzI4aWAqwsP/22a8aq7SPuPaCK/c7u84aHg UkzYNdrC+osDvnrydqyJsmIojVLX+AsJ7TCbBZFaJ6oOuew9bVzmZ5mfNvOVn86H dCH2GMr4NbWbkO3SaFi6ZTUVGl7JyjEhf3uCtKGssa2+Do8FubK6Y88L1rhzFFdz l1Dx3Jp8CpGKcByQfwYyaNZhC/GEZ06pY36d362mLnyctxcQRYr5l+8boDH81nyE f89RE7baNPYOL0YOhZAh3ZilBrZ8DIAaesMXU8LUKFbLTBgWfVPkDy3l5a2m47oP V/Yi+oEQBkL/3Itth57iGWpl8vVkzF2MTu8Aep3BzHJXqXCliTzVVdXETW6NCdut Nss0xtnNdM18+0mhG3LzzdoZGi/Zb0SYz8j+nY5vE2nf7FDVFkAZzKHeW822zNaV A1PLJa+ei4jVhKtTp4wETjpUi+kw+ikM+rR1L1/+IKHbriLsRrj7Zw3xo6Em1KVq cI2g7DZLSzptIprxbEv9rNhb1VlBot4jc4mmGhmyMlwKDkpCxRkYVv+Ilfi6jCSc 6llKTZfKqEV+0sXO6QISv8wfiye84jVTKOlkpQLvpugz9rBTpq8apmInVh4AHF2b wDRgs/iyOSZuz+UiPEHHXbW7ZfF2F7lqxxtQgJefiWLDsvBbsfnVTyDJsKibvWzb lxorlKx/tH/q4pNBjmoB =K7eA -----END PGP SIGNATURE----- Merge tag 'powerpc-4.3-5' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull powerpc fixes from Michael Ellerman: - Revert "Use the POWER8 Micro Partition Prefetch Engine in KVM HV on POWER8" from Paul - Handle irq_happened flag correctly in off-line loop from Paul - Validate rtas.entry before calling enter_rtas() from Vasant * tag 'powerpc-4.3-5' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: powerpc/rtas: Validate rtas.entry before calling enter_rtas() powerpc/powernv: Handle irq_happened flag correctly in off-line loop powerpc: Revert "Use the POWER8 Micro Partition Prefetch Engine in KVM HV on POWER8"
This commit is contained in:
Linus Torvalds
Коммит
a2c01ed5d4
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@ -3,7 +3,6 @@
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#ifdef __KERNEL__
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#include <asm/reg.h>
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/* bytes per L1 cache line */
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#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
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@ -40,12 +39,6 @@ struct ppc64_caches {
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};
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extern struct ppc64_caches ppc64_caches;
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static inline void logmpp(u64 x)
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{
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asm volatile(PPC_LOGMPP(R1) : : "r" (x));
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}
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#endif /* __powerpc64__ && ! __ASSEMBLY__ */
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#if defined(__ASSEMBLY__)
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@ -297,8 +297,6 @@ struct kvmppc_vcore {
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u32 arch_compat;
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ulong pcr;
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ulong dpdes; /* doorbell state (POWER8) */
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void *mpp_buffer; /* Micro Partition Prefetch buffer */
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bool mpp_buffer_is_valid;
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ulong conferring_threads;
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};
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@ -141,7 +141,6 @@
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#define PPC_INST_ISEL 0x7c00001e
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#define PPC_INST_ISEL_MASK 0xfc00003e
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#define PPC_INST_LDARX 0x7c0000a8
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#define PPC_INST_LOGMPP 0x7c0007e4
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#define PPC_INST_LSWI 0x7c0004aa
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#define PPC_INST_LSWX 0x7c00042a
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#define PPC_INST_LWARX 0x7c000028
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@ -285,20 +284,6 @@
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#define __PPC_EH(eh) 0
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#endif
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/* POWER8 Micro Partition Prefetch (MPP) parameters */
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/* Address mask is common for LOGMPP instruction and MPPR SPR */
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#define PPC_MPPE_ADDRESS_MASK 0xffffffffc000ULL
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/* Bits 60 and 61 of MPP SPR should be set to one of the following */
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/* Aborting the fetch is indeed setting 00 in the table size bits */
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#define PPC_MPPR_FETCH_ABORT (0x0ULL << 60)
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#define PPC_MPPR_FETCH_WHOLE_TABLE (0x2ULL << 60)
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/* Bits 54 and 55 of register for LOGMPP instruction should be set to: */
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#define PPC_LOGMPP_LOG_L2 (0x02ULL << 54)
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#define PPC_LOGMPP_LOG_L2L3 (0x01ULL << 54)
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#define PPC_LOGMPP_LOG_ABORT (0x03ULL << 54)
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/* Deal with instructions that older assemblers aren't aware of */
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#define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \
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__PPC_RA(a) | __PPC_RB(b))
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@ -307,8 +292,6 @@
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#define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \
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___PPC_RT(t) | ___PPC_RA(a) | \
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___PPC_RB(b) | __PPC_EH(eh))
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#define PPC_LOGMPP(b) stringify_in_c(.long PPC_INST_LOGMPP | \
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__PPC_RB(b))
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#define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \
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___PPC_RT(t) | ___PPC_RA(a) | \
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___PPC_RB(b) | __PPC_EH(eh))
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@ -226,7 +226,6 @@
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#define CTRL_TE 0x00c00000 /* thread enable */
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#define CTRL_RUNLATCH 0x1
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#define SPRN_DAWR 0xB4
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#define SPRN_MPPR 0xB8 /* Micro Partition Prefetch Register */
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#define SPRN_RPR 0xBA /* Relative Priority Register */
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#define SPRN_CIABR 0xBB
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#define CIABR_PRIV 0x3
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@ -1043,6 +1043,9 @@ asmlinkage int ppc_rtas(struct rtas_args __user *uargs)
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if (!capable(CAP_SYS_ADMIN))
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return -EPERM;
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if (!rtas.entry)
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return -EINVAL;
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if (copy_from_user(&args, uargs, 3 * sizeof(u32)) != 0)
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return -EFAULT;
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@ -36,7 +36,6 @@
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#include <asm/reg.h>
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#include <asm/cputable.h>
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#include <asm/cache.h>
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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#include <asm/uaccess.h>
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@ -75,12 +74,6 @@
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static DECLARE_BITMAP(default_enabled_hcalls, MAX_HCALL_OPCODE/4 + 1);
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#if defined(CONFIG_PPC_64K_PAGES)
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#define MPP_BUFFER_ORDER 0
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#elif defined(CONFIG_PPC_4K_PAGES)
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#define MPP_BUFFER_ORDER 3
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#endif
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static int dynamic_mt_modes = 6;
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module_param(dynamic_mt_modes, int, S_IRUGO | S_IWUSR);
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MODULE_PARM_DESC(dynamic_mt_modes, "Set of allowed dynamic micro-threading modes: 0 (= none), 2, 4, or 6 (= 2 or 4)");
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@ -1455,13 +1448,6 @@ static struct kvmppc_vcore *kvmppc_vcore_create(struct kvm *kvm, int core)
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vcore->kvm = kvm;
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INIT_LIST_HEAD(&vcore->preempt_list);
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vcore->mpp_buffer_is_valid = false;
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if (cpu_has_feature(CPU_FTR_ARCH_207S))
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vcore->mpp_buffer = (void *)__get_free_pages(
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GFP_KERNEL|__GFP_ZERO,
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MPP_BUFFER_ORDER);
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return vcore;
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}
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@ -1894,33 +1880,6 @@ static int on_primary_thread(void)
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return 1;
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}
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static void kvmppc_start_saving_l2_cache(struct kvmppc_vcore *vc)
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{
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phys_addr_t phy_addr, mpp_addr;
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phy_addr = (phys_addr_t)virt_to_phys(vc->mpp_buffer);
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mpp_addr = phy_addr & PPC_MPPE_ADDRESS_MASK;
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mtspr(SPRN_MPPR, mpp_addr | PPC_MPPR_FETCH_ABORT);
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logmpp(mpp_addr | PPC_LOGMPP_LOG_L2);
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vc->mpp_buffer_is_valid = true;
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}
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static void kvmppc_start_restoring_l2_cache(const struct kvmppc_vcore *vc)
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{
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phys_addr_t phy_addr, mpp_addr;
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phy_addr = virt_to_phys(vc->mpp_buffer);
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mpp_addr = phy_addr & PPC_MPPE_ADDRESS_MASK;
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/* We must abort any in-progress save operations to ensure
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* the table is valid so that prefetch engine knows when to
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* stop prefetching. */
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logmpp(mpp_addr | PPC_LOGMPP_LOG_ABORT);
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mtspr(SPRN_MPPR, mpp_addr | PPC_MPPR_FETCH_WHOLE_TABLE);
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}
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/*
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* A list of virtual cores for each physical CPU.
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* These are vcores that could run but their runner VCPU tasks are
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@ -2471,14 +2430,8 @@ static noinline void kvmppc_run_core(struct kvmppc_vcore *vc)
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srcu_idx = srcu_read_lock(&vc->kvm->srcu);
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if (vc->mpp_buffer_is_valid)
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kvmppc_start_restoring_l2_cache(vc);
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__kvmppc_vcore_entry();
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if (vc->mpp_buffer)
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kvmppc_start_saving_l2_cache(vc);
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srcu_read_unlock(&vc->kvm->srcu, srcu_idx);
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spin_lock(&vc->lock);
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@ -3073,14 +3026,8 @@ static void kvmppc_free_vcores(struct kvm *kvm)
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{
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long int i;
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for (i = 0; i < KVM_MAX_VCORES; ++i) {
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if (kvm->arch.vcores[i] && kvm->arch.vcores[i]->mpp_buffer) {
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struct kvmppc_vcore *vc = kvm->arch.vcores[i];
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free_pages((unsigned long)vc->mpp_buffer,
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MPP_BUFFER_ORDER);
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}
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for (i = 0; i < KVM_MAX_VCORES; ++i)
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kfree(kvm->arch.vcores[i]);
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}
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kvm->arch.online_vcores = 0;
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}
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@ -171,7 +171,26 @@ static void pnv_smp_cpu_kill_self(void)
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* so clear LPCR:PECE1. We keep PECE2 enabled.
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*/
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mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) & ~(u64)LPCR_PECE1);
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/*
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* Hard-disable interrupts, and then clear irq_happened flags
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* that we can safely ignore while off-line, since they
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* are for things for which we do no processing when off-line
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* (or in the case of HMI, all the processing we need to do
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* is done in lower-level real-mode code).
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*/
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hard_irq_disable();
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local_paca->irq_happened &= ~(PACA_IRQ_DEC | PACA_IRQ_HMI);
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while (!generic_check_cpu_restart(cpu)) {
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/*
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* Clear IPI flag, since we don't handle IPIs while
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* offline, except for those when changing micro-threading
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* mode, which are handled explicitly below, and those
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* for coming online, which are handled via
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* generic_check_cpu_restart() calls.
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*/
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kvmppc_set_host_ipi(cpu, 0);
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ppc64_runlatch_off();
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@ -196,20 +215,20 @@ static void pnv_smp_cpu_kill_self(void)
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* having finished executing in a KVM guest, then srr1
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* contains 0.
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*/
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if ((srr1 & wmask) == SRR1_WAKEEE) {
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if (((srr1 & wmask) == SRR1_WAKEEE) ||
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(local_paca->irq_happened & PACA_IRQ_EE)) {
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icp_native_flush_interrupt();
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local_paca->irq_happened &= PACA_IRQ_HARD_DIS;
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smp_mb();
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} else if ((srr1 & wmask) == SRR1_WAKEHDBELL) {
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unsigned long msg = PPC_DBELL_TYPE(PPC_DBELL_SERVER);
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asm volatile(PPC_MSGCLR(%0) : : "r" (msg));
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kvmppc_set_host_ipi(cpu, 0);
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}
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local_paca->irq_happened &= ~(PACA_IRQ_EE | PACA_IRQ_DBELL);
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smp_mb();
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if (cpu_core_split_required())
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continue;
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if (!generic_check_cpu_restart(cpu))
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if (srr1 && !generic_check_cpu_restart(cpu))
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DBG("CPU%d Unexpected exit while offline !\n", cpu);
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}
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mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) | LPCR_PECE1);
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