crypto: arm64/aes-neon - fix for big endian
The AES implementation using pure NEON instructions relies on the generic
AES key schedule generation routines, which store the round keys as arrays
of 32-bit quantities stored in memory using native endianness. This means
we should refer to these round keys using 4x4 loads rather than 16x1 loads.
In addition, the ShiftRows tables are loading using a single scalar load,
which is also affected by endianness, so emit these tables in the correct
order depending on whether we are building for big endian or not.
Fixes: 49788fe2a1
("arm64/crypto: AES-ECB/CBC/CTR/XTS using ARMv8 NEON and Crypto Extensions")
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Родитель
56e4e76c68
Коммит
a2c435cc99
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@ -9,6 +9,7 @@
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#define AES_ENTRY(func) ENTRY(neon_ ## func)
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#define AES_ENDPROC(func) ENDPROC(neon_ ## func)
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@ -83,13 +84,13 @@
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.endm
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.macro do_block, enc, in, rounds, rk, rkp, i
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ld1 {v15.16b}, [\rk]
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ld1 {v15.4s}, [\rk]
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add \rkp, \rk, #16
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mov \i, \rounds
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1111: eor \in\().16b, \in\().16b, v15.16b /* ^round key */
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tbl \in\().16b, {\in\().16b}, v13.16b /* ShiftRows */
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sub_bytes \in
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ld1 {v15.16b}, [\rkp], #16
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ld1 {v15.4s}, [\rkp], #16
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subs \i, \i, #1
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beq 2222f
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.if \enc == 1
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@ -229,7 +230,7 @@
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.endm
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.macro do_block_2x, enc, in0, in1 rounds, rk, rkp, i
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ld1 {v15.16b}, [\rk]
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ld1 {v15.4s}, [\rk]
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add \rkp, \rk, #16
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mov \i, \rounds
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1111: eor \in0\().16b, \in0\().16b, v15.16b /* ^round key */
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@ -237,7 +238,7 @@
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sub_bytes_2x \in0, \in1
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tbl \in0\().16b, {\in0\().16b}, v13.16b /* ShiftRows */
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tbl \in1\().16b, {\in1\().16b}, v13.16b /* ShiftRows */
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ld1 {v15.16b}, [\rkp], #16
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ld1 {v15.4s}, [\rkp], #16
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subs \i, \i, #1
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beq 2222f
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.if \enc == 1
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@ -254,7 +255,7 @@
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.endm
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.macro do_block_4x, enc, in0, in1, in2, in3, rounds, rk, rkp, i
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ld1 {v15.16b}, [\rk]
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ld1 {v15.4s}, [\rk]
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add \rkp, \rk, #16
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mov \i, \rounds
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1111: eor \in0\().16b, \in0\().16b, v15.16b /* ^round key */
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@ -266,7 +267,7 @@
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tbl \in1\().16b, {\in1\().16b}, v13.16b /* ShiftRows */
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tbl \in2\().16b, {\in2\().16b}, v13.16b /* ShiftRows */
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tbl \in3\().16b, {\in3\().16b}, v13.16b /* ShiftRows */
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ld1 {v15.16b}, [\rkp], #16
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ld1 {v15.4s}, [\rkp], #16
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subs \i, \i, #1
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beq 2222f
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.if \enc == 1
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@ -306,12 +307,16 @@
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.text
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.align 4
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.LForward_ShiftRows:
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.byte 0x0, 0x5, 0xa, 0xf, 0x4, 0x9, 0xe, 0x3
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.byte 0x8, 0xd, 0x2, 0x7, 0xc, 0x1, 0x6, 0xb
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CPU_LE( .byte 0x0, 0x5, 0xa, 0xf, 0x4, 0x9, 0xe, 0x3 )
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CPU_LE( .byte 0x8, 0xd, 0x2, 0x7, 0xc, 0x1, 0x6, 0xb )
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CPU_BE( .byte 0xb, 0x6, 0x1, 0xc, 0x7, 0x2, 0xd, 0x8 )
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CPU_BE( .byte 0x3, 0xe, 0x9, 0x4, 0xf, 0xa, 0x5, 0x0 )
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.LReverse_ShiftRows:
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.byte 0x0, 0xd, 0xa, 0x7, 0x4, 0x1, 0xe, 0xb
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.byte 0x8, 0x5, 0x2, 0xf, 0xc, 0x9, 0x6, 0x3
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CPU_LE( .byte 0x0, 0xd, 0xa, 0x7, 0x4, 0x1, 0xe, 0xb )
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CPU_LE( .byte 0x8, 0x5, 0x2, 0xf, 0xc, 0x9, 0x6, 0x3 )
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CPU_BE( .byte 0x3, 0x6, 0x9, 0xc, 0xf, 0x2, 0x5, 0x8 )
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CPU_BE( .byte 0xb, 0xe, 0x1, 0x4, 0x7, 0xa, 0xd, 0x0 )
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.LForward_Sbox:
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.byte 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5
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