ARM: iop32x: enable multiplatform support
After iop32x was converted to the generic multi-irq entry code, nothing really stops us from building it into a generic kernel. The two last headers can simply be removed, the mach/irqs.h gets replaced with the sparse-irq intiialization from the board specific .nr_irqs value, and the decompressor debug output can use the debug_ll hack that all other platforms use. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
Родитель
8c1fb11b8a
Коммит
a3102fafdc
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@ -356,17 +356,6 @@ config ARCH_FOOTBRIDGE
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Support for systems based on the DC21285 companion chip
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("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
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config ARCH_IOP32X
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bool "IOP32x-based"
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select CPU_XSCALE
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select GPIO_IOP
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select GPIOLIB
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select FORCE_PCI
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select PLAT_IOP
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help
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Support for Intel's 80219 and IOP32X (XScale) family of
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processors.
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config ARCH_IXP4XX
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bool "IXP4xx-based"
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select ARCH_SUPPORTS_BIG_ENDIAN
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@ -688,9 +677,6 @@ config ARCH_MPS2
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config ARCH_ACORN
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bool
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config PLAT_IOP
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bool
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config PLAT_ORION
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bool
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select CLKSRC_MMIO
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@ -7,6 +7,7 @@ CONFIG_SLAB=y
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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# CONFIG_BLK_DEV_BSG is not set
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# CONFIG_ARCH_MULTI_V7 is not set
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CONFIG_ARCH_IOP32X=y
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CONFIG_MACH_GLANTANK=y
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CONFIG_ARCH_IQ80321=y
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@ -1,10 +1,17 @@
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# SPDX-License-Identifier: GPL-2.0
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menuconfig ARCH_IOP32X
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bool "IOP32x-based platforms"
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depends on ARCH_MULTI_V5
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select CPU_XSCALE
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select GPIO_IOP
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select GPIOLIB
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select FORCE_PCI
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help
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Support for Intel's 80219 and IOP32X (XScale) family of
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processors.
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if ARCH_IOP32X
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menu "IOP32x Implementation Options"
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comment "IOP32x Platform Types"
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config MACH_EP80219
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bool
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@ -42,6 +49,4 @@ config MACH_EM7210
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board. Say also Y here if you have a SS4000e Baxter Creek NAS
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appliance."
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endmenu
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endif
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@ -223,6 +223,7 @@ static void __init em7210_init_machine(void)
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MACHINE_START(EM7210, "Lanner EM7210")
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.atag_offset = 0x100,
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.nr_irqs = IOP32X_NR_IRQS,
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.map_io = em7210_map_io,
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.init_irq = iop32x_init_irq,
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.init_time = em7210_timer_init,
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@ -205,6 +205,7 @@ static void __init glantank_init_machine(void)
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MACHINE_START(GLANTANK, "GLAN Tank")
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/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
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.atag_offset = 0x100,
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.nr_irqs = IOP32X_NR_IRQS,
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.map_io = glantank_map_io,
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.init_irq = iop32x_init_irq,
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.init_time = glantank_timer_init,
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@ -1,14 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* arch/arm/mach-iop32x/include/mach/irqs.h
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*
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* Author: Rory Bolt <rorybolt@pacbell.net>
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* Copyright: (C) 2002 Rory Bolt
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*/
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#ifndef __IRQS_H
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#define __IRQS_H
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#define NR_IRQS 33
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#endif
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@ -1,25 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* arch/arm/mach-iop32x/include/mach/uncompress.h
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*/
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#include <asm/types.h>
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#include <asm/mach-types.h>
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#include <linux/serial_reg.h>
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#define uart_base ((volatile u8 *)0xfe800000)
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#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
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static inline void putc(char c)
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{
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while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
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barrier();
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uart_base[UART_TX] = c;
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}
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static inline void flush(void)
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{
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}
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#define arch_decomp_setup() do { } while (0)
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@ -324,6 +324,7 @@ MACHINE_END
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MACHINE_START(EP80219, "Intel EP80219")
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/* Maintainer: Intel Corp. */
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.atag_offset = 0x100,
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.nr_irqs = IOP32X_NR_IRQS,
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.map_io = iq31244_map_io,
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.init_irq = iop32x_init_irq,
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.init_time = iq31244_timer_init,
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@ -183,6 +183,7 @@ static void __init iq80321_init_machine(void)
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MACHINE_START(IQ80321, "Intel IQ80321")
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/* Maintainer: Intel Corp. */
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.atag_offset = 0x100,
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.nr_irqs = IOP32X_NR_IRQS,
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.map_io = iq80321_map_io,
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.init_irq = iop32x_init_irq,
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.init_time = iq80321_timer_init,
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@ -43,4 +43,6 @@
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#define IRQ_IOP32X_XINT3 IOP_IRQ(30)
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#define IRQ_IOP32X_HPI IOP_IRQ(31)
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#define IOP32X_NR_IRQS (IRQ_IOP32X_HPI + 1)
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#endif
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@ -358,6 +358,7 @@ static void __init n2100_init_machine(void)
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MACHINE_START(N2100, "Thecus N2100")
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/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
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.atag_offset = 0x100,
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.nr_irqs = IOP32X_NR_IRQS,
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.map_io = n2100_map_io,
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.init_irq = iop32x_init_irq,
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.init_time = n2100_timer_init,
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