From a3d9bf1dfdaf6f7df6c5340521dff1aafe39393f Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Wed, 6 May 2009 10:14:04 +1000 Subject: [PATCH] m68knommu: remove unecessary interrupt level setting in ColdFire 520x setup The new code for the interrupt controller in the ColdFire 520x takes care of all the interrupt controller setup. No manual config of the level registers (ICR) is required by the platform device setup code. So remove it. Signed-off-by: Greg Ungerer --- arch/m68knommu/platform/520x/config.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/m68knommu/platform/520x/config.c b/arch/m68knommu/platform/520x/config.c index 6a1fd743817a..92614de42cd3 100644 --- a/arch/m68knommu/platform/520x/config.c +++ b/arch/m68knommu/platform/520x/config.c @@ -81,15 +81,11 @@ static struct platform_device *m520x_devices[] __initdata = { /***************************************************************************/ -#define INTC0 (MCF_MBAR + MCFICM_INTC0) - static void __init m520x_uart_init_line(int line, int irq) { u16 par; u8 par2; - writeb(0x03, INTC0 + MCFINTC_ICR0 + MCFINT_UART0 + line); - switch (line) { case 0: par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART); @@ -128,11 +124,6 @@ static void __init m520x_fec_init(void) { u8 v; - /* Unmask FEC interrupts at ColdFire interrupt controller */ - writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 36); - writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 40); - writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 42); - /* Set multi-function pins to ethernet mode */ v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FEC); writeb(v | 0xf0, MCF_IPSBAR + MCF_GPIO_PAR_FEC);