alx: prepare resource allocation for multi queue support
Allocate, initialise and free alx_tx_queue structs based on the number of alx_napi structures. Also increase the size of the descriptor memory based on the number of tx queues in use. Based on the downstream driver at github.com/qca/alx Signed-off-by: Tobias Regnery <tobias.regnery@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Tobias Regnery
David S. Miller
Родитель
e0eac25460
Коммит
a4076d347f
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@ -429,28 +429,45 @@ static irqreturn_t alx_intr_legacy(int irq, void *data)
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return alx_intr_handle(alx, intr);
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}
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static const u16 txring_header_reg[] = {ALX_TPD_PRI0_ADDR_LO,
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ALX_TPD_PRI1_ADDR_LO,
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ALX_TPD_PRI2_ADDR_LO,
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ALX_TPD_PRI3_ADDR_LO};
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static void alx_init_ring_ptrs(struct alx_priv *alx)
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{
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struct alx_hw *hw = &alx->hw;
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u32 addr_hi = ((u64)alx->descmem.dma) >> 32;
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struct alx_napi *np = alx->qnapi[0];
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struct alx_napi *np;
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int i;
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for (i = 0; i < alx->num_napi; i++) {
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np = alx->qnapi[i];
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if (np->txq) {
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np->txq->read_idx = 0;
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np->txq->write_idx = 0;
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alx_write_mem32(hw,
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txring_header_reg[np->txq->queue_idx],
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np->txq->tpd_dma);
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}
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if (np->rxq) {
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np->rxq->read_idx = 0;
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np->rxq->write_idx = 0;
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np->rxq->rrd_read_idx = 0;
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alx_write_mem32(hw, ALX_RX_BASE_ADDR_HI, addr_hi);
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alx_write_mem32(hw, ALX_RRD_ADDR_LO, np->rxq->rrd_dma);
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alx_write_mem32(hw, ALX_RRD_RING_SZ, alx->rx_ringsz);
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alx_write_mem32(hw, ALX_RFD_ADDR_LO, np->rxq->rfd_dma);
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}
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}
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alx_write_mem32(hw, ALX_TX_BASE_ADDR_HI, addr_hi);
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alx_write_mem32(hw, ALX_TPD_RING_SZ, alx->tx_ringsz);
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alx_write_mem32(hw, ALX_RX_BASE_ADDR_HI, addr_hi);
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alx_write_mem32(hw, ALX_RRD_RING_SZ, alx->rx_ringsz);
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alx_write_mem32(hw, ALX_RFD_RING_SZ, alx->rx_ringsz);
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alx_write_mem32(hw, ALX_RFD_BUF_SZ, alx->rxbuf_size);
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np->txq->read_idx = 0;
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np->txq->write_idx = 0;
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alx_write_mem32(hw, ALX_TX_BASE_ADDR_HI, addr_hi);
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alx_write_mem32(hw, ALX_TPD_PRI0_ADDR_LO, np->txq->tpd_dma);
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alx_write_mem32(hw, ALX_TPD_RING_SZ, alx->tx_ringsz);
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/* load these pointers into the chip */
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alx_write_mem32(hw, ALX_SRAM9, ALX_SRAM_LOAD_PTR);
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}
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@ -478,7 +495,7 @@ static void alx_free_rxring_buf(struct alx_rx_queue *rxq)
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struct alx_buffer *cur_buf;
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u16 i;
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if (rxq == NULL)
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if (!rxq->bufs)
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return;
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for (i = 0; i < rxq->count; i++) {
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@ -502,7 +519,13 @@ static void alx_free_rxring_buf(struct alx_rx_queue *rxq)
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static void alx_free_buffers(struct alx_priv *alx)
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{
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alx_free_txring_buf(alx->qnapi[0]->txq);
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int i;
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for (i = 0; i < alx->num_txq; i++)
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if (alx->qnapi[i] && alx->qnapi[i]->txq)
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alx_free_txring_buf(alx->qnapi[i]->txq);
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if (alx->qnapi[0] && alx->qnapi[0]->rxq)
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alx_free_rxring_buf(alx->qnapi[0]->rxq);
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}
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@ -611,7 +634,7 @@ static int alx_alloc_rx_ring(struct alx_priv *alx, struct alx_rx_queue *rxq,
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static int alx_alloc_rings(struct alx_priv *alx)
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{
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int offset = 0;
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int i, offset = 0;
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/* physical tx/rx ring descriptors
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*
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@ -619,7 +642,8 @@ static int alx_alloc_rings(struct alx_priv *alx)
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* 4G boundary (hardware has a single register for high 32 bits
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* of addresses only)
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*/
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alx->descmem.size = sizeof(struct alx_txd) * alx->tx_ringsz +
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alx->descmem.size = sizeof(struct alx_txd) * alx->tx_ringsz *
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alx->num_txq +
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sizeof(struct alx_rrd) * alx->rx_ringsz +
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sizeof(struct alx_rfd) * alx->rx_ringsz;
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alx->descmem.virt = dma_zalloc_coherent(&alx->hw.pdev->dev,
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@ -633,11 +657,13 @@ static int alx_alloc_rings(struct alx_priv *alx)
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BUILD_BUG_ON(sizeof(struct alx_txd) % 8);
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BUILD_BUG_ON(sizeof(struct alx_rrd) % 8);
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offset = alx_alloc_tx_ring(alx, alx->qnapi[0]->txq, offset);
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for (i = 0; i < alx->num_txq; i++) {
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offset = alx_alloc_tx_ring(alx, alx->qnapi[i]->txq, offset);
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if (offset < 0) {
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netdev_err(alx->dev, "Allocation of tx buffer failed!\n");
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return -ENOMEM;
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}
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}
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offset = alx_alloc_rx_ring(alx, alx->qnapi[0]->rxq, offset);
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if (offset < 0) {
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@ -652,10 +678,15 @@ static int alx_alloc_rings(struct alx_priv *alx)
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static void alx_free_rings(struct alx_priv *alx)
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{
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int i;
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alx_free_buffers(alx);
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kfree(alx->qnapi[0]->txq->bufs);
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for (i = 0; i < alx->num_txq; i++)
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if (alx->qnapi[i] && alx->qnapi[i]->txq)
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kfree(alx->qnapi[i]->txq->bufs);
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if (alx->qnapi[0] && alx->qnapi[0]->rxq)
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kfree(alx->qnapi[0]->rxq->bufs);
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if (!alx->descmem.virt)
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@ -668,16 +699,19 @@ static void alx_free_rings(struct alx_priv *alx)
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static void alx_free_napis(struct alx_priv *alx)
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{
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struct alx_napi *np;
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int i;
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np = alx->qnapi[0];
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for (i = 0; i < alx->num_napi; i++) {
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np = alx->qnapi[i];
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if (!np)
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return;
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continue;
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netif_napi_del(&np->napi);
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kfree(np->txq);
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kfree(np->rxq);
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kfree(np);
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alx->qnapi[0] = NULL;
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alx->qnapi[i] = NULL;
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}
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}
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static const u32 tx_vect_mask[] = {ALX_ISR_TX_Q0, ALX_ISR_TX_Q1,
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@ -692,31 +726,36 @@ static int alx_alloc_napis(struct alx_priv *alx)
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struct alx_napi *np;
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struct alx_rx_queue *rxq;
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struct alx_tx_queue *txq;
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int i;
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alx->int_mask &= ~ALX_ISR_ALL_QUEUES;
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/* allocate alx_napi structures */
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for (i = 0; i < alx->num_napi; i++) {
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np = kzalloc(sizeof(struct alx_napi), GFP_KERNEL);
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if (!np)
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goto err_out;
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np->alx = alx;
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netif_napi_add(alx->dev, &np->napi, alx_poll, 64);
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alx->qnapi[0] = np;
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alx->qnapi[i] = np;
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}
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/* allocate tx queues */
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np = alx->qnapi[0];
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for (i = 0; i < alx->num_txq; i++) {
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np = alx->qnapi[i];
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txq = kzalloc(sizeof(*txq), GFP_KERNEL);
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if (!txq)
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goto err_out;
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np->txq = txq;
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txq->queue_idx = 0;
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txq->queue_idx = i;
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txq->count = alx->tx_ringsz;
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txq->netdev = alx->dev;
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txq->dev = &alx->hw.pdev->dev;
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np->vec_mask |= tx_vect_mask[0];
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alx->int_mask |= tx_vect_mask[0];
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np->vec_mask |= tx_vect_mask[i];
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alx->int_mask |= tx_vect_mask[i];
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}
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/* allocate rx queues */
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np = alx->qnapi[0];
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@ -1075,11 +1114,14 @@ static netdev_features_t alx_fix_features(struct net_device *netdev,
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static void alx_netif_stop(struct alx_priv *alx)
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{
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int i;
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netif_trans_update(alx->dev);
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if (netif_carrier_ok(alx->dev)) {
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netif_carrier_off(alx->dev);
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netif_tx_disable(alx->dev);
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napi_disable(&alx->qnapi[0]->napi);
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for (i = 0; i < alx->num_napi; i++)
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napi_disable(&alx->qnapi[i]->napi);
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}
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}
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@ -1148,8 +1190,11 @@ static int alx_change_mtu(struct net_device *netdev, int mtu)
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static void alx_netif_start(struct alx_priv *alx)
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{
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int i;
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netif_tx_wake_all_queues(alx->dev);
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napi_enable(&alx->qnapi[0]->napi);
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for (i = 0; i < alx->num_napi; i++)
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napi_enable(&alx->qnapi[i]->napi);
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netif_carrier_on(alx->dev);
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}
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