A single commit to handle an erratum in Cavium ThunderX to prevent access

to GIC registers which miss in the implementation.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAl5uP1gTHHRnbHhAbGlu
 dXRyb25peC5kZQAKCRCmGPVMDXSYoTOpD/9tPpEEosbmlQfAXe7bkBCzz3+Zrxcv
 XxgmVhhU1MhKImNCchi88wHT7Gibxr4JR3AaM2iIoXV2rRn5VTnUk9udm2rjQaLA
 ufXNm8zJQt9zia90GHc/R5JW+eeY7s+rBlExQLuBFHmV29ZnqlNOv0hAWOfz+gSM
 +q9JOSy21F+KW93T6lXgDWVT77b/vI+DdOQAF16Y/zwMT5sv1HK+2GbLjTmWCf/u
 vjEIm4ggJRwn2edhe0/Ex0M1Q2S3bgq5nVx3SfunOHu17BZWTupotqjVjQDPcey0
 JEfvN873FO499ILaacAozzVd/Ajhr617HE1KLGNuMyOzk4t1ZLmWXoqxju1NYRIC
 NpQaxEJVggz76NFdudLjSpd7gqSZho5TjnMFfCbiSPrrQ2rIQRLdcB4u4jwHDNlA
 AZLMhK5/xT0fWqAzoOvGCdO9Sj8axZ2/jNylXGEVMjw6tf96tL6Qz0V+WaA8LF1k
 7IpXy4cx+Sj/4LRNBiw2Xxb0BPe919lSJ7QNln7239NiiJs7OKGQAH0UrICzpJec
 6n8iBSkkr/DLoOjUFncIpuINsT5XN8odgkJT3xV9VYc1veg3yLIevZx8Z2RDOyAS
 I9Giq8rVE0PWPcDQfJscLbXjAL5xTa7H2rzOjiKIf4aGKdY1+bmaaonDkwOs6MfL
 SPAe5rvPhNvClA==
 =Z7sW
 -----END PGP SIGNATURE-----

Merge tag 'irq-urgent-2020-03-15' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq fix from Thomas Gleixner:
 "A single commit to handle an erratum in Cavium ThunderX to prevent
  access to GIC registers which are broken in the implementation"

* tag 'irq-urgent-2020-03-15' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip/gic-v3: Workaround Cavium erratum 38539 when reading GICD_TYPER2

Documentation/arm64/silicon-errata.rst

@@ -110,6 +110,8 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154        |
 +----------------+-----------------+-----------------+-----------------------------+
+| Cavium         | ThunderX GICv3  | #38539          | N/A                         |
++----------------+-----------------+-----------------+-----------------------------+
 | Cavium         | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456        |
 +----------------+-----------------+-----------------+-----------------------------+
 | Cavium         | ThunderX Core   | #30115          | CAVIUM_ERRATUM_30115        |

drivers/irqchip/irq-gic-v3.c

@@ -34,6 +34,7 @@
 #define GICD_INT_NMI_PRI	(GICD_INT_DEF_PRI & ~0x80)
 
 #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996	(1ULL << 0)
+#define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539	(1ULL << 1)
 
 struct redist_region {
 	void __iomem		*redist_base;
@@ -1464,6 +1465,15 @@ static bool gic_enable_quirk_msm8996(void *data)
 	return true;
 }
 
+static bool gic_enable_quirk_cavium_38539(void *data)
+{
+	struct gic_chip_data *d = data;
+
+	d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539;
+
+	return true;
+}
+
 static bool gic_enable_quirk_hip06_07(void *data)
 {
 	struct gic_chip_data *d = data;
@@ -1502,6 +1512,19 @@ static const struct gic_quirk gic_quirks[] = {
 		.mask	= 0xffffffff,
 		.init	= gic_enable_quirk_hip06_07,
 	},
+	{
+		/*
+		 * Reserved register accesses generate a Synchronous
+		 * External Abort. This erratum applies to:
+		 * - ThunderX: CN88xx
+		 * - OCTEON TX: CN83xx, CN81xx
+		 * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
+		 */
+		.desc	= "GICv3: Cavium erratum 38539",
+		.iidr	= 0xa000034c,
+		.mask	= 0xe8f00fff,
+		.init	= gic_enable_quirk_cavium_38539,
+	},
 	{
 	}
 };
@@ -1577,7 +1600,12 @@ static int __init gic_init_bases(void __iomem *dist_base,
 	pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32);
 	pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR);
 
-	gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2);
+	/*
+	 * ThunderX1 explodes on reading GICD_TYPER2, in violation of the
+	 * architecture spec (which says that reserved registers are RES0).
+	 */
+	if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539))
+		gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2);
 
 	gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
 						 &gic_data);