mlx5: move affinity hints assignments to generic code
generic api takes care of spreading affinity similar to what mlx5 open coded (and even handles better asymmetric configurations). Ask the generic API to spread affinity for us, and feed him pre_vectors that do not participate in affinity settings (which is an improvement to what we had before). The affinity assignments should match what mlx5 tried to do earlier but now we do not set affinity to async, cmd and pages dedicated vectors. Also, remove mlx5e_get_cpu and introduce mlx5e_get_node (used for allocation purposes) and mlx5_get_vector_affinity (for indirection table construction) as they provide the needed information. Luckily, we have generic helpers to get cpumask and node given a irq vector. mlx5_get_vector_affinity will be used by mlx5_ib in a subsequent patch. Reviewed-by: Christoph Hellwig <hch@lst.de> Acked-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: Sagi Grimberg <sagi@grimberg.me> Signed-off-by: Doug Ledford <dledford@redhat.com>
This commit is contained in:
Sagi Grimberg
Doug Ledford
Родитель
a85e5474f4
Коммит
a435393aca
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@ -587,7 +587,6 @@ struct mlx5e_channel {
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struct mlx5_core_dev *mdev;
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struct mlx5e_tstamp *tstamp;
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int ix;
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int cpu;
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};
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struct mlx5e_channels {
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@ -71,6 +71,11 @@ struct mlx5e_channel_param {
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struct mlx5e_cq_param icosq_cq;
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};
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static int mlx5e_get_node(struct mlx5e_priv *priv, int ix)
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{
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return pci_irq_get_node(priv->mdev->pdev, MLX5_EQ_VEC_COMP_BASE + ix);
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}
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static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
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{
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return MLX5_CAP_GEN(mdev, striding_rq) &&
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@ -444,16 +449,17 @@ static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
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int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
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int mtt_sz = mlx5e_get_wqe_mtt_sz();
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int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
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int node = mlx5e_get_node(c->priv, c->ix);
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int i;
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rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
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GFP_KERNEL, cpu_to_node(c->cpu));
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GFP_KERNEL, node);
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if (!rq->mpwqe.info)
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goto err_out;
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/* We allocate more than mtt_sz as we will align the pointer */
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rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
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cpu_to_node(c->cpu));
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rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz,
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GFP_KERNEL, node);
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if (unlikely(!rq->mpwqe.mtt_no_align))
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goto err_free_wqe_info;
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@ -561,7 +567,7 @@ static int mlx5e_alloc_rq(struct mlx5e_channel *c,
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int err;
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int i;
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rqp->wq.db_numa_node = cpu_to_node(c->cpu);
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rqp->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
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err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
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&rq->wq_ctrl);
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@ -628,7 +634,8 @@ static int mlx5e_alloc_rq(struct mlx5e_channel *c,
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default: /* MLX5_WQ_TYPE_LINKED_LIST */
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rq->wqe.frag_info =
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kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
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GFP_KERNEL, cpu_to_node(c->cpu));
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GFP_KERNEL,
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mlx5e_get_node(c->priv, c->ix));
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if (!rq->wqe.frag_info) {
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err = -ENOMEM;
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goto err_rq_wq_destroy;
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@ -993,13 +1000,13 @@ static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
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sq->uar_map = mdev->mlx5e_res.bfreg.map;
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sq->min_inline_mode = params->tx_min_inline_mode;
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param->wq.db_numa_node = cpu_to_node(c->cpu);
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param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
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err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
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if (err)
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return err;
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sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
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err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
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err = mlx5e_alloc_xdpsq_db(sq, mlx5e_get_node(c->priv, c->ix));
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if (err)
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goto err_sq_wq_destroy;
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@ -1047,13 +1054,13 @@ static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
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sq->channel = c;
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sq->uar_map = mdev->mlx5e_res.bfreg.map;
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param->wq.db_numa_node = cpu_to_node(c->cpu);
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param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
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err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
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if (err)
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return err;
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sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
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err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
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err = mlx5e_alloc_icosq_db(sq, mlx5e_get_node(c->priv, c->ix));
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if (err)
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goto err_sq_wq_destroy;
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@ -1119,13 +1126,13 @@ static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
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if (MLX5_IPSEC_DEV(c->priv->mdev))
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set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
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param->wq.db_numa_node = cpu_to_node(c->cpu);
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param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
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err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
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if (err)
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return err;
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sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
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err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
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err = mlx5e_alloc_txqsq_db(sq, mlx5e_get_node(c->priv, c->ix));
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if (err)
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goto err_sq_wq_destroy;
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@ -1497,8 +1504,8 @@ static int mlx5e_alloc_cq(struct mlx5e_channel *c,
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struct mlx5_core_dev *mdev = c->priv->mdev;
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int err;
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param->wq.buf_numa_node = cpu_to_node(c->cpu);
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param->wq.db_numa_node = cpu_to_node(c->cpu);
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param->wq.buf_numa_node = mlx5e_get_node(c->priv, c->ix);
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param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
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param->eq_ix = c->ix;
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err = mlx5e_alloc_cq_common(mdev, param, cq);
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@ -1597,11 +1604,6 @@ static void mlx5e_close_cq(struct mlx5e_cq *cq)
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mlx5e_free_cq(cq);
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}
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static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
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{
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return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
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}
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static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
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struct mlx5e_params *params,
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struct mlx5e_channel_param *cparam)
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@ -1750,11 +1752,10 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
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{
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struct mlx5e_cq_moder icocq_moder = {0, 0};
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struct net_device *netdev = priv->netdev;
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int cpu = mlx5e_get_cpu(priv, ix);
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struct mlx5e_channel *c;
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int err;
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c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
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c = kzalloc_node(sizeof(*c), GFP_KERNEL, mlx5e_get_node(priv, ix));
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if (!c)
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return -ENOMEM;
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@ -1762,7 +1763,6 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
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c->mdev = priv->mdev;
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c->tstamp = &priv->tstamp;
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c->ix = ix;
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c->cpu = cpu;
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c->pdev = &priv->mdev->pdev->dev;
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c->netdev = priv->netdev;
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c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
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@ -1848,7 +1848,8 @@ static void mlx5e_activate_channel(struct mlx5e_channel *c)
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for (tc = 0; tc < c->num_tc; tc++)
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mlx5e_activate_txqsq(&c->sq[tc]);
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mlx5e_activate_rq(&c->rq);
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netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
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netif_set_xps_queue(c->netdev,
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mlx5_get_vector_affinity(c->priv->mdev, c->ix), c->ix);
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}
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static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
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@ -316,6 +316,9 @@ static int mlx5_alloc_irq_vectors(struct mlx5_core_dev *dev)
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{
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struct mlx5_priv *priv = &dev->priv;
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struct mlx5_eq_table *table = &priv->eq_table;
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struct irq_affinity irqdesc = {
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.pre_vectors = MLX5_EQ_VEC_COMP_BASE,
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};
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int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
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int nvec;
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@ -329,9 +332,10 @@ static int mlx5_alloc_irq_vectors(struct mlx5_core_dev *dev)
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if (!priv->irq_info)
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goto err_free_msix;
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nvec = pci_alloc_irq_vectors(dev->pdev,
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nvec = pci_alloc_irq_vectors_affinity(dev->pdev,
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MLX5_EQ_VEC_COMP_BASE + 1, nvec,
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PCI_IRQ_MSIX);
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PCI_IRQ_MSIX | PCI_IRQ_AFFINITY,
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&irqdesc);
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if (nvec < 0)
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return nvec;
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@ -605,63 +609,6 @@ u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev)
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return (u64)timer_l | (u64)timer_h1 << 32;
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}
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static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
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{
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struct mlx5_priv *priv = &mdev->priv;
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int irq = pci_irq_vector(mdev->pdev, MLX5_EQ_VEC_COMP_BASE + i);
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if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
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mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
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return -ENOMEM;
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}
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cpumask_set_cpu(cpumask_local_spread(i, priv->numa_node),
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priv->irq_info[i].mask);
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if (IS_ENABLED(CONFIG_SMP) &&
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irq_set_affinity_hint(irq, priv->irq_info[i].mask))
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mlx5_core_warn(mdev, "irq_set_affinity_hint failed, irq 0x%.4x", irq);
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return 0;
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}
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static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
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{
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struct mlx5_priv *priv = &mdev->priv;
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int irq = pci_irq_vector(mdev->pdev, MLX5_EQ_VEC_COMP_BASE + i);
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irq_set_affinity_hint(irq, NULL);
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free_cpumask_var(priv->irq_info[i].mask);
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}
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static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
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{
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int err;
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int i;
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for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
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err = mlx5_irq_set_affinity_hint(mdev, i);
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if (err)
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goto err_out;
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}
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return 0;
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err_out:
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for (i--; i >= 0; i--)
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mlx5_irq_clear_affinity_hint(mdev, i);
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return err;
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}
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static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
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{
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int i;
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for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
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mlx5_irq_clear_affinity_hint(mdev, i);
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}
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int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
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unsigned int *irqn)
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{
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@ -1134,12 +1081,6 @@ static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
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goto err_stop_eqs;
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}
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err = mlx5_irq_set_affinity_hints(dev);
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if (err) {
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dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
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goto err_affinity_hints;
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}
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err = mlx5_init_fs(dev);
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if (err) {
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dev_err(&pdev->dev, "Failed to init flow steering\n");
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@ -1199,9 +1140,6 @@ err_sriov:
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mlx5_cleanup_fs(dev);
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err_fs:
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mlx5_irq_clear_affinity_hints(dev);
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err_affinity_hints:
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free_comp_eqs(dev);
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err_stop_eqs:
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@ -1274,7 +1212,6 @@ static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
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mlx5_eswitch_detach(dev->priv.eswitch);
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#endif
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mlx5_cleanup_fs(dev);
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mlx5_irq_clear_affinity_hints(dev);
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free_comp_eqs(dev);
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mlx5_stop_eqs(dev);
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mlx5_put_uars_page(dev, priv->uar);
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@ -534,7 +534,6 @@ struct mlx5_core_sriov {
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};
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struct mlx5_irq_info {
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cpumask_var_t mask;
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char name[MLX5_MAX_IRQ_NAME];
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};
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@ -1184,4 +1183,10 @@ enum {
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MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
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};
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static inline const struct cpumask *
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mlx5_get_vector_affinity(struct mlx5_core_dev *dev, int vector)
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{
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return pci_irq_get_affinity(dev->pdev, MLX5_EQ_VEC_COMP_BASE + vector);
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}
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#endif /* MLX5_DRIVER_H */
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