cpufreq: exynos: Remove support for Exynos5440
The Exynos5440 is not actively developed, there are no development boards available and probably there are no real products with it. Remove wide-tree support for Exynos5440. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Krzysztof Kozlowski
Родитель
956698445d
Коммит
a443c1fc10
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@ -1,28 +0,0 @@
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Exynos5440 cpufreq driver
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-------------------
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Exynos5440 SoC cpufreq driver for CPU frequency scaling.
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Required properties:
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- interrupts: Interrupt to know the completion of cpu frequency change.
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- operating-points: Table of frequencies and voltage CPU could be transitioned into,
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in the decreasing order. Frequency should be in KHz units and voltage
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should be in microvolts.
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Optional properties:
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- clock-latency: Clock monitor latency in microsecond.
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All the required listed above must be defined under node cpufreq.
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Example:
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--------
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cpufreq@160000 {
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compatible = "samsung,exynos5440-cpufreq";
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reg = <0x160000 0x1000>;
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interrupts = <0 57 0>;
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operating-points = <
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1000000 975000
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800000 925000>;
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clock-latency = <100000>;
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};
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@ -71,20 +71,6 @@ config ARM_BRCMSTB_AVS_CPUFREQ
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Say Y, if you have a Broadcom SoC with AVS support for DFS or DVFS.
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config ARM_EXYNOS5440_CPUFREQ
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tristate "SAMSUNG EXYNOS5440"
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depends on SOC_EXYNOS5440
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depends on HAVE_CLK && OF
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select PM_OPP
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default y
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help
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This adds the CPUFreq driver for Samsung EXYNOS5440
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SoC. The nature of exynos5440 clock controller is
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different than previous exynos controllers so not using
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the common exynos framework.
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If in doubt, say N.
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config ARM_HIGHBANK_CPUFREQ
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tristate "Calxeda Highbank-based"
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depends on ARCH_HIGHBANK && CPUFREQ_DT && REGULATOR
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@ -56,7 +56,6 @@ obj-$(CONFIG_ARM_ARMADA_37XX_CPUFREQ) += armada-37xx-cpufreq.o
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obj-$(CONFIG_ARM_BRCMSTB_AVS_CPUFREQ) += brcmstb-avs-cpufreq.o
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obj-$(CONFIG_ACPI_CPPC_CPUFREQ) += cppc_cpufreq.o
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obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o
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obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o
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obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
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obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o
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obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o
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@ -1,452 +0,0 @@
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/*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Amit Daniel Kachhap <amit.daniel@samsung.com>
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*
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* EXYNOS5440 - CPU frequency scaling support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/cpu.h>
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#include <linux/cpufreq.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/pm_opp.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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/* Register definitions */
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#define XMU_DVFS_CTRL 0x0060
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#define XMU_PMU_P0_7 0x0064
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#define XMU_C0_3_PSTATE 0x0090
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#define XMU_P_LIMIT 0x00a0
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#define XMU_P_STATUS 0x00a4
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#define XMU_PMUEVTEN 0x00d0
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#define XMU_PMUIRQEN 0x00d4
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#define XMU_PMUIRQ 0x00d8
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/* PMU mask and shift definations */
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#define P_VALUE_MASK 0x7
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#define XMU_DVFS_CTRL_EN_SHIFT 0
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#define P0_7_CPUCLKDEV_SHIFT 21
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#define P0_7_CPUCLKDEV_MASK 0x7
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#define P0_7_ATBCLKDEV_SHIFT 18
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#define P0_7_ATBCLKDEV_MASK 0x7
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#define P0_7_CSCLKDEV_SHIFT 15
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#define P0_7_CSCLKDEV_MASK 0x7
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#define P0_7_CPUEMA_SHIFT 28
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#define P0_7_CPUEMA_MASK 0xf
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#define P0_7_L2EMA_SHIFT 24
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#define P0_7_L2EMA_MASK 0xf
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#define P0_7_VDD_SHIFT 8
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#define P0_7_VDD_MASK 0x7f
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#define P0_7_FREQ_SHIFT 0
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#define P0_7_FREQ_MASK 0xff
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#define C0_3_PSTATE_VALID_SHIFT 8
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#define C0_3_PSTATE_CURR_SHIFT 4
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#define C0_3_PSTATE_NEW_SHIFT 0
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#define PSTATE_CHANGED_EVTEN_SHIFT 0
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#define PSTATE_CHANGED_IRQEN_SHIFT 0
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#define PSTATE_CHANGED_SHIFT 0
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/* some constant values for clock divider calculation */
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#define CPU_DIV_FREQ_MAX 500
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#define CPU_DBG_FREQ_MAX 375
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#define CPU_ATB_FREQ_MAX 500
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#define PMIC_LOW_VOLT 0x30
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#define PMIC_HIGH_VOLT 0x28
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#define CPUEMA_HIGH 0x2
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#define CPUEMA_MID 0x4
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#define CPUEMA_LOW 0x7
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#define L2EMA_HIGH 0x1
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#define L2EMA_MID 0x3
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#define L2EMA_LOW 0x4
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#define DIV_TAB_MAX 2
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/* frequency unit is 20MHZ */
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#define FREQ_UNIT 20
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#define MAX_VOLTAGE 1550000 /* In microvolt */
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#define VOLTAGE_STEP 12500 /* In microvolt */
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#define CPUFREQ_NAME "exynos5440_dvfs"
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#define DEF_TRANS_LATENCY 100000
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enum cpufreq_level_index {
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L0, L1, L2, L3, L4,
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L5, L6, L7, L8, L9,
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};
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#define CPUFREQ_LEVEL_END (L7 + 1)
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struct exynos_dvfs_data {
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void __iomem *base;
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struct resource *mem;
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int irq;
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struct clk *cpu_clk;
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unsigned int latency;
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struct cpufreq_frequency_table *freq_table;
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unsigned int freq_count;
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struct device *dev;
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bool dvfs_enabled;
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struct work_struct irq_work;
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};
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static struct exynos_dvfs_data *dvfs_info;
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static DEFINE_MUTEX(cpufreq_lock);
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static struct cpufreq_freqs freqs;
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static int init_div_table(void)
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{
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struct cpufreq_frequency_table *pos, *freq_tbl = dvfs_info->freq_table;
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unsigned int tmp, clk_div, ema_div, freq, volt_id, idx;
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struct dev_pm_opp *opp;
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cpufreq_for_each_entry_idx(pos, freq_tbl, idx) {
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opp = dev_pm_opp_find_freq_exact(dvfs_info->dev,
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pos->frequency * 1000, true);
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if (IS_ERR(opp)) {
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dev_err(dvfs_info->dev,
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"failed to find valid OPP for %u KHZ\n",
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pos->frequency);
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return PTR_ERR(opp);
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}
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freq = pos->frequency / 1000; /* In MHZ */
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clk_div = ((freq / CPU_DIV_FREQ_MAX) & P0_7_CPUCLKDEV_MASK)
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<< P0_7_CPUCLKDEV_SHIFT;
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clk_div |= ((freq / CPU_ATB_FREQ_MAX) & P0_7_ATBCLKDEV_MASK)
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<< P0_7_ATBCLKDEV_SHIFT;
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clk_div |= ((freq / CPU_DBG_FREQ_MAX) & P0_7_CSCLKDEV_MASK)
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<< P0_7_CSCLKDEV_SHIFT;
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/* Calculate EMA */
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volt_id = dev_pm_opp_get_voltage(opp);
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volt_id = (MAX_VOLTAGE - volt_id) / VOLTAGE_STEP;
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if (volt_id < PMIC_HIGH_VOLT) {
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ema_div = (CPUEMA_HIGH << P0_7_CPUEMA_SHIFT) |
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(L2EMA_HIGH << P0_7_L2EMA_SHIFT);
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} else if (volt_id > PMIC_LOW_VOLT) {
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ema_div = (CPUEMA_LOW << P0_7_CPUEMA_SHIFT) |
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(L2EMA_LOW << P0_7_L2EMA_SHIFT);
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} else {
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ema_div = (CPUEMA_MID << P0_7_CPUEMA_SHIFT) |
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(L2EMA_MID << P0_7_L2EMA_SHIFT);
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}
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tmp = (clk_div | ema_div | (volt_id << P0_7_VDD_SHIFT)
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| ((freq / FREQ_UNIT) << P0_7_FREQ_SHIFT));
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__raw_writel(tmp, dvfs_info->base + XMU_PMU_P0_7 + 4 * idx);
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dev_pm_opp_put(opp);
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}
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return 0;
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}
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static void exynos_enable_dvfs(unsigned int cur_frequency)
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{
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unsigned int tmp, cpu;
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struct cpufreq_frequency_table *freq_table = dvfs_info->freq_table;
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struct cpufreq_frequency_table *pos;
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/* Disable DVFS */
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__raw_writel(0, dvfs_info->base + XMU_DVFS_CTRL);
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/* Enable PSTATE Change Event */
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tmp = __raw_readl(dvfs_info->base + XMU_PMUEVTEN);
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tmp |= (1 << PSTATE_CHANGED_EVTEN_SHIFT);
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__raw_writel(tmp, dvfs_info->base + XMU_PMUEVTEN);
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/* Enable PSTATE Change IRQ */
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tmp = __raw_readl(dvfs_info->base + XMU_PMUIRQEN);
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tmp |= (1 << PSTATE_CHANGED_IRQEN_SHIFT);
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__raw_writel(tmp, dvfs_info->base + XMU_PMUIRQEN);
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/* Set initial performance index */
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cpufreq_for_each_entry(pos, freq_table)
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if (pos->frequency == cur_frequency)
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break;
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if (pos->frequency == CPUFREQ_TABLE_END) {
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dev_crit(dvfs_info->dev, "Boot up frequency not supported\n");
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/* Assign the highest frequency */
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pos = freq_table;
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cur_frequency = pos->frequency;
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}
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dev_info(dvfs_info->dev, "Setting dvfs initial frequency = %uKHZ",
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cur_frequency);
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for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) {
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tmp = __raw_readl(dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4);
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tmp &= ~(P_VALUE_MASK << C0_3_PSTATE_NEW_SHIFT);
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tmp |= ((pos - freq_table) << C0_3_PSTATE_NEW_SHIFT);
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__raw_writel(tmp, dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4);
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}
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/* Enable DVFS */
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__raw_writel(1 << XMU_DVFS_CTRL_EN_SHIFT,
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dvfs_info->base + XMU_DVFS_CTRL);
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}
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static int exynos_target(struct cpufreq_policy *policy, unsigned int index)
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{
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unsigned int tmp;
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int i;
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struct cpufreq_frequency_table *freq_table = dvfs_info->freq_table;
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mutex_lock(&cpufreq_lock);
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freqs.old = policy->cur;
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freqs.new = freq_table[index].frequency;
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cpufreq_freq_transition_begin(policy, &freqs);
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/* Set the target frequency in all C0_3_PSTATE register */
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for_each_cpu(i, policy->cpus) {
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tmp = __raw_readl(dvfs_info->base + XMU_C0_3_PSTATE + i * 4);
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tmp &= ~(P_VALUE_MASK << C0_3_PSTATE_NEW_SHIFT);
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tmp |= (index << C0_3_PSTATE_NEW_SHIFT);
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__raw_writel(tmp, dvfs_info->base + XMU_C0_3_PSTATE + i * 4);
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}
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mutex_unlock(&cpufreq_lock);
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return 0;
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}
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static void exynos_cpufreq_work(struct work_struct *work)
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{
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unsigned int cur_pstate, index;
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struct cpufreq_policy *policy = cpufreq_cpu_get(0); /* boot CPU */
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struct cpufreq_frequency_table *freq_table = dvfs_info->freq_table;
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/* Ensure we can access cpufreq structures */
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if (unlikely(dvfs_info->dvfs_enabled == false))
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goto skip_work;
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mutex_lock(&cpufreq_lock);
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freqs.old = policy->cur;
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cur_pstate = __raw_readl(dvfs_info->base + XMU_P_STATUS);
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if (cur_pstate >> C0_3_PSTATE_VALID_SHIFT & 0x1)
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index = (cur_pstate >> C0_3_PSTATE_CURR_SHIFT) & P_VALUE_MASK;
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else
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index = (cur_pstate >> C0_3_PSTATE_NEW_SHIFT) & P_VALUE_MASK;
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if (likely(index < dvfs_info->freq_count)) {
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freqs.new = freq_table[index].frequency;
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} else {
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dev_crit(dvfs_info->dev, "New frequency out of range\n");
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freqs.new = freqs.old;
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}
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cpufreq_freq_transition_end(policy, &freqs, 0);
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cpufreq_cpu_put(policy);
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mutex_unlock(&cpufreq_lock);
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skip_work:
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enable_irq(dvfs_info->irq);
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}
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static irqreturn_t exynos_cpufreq_irq(int irq, void *id)
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{
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unsigned int tmp;
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tmp = __raw_readl(dvfs_info->base + XMU_PMUIRQ);
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if (tmp >> PSTATE_CHANGED_SHIFT & 0x1) {
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__raw_writel(tmp, dvfs_info->base + XMU_PMUIRQ);
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disable_irq_nosync(irq);
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schedule_work(&dvfs_info->irq_work);
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}
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return IRQ_HANDLED;
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}
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static void exynos_sort_descend_freq_table(void)
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{
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struct cpufreq_frequency_table *freq_tbl = dvfs_info->freq_table;
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int i = 0, index;
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unsigned int tmp_freq;
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/*
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* Exynos5440 clock controller state logic expects the cpufreq table to
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* be in descending order. But the OPP library constructs the table in
|
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* ascending order. So to make the table descending we just need to
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* swap the i element with the N - i element.
|
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*/
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for (i = 0; i < dvfs_info->freq_count / 2; i++) {
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index = dvfs_info->freq_count - i - 1;
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tmp_freq = freq_tbl[i].frequency;
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freq_tbl[i].frequency = freq_tbl[index].frequency;
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freq_tbl[index].frequency = tmp_freq;
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}
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}
|
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|
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static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy)
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{
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policy->clk = dvfs_info->cpu_clk;
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return cpufreq_generic_init(policy, dvfs_info->freq_table,
|
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dvfs_info->latency);
|
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}
|
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|
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static struct cpufreq_driver exynos_driver = {
|
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.flags = CPUFREQ_STICKY | CPUFREQ_ASYNC_NOTIFICATION |
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CPUFREQ_NEED_INITIAL_FREQ_CHECK,
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.verify = cpufreq_generic_frequency_table_verify,
|
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.target_index = exynos_target,
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.get = cpufreq_generic_get,
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.init = exynos_cpufreq_cpu_init,
|
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.name = CPUFREQ_NAME,
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.attr = cpufreq_generic_attr,
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};
|
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|
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static const struct of_device_id exynos_cpufreq_match[] = {
|
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{
|
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.compatible = "samsung,exynos5440-cpufreq",
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},
|
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{},
|
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};
|
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MODULE_DEVICE_TABLE(of, exynos_cpufreq_match);
|
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|
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static int exynos_cpufreq_probe(struct platform_device *pdev)
|
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{
|
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int ret = -EINVAL;
|
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struct device_node *np;
|
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struct resource res;
|
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unsigned int cur_frequency;
|
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|
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np = pdev->dev.of_node;
|
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if (!np)
|
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return -ENODEV;
|
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|
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dvfs_info = devm_kzalloc(&pdev->dev, sizeof(*dvfs_info), GFP_KERNEL);
|
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if (!dvfs_info) {
|
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ret = -ENOMEM;
|
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goto err_put_node;
|
||||
}
|
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|
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dvfs_info->dev = &pdev->dev;
|
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|
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ret = of_address_to_resource(np, 0, &res);
|
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if (ret)
|
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goto err_put_node;
|
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|
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dvfs_info->base = devm_ioremap_resource(dvfs_info->dev, &res);
|
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if (IS_ERR(dvfs_info->base)) {
|
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ret = PTR_ERR(dvfs_info->base);
|
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goto err_put_node;
|
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}
|
||||
|
||||
dvfs_info->irq = irq_of_parse_and_map(np, 0);
|
||||
if (!dvfs_info->irq) {
|
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dev_err(dvfs_info->dev, "No cpufreq irq found\n");
|
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ret = -ENODEV;
|
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goto err_put_node;
|
||||
}
|
||||
|
||||
ret = dev_pm_opp_of_add_table(dvfs_info->dev);
|
||||
if (ret) {
|
||||
dev_err(dvfs_info->dev, "failed to init OPP table: %d\n", ret);
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goto err_put_node;
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}
|
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|
||||
ret = dev_pm_opp_init_cpufreq_table(dvfs_info->dev,
|
||||
&dvfs_info->freq_table);
|
||||
if (ret) {
|
||||
dev_err(dvfs_info->dev,
|
||||
"failed to init cpufreq table: %d\n", ret);
|
||||
goto err_free_opp;
|
||||
}
|
||||
dvfs_info->freq_count = dev_pm_opp_get_opp_count(dvfs_info->dev);
|
||||
exynos_sort_descend_freq_table();
|
||||
|
||||
if (of_property_read_u32(np, "clock-latency", &dvfs_info->latency))
|
||||
dvfs_info->latency = DEF_TRANS_LATENCY;
|
||||
|
||||
dvfs_info->cpu_clk = devm_clk_get(dvfs_info->dev, "armclk");
|
||||
if (IS_ERR(dvfs_info->cpu_clk)) {
|
||||
dev_err(dvfs_info->dev, "Failed to get cpu clock\n");
|
||||
ret = PTR_ERR(dvfs_info->cpu_clk);
|
||||
goto err_free_table;
|
||||
}
|
||||
|
||||
cur_frequency = clk_get_rate(dvfs_info->cpu_clk);
|
||||
if (!cur_frequency) {
|
||||
dev_err(dvfs_info->dev, "Failed to get clock rate\n");
|
||||
ret = -EINVAL;
|
||||
goto err_free_table;
|
||||
}
|
||||
cur_frequency /= 1000;
|
||||
|
||||
INIT_WORK(&dvfs_info->irq_work, exynos_cpufreq_work);
|
||||
ret = devm_request_irq(dvfs_info->dev, dvfs_info->irq,
|
||||
exynos_cpufreq_irq, IRQF_TRIGGER_NONE,
|
||||
CPUFREQ_NAME, dvfs_info);
|
||||
if (ret) {
|
||||
dev_err(dvfs_info->dev, "Failed to register IRQ\n");
|
||||
goto err_free_table;
|
||||
}
|
||||
|
||||
ret = init_div_table();
|
||||
if (ret) {
|
||||
dev_err(dvfs_info->dev, "Failed to initialise div table\n");
|
||||
goto err_free_table;
|
||||
}
|
||||
|
||||
exynos_enable_dvfs(cur_frequency);
|
||||
ret = cpufreq_register_driver(&exynos_driver);
|
||||
if (ret) {
|
||||
dev_err(dvfs_info->dev,
|
||||
"%s: failed to register cpufreq driver\n", __func__);
|
||||
goto err_free_table;
|
||||
}
|
||||
|
||||
of_node_put(np);
|
||||
dvfs_info->dvfs_enabled = true;
|
||||
return 0;
|
||||
|
||||
err_free_table:
|
||||
dev_pm_opp_free_cpufreq_table(dvfs_info->dev, &dvfs_info->freq_table);
|
||||
err_free_opp:
|
||||
dev_pm_opp_of_remove_table(dvfs_info->dev);
|
||||
err_put_node:
|
||||
of_node_put(np);
|
||||
dev_err(&pdev->dev, "%s: failed initialization\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int exynos_cpufreq_remove(struct platform_device *pdev)
|
||||
{
|
||||
cpufreq_unregister_driver(&exynos_driver);
|
||||
dev_pm_opp_free_cpufreq_table(dvfs_info->dev, &dvfs_info->freq_table);
|
||||
dev_pm_opp_of_remove_table(dvfs_info->dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver exynos_cpufreq_platdrv = {
|
||||
.driver = {
|
||||
.name = "exynos5440-cpufreq",
|
||||
.of_match_table = exynos_cpufreq_match,
|
||||
},
|
||||
.probe = exynos_cpufreq_probe,
|
||||
.remove = exynos_cpufreq_remove,
|
||||
};
|
||||
module_platform_driver(exynos_cpufreq_platdrv);
|
||||
|
||||
MODULE_AUTHOR("Amit Daniel Kachhap <amit.daniel@samsung.com>");
|
||||
MODULE_DESCRIPTION("Exynos5440 cpufreq driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
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