iommu/arm-smmu: use mutex instead of spinlock for locking page tables
When creating IO mappings, we lazily allocate our page tables using the standard, non-atomic allocator functions. This presents us with a problem, since our page tables are protected with a spinlock. This patch reworks the smmu_domain lock to use a mutex instead of a spinlock. iova_to_phys is then reworked so that it only reads the page tables, and can run in a lockless fashion, leaving the mutex to guard against concurrent mapping threads. Cc: <stable@vger.kernel.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
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dc1ccc4815
Коммит
a44a9791e7
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@ -392,7 +392,7 @@ struct arm_smmu_domain {
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struct arm_smmu_cfg root_cfg;
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phys_addr_t output_mask;
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spinlock_t lock;
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struct mutex lock;
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};
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static DEFINE_SPINLOCK(arm_smmu_devices_lock);
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@ -900,7 +900,7 @@ static int arm_smmu_domain_init(struct iommu_domain *domain)
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goto out_free_domain;
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smmu_domain->root_cfg.pgd = pgd;
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spin_lock_init(&smmu_domain->lock);
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mutex_init(&smmu_domain->lock);
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domain->priv = smmu_domain;
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return 0;
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@ -1137,7 +1137,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
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* Sanity check the domain. We don't currently support domains
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* that cross between different SMMU chains.
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*/
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spin_lock(&smmu_domain->lock);
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mutex_lock(&smmu_domain->lock);
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if (!smmu_domain->leaf_smmu) {
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/* Now that we have a master, we can finalise the domain */
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ret = arm_smmu_init_domain_context(domain, dev);
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@ -1152,7 +1152,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
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dev_name(device_smmu->dev));
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goto err_unlock;
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}
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spin_unlock(&smmu_domain->lock);
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mutex_unlock(&smmu_domain->lock);
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/* Looks ok, so add the device to the domain */
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master = find_smmu_master(smmu_domain->leaf_smmu, dev->of_node);
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@ -1162,7 +1162,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
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return arm_smmu_domain_add_master(smmu_domain, master);
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err_unlock:
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spin_unlock(&smmu_domain->lock);
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mutex_unlock(&smmu_domain->lock);
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return ret;
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}
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@ -1394,7 +1394,7 @@ static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
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if (paddr & ~output_mask)
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return -ERANGE;
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spin_lock(&smmu_domain->lock);
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mutex_lock(&smmu_domain->lock);
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pgd += pgd_index(iova);
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end = iova + size;
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do {
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@ -1410,7 +1410,7 @@ static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
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} while (pgd++, iova != end);
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out_unlock:
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spin_unlock(&smmu_domain->lock);
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mutex_unlock(&smmu_domain->lock);
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/* Ensure new page tables are visible to the hardware walker */
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if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
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@ -1449,44 +1449,34 @@ static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
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static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
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dma_addr_t iova)
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{
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pgd_t *pgd;
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pud_t *pud;
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pmd_t *pmd;
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pte_t *pte;
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pgd_t *pgdp, pgd;
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pud_t pud;
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pmd_t pmd;
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pte_t pte;
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struct arm_smmu_domain *smmu_domain = domain->priv;
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struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
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struct arm_smmu_device *smmu = root_cfg->smmu;
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spin_lock(&smmu_domain->lock);
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pgd = root_cfg->pgd;
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if (!pgd)
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goto err_unlock;
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pgdp = root_cfg->pgd;
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if (!pgdp)
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return 0;
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pgd += pgd_index(iova);
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if (pgd_none_or_clear_bad(pgd))
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goto err_unlock;
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pgd = *(pgdp + pgd_index(iova));
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if (pgd_none(pgd))
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return 0;
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pud = pud_offset(pgd, iova);
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if (pud_none_or_clear_bad(pud))
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goto err_unlock;
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pud = *pud_offset(&pgd, iova);
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if (pud_none(pud))
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return 0;
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pmd = pmd_offset(pud, iova);
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if (pmd_none_or_clear_bad(pmd))
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goto err_unlock;
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pmd = *pmd_offset(&pud, iova);
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if (pmd_none(pmd))
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return 0;
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pte = pmd_page_vaddr(*pmd) + pte_index(iova);
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pte = *(pmd_page_vaddr(pmd) + pte_index(iova));
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if (pte_none(pte))
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goto err_unlock;
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return 0;
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spin_unlock(&smmu_domain->lock);
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return __pfn_to_phys(pte_pfn(*pte)) | (iova & ~PAGE_MASK);
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err_unlock:
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spin_unlock(&smmu_domain->lock);
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dev_warn(smmu->dev,
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"invalid (corrupt?) page tables detected for iova 0x%llx\n",
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(unsigned long long)iova);
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return -EINVAL;
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return __pfn_to_phys(pte_pfn(pte)) | (iova & ~PAGE_MASK);
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}
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static int arm_smmu_domain_has_cap(struct iommu_domain *domain,
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