sh: Reworked SH7780 PCI initialization.
This consolidates the PCI initialization code for all of the pci-sh7780 users, and sets up the memory window dynamically as opposed to using hardcoded window positions. A number of bugs were fixed at the same time, including the PIO handling and master abort timeout settings being incorrect. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
Родитель
9762528f37
Коммит
a45635dfb0
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@ -22,15 +22,3 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
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{
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return irq_tab[slot];
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}
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int pci_fixup_pcic(struct pci_channel *chan)
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{
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pci_write_reg(chan, 0x000043ff, SH4_PCIINTM);
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pci_write_reg(chan, 0x00000000, SH7780_PCIIBAR);
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pci_write_reg(chan, 0x08000000, SH7780_PCICSCR0);
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pci_write_reg(chan, 0x0000001b, SH7780_PCICSAR0);
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pci_write_reg(chan, 0xfd000000, SH7780_PCICSCR1);
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pci_write_reg(chan, 0x0000000f, SH7780_PCICSAR1);
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return 0;
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}
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@ -31,22 +31,3 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
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{
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return sdk7780_irq_tab[pin-1][slot];
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}
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int pci_fixup_pcic(struct pci_channel *chan)
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{
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/* Enable all interrupts, so we know what to fix */
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pci_write_reg(chan, 0x0000C3FF, SH7780_PCIIMR);
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/* Set up standard PCI config registers */
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pci_write_reg(chan, 0x08000000, SH7780_PCIMBAR0); /* PCI */
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pci_write_reg(chan, 0x08000000, SH4_PCILAR0); /* SHwy */
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pci_write_reg(chan, 0x07F00001, SH4_PCILSR0); /* size 128M w/ MBAR */
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pci_write_reg(chan, 0x00000000, SH7780_PCIMBAR1);
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pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
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pci_write_reg(chan, 0x00000000, SH4_PCILSR1);
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pci_write_reg(chan, 0xAB000801, SH7780_PCIIBAR);
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pci_write_reg(chan, 0xA5000C01, SH4_PCICR);
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return 0;
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}
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@ -49,6 +49,17 @@
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#define SH4_PCIINT_MWPD 0x00000002 /* Master Write PERR Detect */
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#define SH4_PCIINT_MRPD 0x00000001 /* Master Read PERR Detect */
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#define SH4_PCIINTM 0x118 /* PCI Interrupt Mask */
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#define SH4_PCIINTM_TTADIM BIT(14) /* Target-target abort interrupt */
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#define SH4_PCIINTM_TMTOIM BIT(9) /* Target retry timeout */
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#define SH4_PCIINTM_MDEIM BIT(8) /* Master function disable error */
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#define SH4_PCIINTM_APEDIM BIT(7) /* Address parity error detection */
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#define SH4_PCIINTM_SDIM BIT(6) /* SERR detection */
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#define SH4_PCIINTM_DPEITWM BIT(5) /* Data parity error for target write */
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#define SH4_PCIINTM_PEDITRM BIT(4) /* PERR detection for target read */
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#define SH4_PCIINTM_TADIMM BIT(3) /* Target abort for master */
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#define SH4_PCIINTM_MADIMM BIT(2) /* Master abort for master */
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#define SH4_PCIINTM_MWPDIM BIT(1) /* Master write data parity error */
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#define SH4_PCIINTM_MRDPEIM BIT(0) /* Master read data parity error */
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#define SH4_PCIALR 0x11C /* Error Address Register */
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#define SH4_PCICLR 0x120 /* Error Command/Data */
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#define SH4_PCICLR_MPIO 0x80000000
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@ -61,7 +72,7 @@
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#define SH4_PCIAINT 0x130 /* Arbiter Interrupt Register */
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#define SH4_PCIAINT_MBKN 0x00002000 /* Master Broken Interrupt */
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#define SH4_PCIAINT_TBTO 0x00001000 /* Target Bus Time Out */
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#define SH4_PCIAINT_MBTO 0x00001000 /* Master Bus Time Out */
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#define SH4_PCIAINT_MBTO 0x00000800 /* Master Bus Time Out */
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#define SH4_PCIAINT_TABT 0x00000008 /* Target Abort */
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#define SH4_PCIAINT_MABT 0x00000004 /* Master Abort */
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#define SH4_PCIAINT_RDPE 0x00000002 /* Read Data Parity Error */
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@ -1,7 +1,7 @@
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/*
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* Low-Level PCI Support for the SH7780
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*
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* Copyright (C) 2005 - 2009 Paul Mundt
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* Copyright (C) 2005 - 2010 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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@ -14,11 +14,13 @@
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include "pci-sh4.h"
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#include <asm/mmu.h>
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#include <asm/sizes.h>
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static struct resource sh7785_io_resource = {
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.name = "SH7785_IO",
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.start = SH7780_PCI_IO_BASE,
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.end = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1,
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.start = 0x1000,
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.end = SH7780_PCI_IO_SIZE - 1,
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.flags = IORESOURCE_IO
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};
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@ -38,25 +40,14 @@ static struct pci_channel sh7780_pci_controller = {
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.io_map_base = SH7780_PCI_IO_BASE,
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};
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static struct sh4_pci_address_map sh7780_pci_map = {
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.window0 = {
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#if defined(CONFIG_32BIT)
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.base = SH7780_32BIT_DDR_BASE_ADDR,
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.size = 0x40000000,
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#else
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.base = SH7780_CS0_BASE_ADDR,
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.size = 0x20000000,
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#endif
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},
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};
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static int __init sh7780_pci_init(void)
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{
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struct pci_channel *chan = &sh7780_pci_controller;
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phys_addr_t memphys;
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size_t memsize;
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unsigned int id;
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const char *type = NULL;
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const char *type;
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int ret;
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u32 word;
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printk(KERN_NOTICE "PCI: Starting intialization.\n");
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@ -65,17 +56,24 @@ static int __init sh7780_pci_init(void)
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/* Enable CPU access to the PCIC registers. */
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__raw_writel(PCIECR_ENBL, PCIECR);
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id = __raw_readw(chan->reg_base + SH7780_PCIVID);
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if (id != SH7780_VENDOR_ID) {
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/* Reset */
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__raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_PRST,
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chan->reg_base + SH4_PCICR);
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/* Wait for it to come back up.. */
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mdelay(100);
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id = __raw_readw(chan->reg_base + PCI_VENDOR_ID);
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if (id != PCI_VENDOR_ID_RENESAS) {
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printk(KERN_ERR "PCI: Unknown vendor ID 0x%04x.\n", id);
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return -ENODEV;
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}
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id = __raw_readw(chan->reg_base + SH7780_PCIDID);
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type = (id == SH7763_DEVICE_ID) ? "SH7763" :
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(id == SH7780_DEVICE_ID) ? "SH7780" :
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(id == SH7781_DEVICE_ID) ? "SH7781" :
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(id == SH7785_DEVICE_ID) ? "SH7785" :
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id = __raw_readw(chan->reg_base + PCI_DEVICE_ID);
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type = (id == PCI_DEVICE_ID_RENESAS_SH7763) ? "SH7763" :
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(id == PCI_DEVICE_ID_RENESAS_SH7780) ? "SH7780" :
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(id == PCI_DEVICE_ID_RENESAS_SH7781) ? "SH7781" :
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(id == PCI_DEVICE_ID_RENESAS_SH7785) ? "SH7785" :
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NULL;
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if (unlikely(!type)) {
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printk(KERN_ERR "PCI: Found an unsupported Renesas host "
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@ -85,59 +83,78 @@ static int __init sh7780_pci_init(void)
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printk(KERN_NOTICE "PCI: Found a Renesas %s host "
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"controller, revision %d.\n", type,
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__raw_readb(chan->reg_base + SH7780_PCIRID));
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__raw_readb(chan->reg_base + PCI_REVISION_ID));
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if ((ret = sh4_pci_check_direct(chan)) != 0)
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return ret;
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/*
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* Set the class and sub-class codes.
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* Now throw it in to register initialization mode and
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* start the real work.
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*/
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__raw_writeb(PCI_CLASS_BRIDGE_HOST >> 8,
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chan->reg_base + SH7780_PCIBCC);
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__raw_writeb(PCI_CLASS_BRIDGE_HOST & 0xff,
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chan->reg_base + SH7780_PCISUB);
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__raw_writel(SH4_PCICR_PREFIX, chan->reg_base + SH4_PCICR);
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memphys = __pa(memory_start);
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memsize = memory_end - memory_start;
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/*
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* Set IO and Mem windows to local address
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* Make PCI and local address the same for easy 1 to 1 mapping
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*/
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pci_write_reg(chan, sh7780_pci_map.window0.size - 0xfffff, SH4_PCILSR0);
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/* Set the values on window 0 PCI config registers */
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pci_write_reg(chan, sh7780_pci_map.window0.base, SH4_PCILAR0);
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pci_write_reg(chan, sh7780_pci_map.window0.base, SH7780_PCIMBAR0);
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__raw_writel(0, chan->reg_base + PCI_BASE_ADDRESS_0);
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pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
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__raw_writel(memphys, chan->reg_base + SH4_PCILAR0);
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__raw_writel((memsize - 1) << 9 | 1,
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chan->reg_base + SH4_PCILSR0);
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/* Set up standard PCI config registers */
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__raw_writew(0xFB00, chan->reg_base + SH7780_PCISTATUS);
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__raw_writew(0x0047, chan->reg_base + SH7780_PCICMD);
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__raw_writew(0x1912, chan->reg_base + SH7780_PCISVID);
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__raw_writew(0x0001, chan->reg_base + SH7780_PCISID);
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/* Clear out PCI arbiter IRQs */
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__raw_writel(0, chan->reg_base + SH4_PCIAINT);
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__raw_writeb(0x00, chan->reg_base + SH7780_PCIPIF);
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/* Unmask all of the arbiter IRQs. */
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__raw_writel(SH4_PCIAINT_MBKN | SH4_PCIAINT_TBTO | SH4_PCIAINT_MBTO | \
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SH4_PCIAINT_TABT | SH4_PCIAINT_MABT | SH4_PCIAINT_RDPE | \
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SH4_PCIAINT_WDPE, chan->reg_base + SH4_PCIAINTM);
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/* Apply any last-minute PCIC fixups */
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pci_fixup_pcic(chan);
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/* Clear all error conditions */
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__raw_writew(PCI_STATUS_DETECTED_PARITY | \
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PCI_STATUS_SIG_SYSTEM_ERROR | \
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PCI_STATUS_REC_MASTER_ABORT | \
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PCI_STATUS_REC_TARGET_ABORT | \
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PCI_STATUS_SIG_TARGET_ABORT | \
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PCI_STATUS_PARITY, chan->reg_base + PCI_STATUS);
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pci_write_reg(chan, 0xfd000000, SH7780_PCIMBR0);
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pci_write_reg(chan, 0x00fc0000, SH7780_PCIMBMR0);
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__raw_writew(PCI_COMMAND_SERR | PCI_COMMAND_WAIT | \
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PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | \
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PCI_COMMAND_MEMORY, chan->reg_base + PCI_COMMAND);
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#ifdef CONFIG_32BIT
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pci_write_reg(chan, 0xc0000000, SH7780_PCIMBR2);
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pci_write_reg(chan, 0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);
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#endif
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/* Unmask all of the PCI IRQs */
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__raw_writel(SH4_PCIINTM_TTADIM | SH4_PCIINTM_TMTOIM | \
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SH4_PCIINTM_MDEIM | SH4_PCIINTM_APEDIM | \
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SH4_PCIINTM_SDIM | SH4_PCIINTM_DPEITWM | \
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SH4_PCIINTM_PEDITRM | SH4_PCIINTM_TADIMM | \
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SH4_PCIINTM_MADIMM | SH4_PCIINTM_MWPDIM | \
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SH4_PCIINTM_MRDPEIM, chan->reg_base + SH4_PCIINTM);
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/* Set IOBR for windows containing area specified in pci.h */
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pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE-1),
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SH7780_PCIIOBR);
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pci_write_reg(chan, ((SH7780_PCI_IO_SIZE-1) & (7<<18)),
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SH7780_PCIIOBMR);
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/*
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* Disable the cache snoop controller for non-coherent DMA.
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*/
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__raw_writel(0, chan->reg_base + SH7780_PCICSCR0);
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__raw_writel(0, chan->reg_base + SH7780_PCICSAR0);
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__raw_writel(0, chan->reg_base + SH7780_PCICSCR1);
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__raw_writel(0, chan->reg_base + SH7780_PCICSAR1);
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/* SH7780 init done, set central function init complete */
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/* use round robin mode to stop a device starving/overruning */
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word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO;
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pci_write_reg(chan, word, SH4_PCICR);
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__raw_writel(0xfd000000, chan->reg_base + SH7780_PCIMBR0);
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__raw_writel(0x00fc0000, chan->reg_base + SH7780_PCIMBMR0);
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__raw_writel(0, chan->reg_base + SH7780_PCIIOBR);
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__raw_writel(0, chan->reg_base + SH7780_PCIIOBMR);
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/*
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* Initialization mode complete, release the control register and
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* enable round robin mode to stop device overruns/starvation.
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*/
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__raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO,
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chan->reg_base + SH4_PCICR);
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register_pci_controller(chan);
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@ -12,12 +12,11 @@
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#ifndef _PCI_SH7780_H_
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#define _PCI_SH7780_H_
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/* Platform Specific Values */
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#define SH7780_VENDOR_ID 0x1912
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#define SH7781_DEVICE_ID 0x0001
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#define SH7780_DEVICE_ID 0x0002
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#define SH7763_DEVICE_ID 0x0004
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#define SH7785_DEVICE_ID 0x0007
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#define PCI_VENDOR_ID_RENESAS 0x1912
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#define PCI_DEVICE_ID_RENESAS_SH7781 0x0001
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#define PCI_DEVICE_ID_RENESAS_SH7780 0x0002
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#define PCI_DEVICE_ID_RENESAS_SH7763 0x0004
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#define PCI_DEVICE_ID_RENESAS_SH7785 0x0007
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/* SH7780 Control Registers */
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#define PCIECR 0xFE000008
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@ -36,35 +35,6 @@
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#define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
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/* SH7780 PCI Config Registers */
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#define SH7780_PCIVID 0x000 /* Vendor ID */
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#define SH7780_PCIDID 0x002 /* Device ID */
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#define SH7780_PCICMD 0x004 /* Command */
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#define SH7780_PCISTATUS 0x006 /* Status */
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#define SH7780_PCIRID 0x008 /* Revision ID */
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#define SH7780_PCIPIF 0x009 /* Program Interface */
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#define SH7780_PCISUB 0x00a /* Sub class code */
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#define SH7780_PCIBCC 0x00b /* Base class code */
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#define SH7780_PCICLS 0x00c /* Cache line size */
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#define SH7780_PCILTM 0x00d /* latency timer */
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#define SH7780_PCIHDR 0x00e /* Header type */
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#define SH7780_PCIBIST 0x00f /* BIST */
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#define SH7780_PCIIBAR 0x010 /* IO Base address */
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#define SH7780_PCIMBAR0 0x014 /* Memory base address0 */
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#define SH7780_PCIMBAR1 0x018 /* Memory base address1 */
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#define SH7780_PCISVID 0x02c /* Sub system vendor ID */
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#define SH7780_PCISID 0x02e /* Sub system ID */
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#define SH7780_PCICP 0x034
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#define SH7780_PCIINTLINE 0x03c /* Interrupt line */
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#define SH7780_PCIINTPIN 0x03d /* Interrupt pin */
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#define SH7780_PCIMINGNT 0x03e /* Minumum grand */
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#define SH7780_PCIMAXLAT 0x03f /* Maxmum latency */
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#define SH7780_PCICID 0x040
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#define SH7780_PCINIP 0x041
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#define SH7780_PCIPMC 0x042
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#define SH7780_PCIPMCSR 0x044
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#define SH7780_PCIPMCSR_BSE 0x046
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#define SH7780_PCICDD 0x047
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#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
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#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
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#define SH7780_PCIAIR 0x11C /* Error Address Register */
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@ -78,6 +48,8 @@
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#define SH7780_PCIMBR0 0x1E0
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#define SH7780_PCIMBMR0 0x1E4
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#define SH7780_PCIMBR1 0x1E8
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#define SH7780_PCIMBMR1 0x1EC
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#define SH7780_PCIMBR2 0x1F0
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#define SH7780_PCIMBMR2 0x1F4
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#define SH7780_PCIIOBR 0x1F8
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@ -87,16 +59,4 @@
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#define SH7780_PCICSAR0 0x218 /* Cache Snoop1 Addr. Register */
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#define SH7780_PCICSAR1 0x21C /* Cache Snoop2 Addr. Register */
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/* General Memory Config Addresses */
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#define SH7780_CS0_BASE_ADDR 0x0
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#define SH7780_MEM_REGION_SIZE 0x04000000
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#define SH7780_CS1_BASE_ADDR (SH7780_CS0_BASE_ADDR + SH7780_MEM_REGION_SIZE)
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#define SH7780_CS2_BASE_ADDR (SH7780_CS1_BASE_ADDR + SH7780_MEM_REGION_SIZE)
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#define SH7780_CS3_BASE_ADDR (SH7780_CS2_BASE_ADDR + SH7780_MEM_REGION_SIZE)
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#define SH7780_CS4_BASE_ADDR (SH7780_CS3_BASE_ADDR + SH7780_MEM_REGION_SIZE)
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#define SH7780_CS5_BASE_ADDR (SH7780_CS4_BASE_ADDR + SH7780_MEM_REGION_SIZE)
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#define SH7780_CS6_BASE_ADDR (SH7780_CS5_BASE_ADDR + SH7780_MEM_REGION_SIZE)
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#define SH7780_32BIT_DDR_BASE_ADDR 0x40000000
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#endif /* _PCI_SH7780_H_ */
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