[SCSI] mvsas: Add new macros and functions
Add new macros: MVS_SOFT_RESET, MVS_HARD_RESET, MVS_PHY_TUNE, MVS_COMMAND_ACTIVE, EXP_BRCT_CHG, MVS_MAX_SG Add new member sg_width in struct mvs_chip_info Use macros rather than magic number Add new functions: mvs_fill_ssp_resp_iu, mvs_set_sense, mvs_94xx_clear_srs_irq, mvs_94xx_phy_set_link_rate Signed-off-by: Xiangliang Yu <yuxiangl@marvell.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
This commit is contained in:
Xiangliang Yu
James Bottomley
Родитель
b89e8f539f
Коммит
a4632aae8b
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@ -48,7 +48,7 @@ static void __devinit mvs_64xx_enable_xmt(struct mvs_info *mvi, int phy_id)
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u32 tmp;
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tmp = mr32(MVS_PCS);
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if (mvi->chip->n_phy <= 4)
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if (mvi->chip->n_phy <= MVS_SOC_PORTS)
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tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT);
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else
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tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2);
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@ -95,7 +95,7 @@ static void mvs_64xx_stp_reset(struct mvs_info *mvi, u32 phy_id)
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u32 reg, tmp;
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if (!(mvi->flags & MVF_FLAG_SOC)) {
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if (phy_id < 4)
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if (phy_id < MVS_SOC_PORTS)
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pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, ®);
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else
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pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, ®);
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@ -104,13 +104,13 @@ static void mvs_64xx_stp_reset(struct mvs_info *mvi, u32 phy_id)
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reg = mr32(MVS_PHY_CTL);
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tmp = reg;
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if (phy_id < 4)
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if (phy_id < MVS_SOC_PORTS)
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tmp |= (1U << phy_id) << PCTL_LINK_OFFS;
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else
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tmp |= (1U << (phy_id - 4)) << PCTL_LINK_OFFS;
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tmp |= (1U << (phy_id - MVS_SOC_PORTS)) << PCTL_LINK_OFFS;
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if (!(mvi->flags & MVF_FLAG_SOC)) {
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if (phy_id < 4) {
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if (phy_id < MVS_SOC_PORTS) {
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pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
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mdelay(10);
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pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, reg);
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@ -133,9 +133,9 @@ static void mvs_64xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard)
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tmp &= ~PHYEV_RDY_CH;
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mvs_write_port_irq_stat(mvi, phy_id, tmp);
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tmp = mvs_read_phy_ctl(mvi, phy_id);
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if (hard == 1)
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if (hard == MVS_HARD_RESET)
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tmp |= PHY_RST_HARD;
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else if (hard == 0)
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else if (hard == MVS_SOFT_RESET)
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tmp |= PHY_RST;
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mvs_write_phy_ctl(mvi, phy_id, tmp);
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if (hard) {
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@ -346,7 +346,7 @@ static int __devinit mvs_64xx_init(struct mvs_info *mvi)
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mvs_64xx_enable_xmt(mvi, i);
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mvs_64xx_phy_reset(mvi, i, 1);
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mvs_64xx_phy_reset(mvi, i, MVS_HARD_RESET);
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msleep(500);
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mvs_64xx_detect_porttype(mvi, i);
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}
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@ -661,7 +661,7 @@ void mvs_64xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,
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tmp |= lrmax;
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}
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mvs_write_phy_ctl(mvi, phy_id, tmp);
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mvs_64xx_phy_reset(mvi, phy_id, 1);
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mvs_64xx_phy_reset(mvi, phy_id, MVS_HARD_RESET);
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}
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static void mvs_64xx_clear_active_cmds(struct mvs_info *mvi)
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@ -389,7 +389,7 @@ static int __devinit mvs_94xx_init(struct mvs_info *mvi)
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mvs_phy_hacks(mvi);
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/* set LED blink when IO*/
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mw32(MVS_PA_VSR_ADDR, 0x00000030);
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mw32(MVS_PA_VSR_ADDR, VSR_PHY_ACT_LED);
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tmp = mr32(MVS_PA_VSR_PORT);
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tmp &= 0xFFFF00FF;
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tmp |= 0x00003300;
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@ -419,7 +419,7 @@ static int __devinit mvs_94xx_init(struct mvs_info *mvi)
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mvs_94xx_config_reg_from_hba(mvi, i);
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mvs_94xx_phy_enable(mvi, i);
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mvs_94xx_phy_reset(mvi, i, 1);
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mvs_94xx_phy_reset(mvi, i, PHY_RST_HARD);
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msleep(500);
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mvs_94xx_detect_porttype(mvi, i);
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}
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@ -585,10 +585,48 @@ static irqreturn_t mvs_94xx_isr(struct mvs_info *mvi, int irq, u32 stat)
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static void mvs_94xx_command_active(struct mvs_info *mvi, u32 slot_idx)
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{
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u32 tmp;
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mvs_cw32(mvi, 0x300 + (slot_idx >> 3), 1 << (slot_idx % 32));
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do {
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tmp = mvs_cr32(mvi, 0x300 + (slot_idx >> 3));
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} while (tmp & 1 << (slot_idx % 32));
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tmp = mvs_cr32(mvi, MVS_COMMAND_ACTIVE+(slot_idx >> 3));
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if (tmp && 1 << (slot_idx % 32)) {
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mv_printk("command active %08X, slot [%x].\n", tmp, slot_idx);
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mvs_cw32(mvi, MVS_COMMAND_ACTIVE + (slot_idx >> 3),
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1 << (slot_idx % 32));
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do {
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tmp = mvs_cr32(mvi,
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MVS_COMMAND_ACTIVE + (slot_idx >> 3));
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} while (tmp & 1 << (slot_idx % 32));
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}
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}
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void mvs_94xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all)
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{
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void __iomem *regs = mvi->regs;
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u32 tmp;
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if (clear_all) {
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tmp = mr32(MVS_INT_STAT_SRS_0);
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if (tmp) {
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mv_dprintk("check SRS 0 %08X.\n", tmp);
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mw32(MVS_INT_STAT_SRS_0, tmp);
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}
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tmp = mr32(MVS_INT_STAT_SRS_1);
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if (tmp) {
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mv_dprintk("check SRS 1 %08X.\n", tmp);
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mw32(MVS_INT_STAT_SRS_1, tmp);
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}
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} else {
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if (reg_set > 31)
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tmp = mr32(MVS_INT_STAT_SRS_1);
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else
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tmp = mr32(MVS_INT_STAT_SRS_0);
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if (tmp & (1 << (reg_set % 32))) {
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mv_dprintk("register set 0x%x was stopped.\n", reg_set);
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if (reg_set > 31)
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mw32(MVS_INT_STAT_SRS_1, 1 << (reg_set % 32));
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else
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mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32));
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}
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}
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}
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static void mvs_94xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type,
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@ -596,12 +634,10 @@ static void mvs_94xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type,
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{
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void __iomem *regs = mvi->regs;
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u32 tmp;
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mvs_94xx_clear_srs_irq(mvi, 0, 1);
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if (type == PORT_TYPE_SATA) {
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tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs);
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mw32(MVS_INT_STAT_SRS_0, tmp);
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}
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mw32(MVS_INT_STAT, CINT_CI_STOP);
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tmp = mr32(MVS_INT_STAT);
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mw32(MVS_INT_STAT, tmp | CINT_CI_STOP);
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tmp = mr32(MVS_PCS) | 0xFF00;
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mw32(MVS_PCS, tmp);
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}
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@ -794,7 +830,18 @@ static void mvs_94xx_fix_phy_info(struct mvs_info *mvi, int i,
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void mvs_94xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,
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struct sas_phy_linkrates *rates)
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{
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/* TODO */
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u32 lrmax = 0;
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u32 tmp;
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tmp = mvs_read_phy_ctl(mvi, phy_id);
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lrmax = (rates->maximum_linkrate - SAS_LINK_RATE_1_5_GBPS) << 12;
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if (lrmax) {
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tmp &= ~(0x3 << 12);
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tmp |= lrmax;
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}
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mvs_write_phy_ctl(mvi, phy_id, tmp);
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mvs_94xx_phy_reset(mvi, phy_id, PHY_RST_HARD);
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}
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static void mvs_94xx_clear_active_cmds(struct mvs_info *mvi)
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@ -893,15 +940,6 @@ void mvs_94xx_fix_dma(struct mvs_info *mvi, u32 phy_mask,
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}
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}
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/*
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* FIXME JEJB: temporary nop clear_srs_irq to make 94xx still work
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* with 64xx fixes
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*/
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static void mvs_94xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set,
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u8 clear_all)
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{
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}
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static void mvs_94xx_tune_interrupt(struct mvs_info *mvi, u32 time)
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{
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void __iomem *regs = mvi->regs;
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@ -109,6 +109,7 @@ enum hw_registers {
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MVS_P4_VSR_DATA = 0x254, /* phy4 VSR data */
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MVS_PA_VSR_ADDR = 0x290, /* All port VSR addr */
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MVS_PA_VSR_PORT = 0x294, /* All port VSR data */
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MVS_COMMAND_ACTIVE = 0x300,
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};
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enum pci_cfg_registers {
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@ -132,6 +133,7 @@ enum sas_sata_vsp_regs {
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VSR_PHY_MODE9 = 0x09 * 4, /* Test */
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VSR_PHY_MODE10 = 0x0A * 4, /* Power */
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VSR_PHY_MODE11 = 0x0B * 4, /* Phy Mode */
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VSR_PHY_ACT_LED = 0x0C * 4, /* Activity LED control */
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VSR_PHY_FFE_CONTROL = 0x10C,
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VSR_PHY_DFE_UPDATE_CRTL = 0x110,
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@ -395,9 +395,10 @@ enum mvs_info_flags {
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};
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enum mvs_event_flags {
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PHY_PLUG_EVENT = (3U),
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PHY_PLUG_EVENT = (3U),
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PHY_PLUG_IN = (1U << 0), /* phy plug in */
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PHY_PLUG_OUT = (1U << 1), /* phy plug out */
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EXP_BRCT_CHG = (1U << 2), /* broadcast change */
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};
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enum mvs_port_type {
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@ -39,15 +39,15 @@ int interrupt_coalescing = 0x80;
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static struct scsi_transport_template *mvs_stt;
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struct kmem_cache *mvs_task_list_cache;
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static const struct mvs_chip_info mvs_chips[] = {
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[chip_6320] = { 1, 2, 0x400, 17, 16, 9, &mvs_64xx_dispatch, },
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[chip_6440] = { 1, 4, 0x400, 17, 16, 9, &mvs_64xx_dispatch, },
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[chip_6485] = { 1, 8, 0x800, 33, 32, 10, &mvs_64xx_dispatch, },
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[chip_9180] = { 2, 4, 0x800, 17, 64, 9, &mvs_94xx_dispatch, },
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[chip_9480] = { 2, 4, 0x800, 17, 64, 9, &mvs_94xx_dispatch, },
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[chip_9445] = { 1, 4, 0x800, 17, 64, 11, &mvs_94xx_dispatch, },
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[chip_9485] = { 2, 4, 0x800, 17, 64, 11, &mvs_94xx_dispatch, },
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[chip_1300] = { 1, 4, 0x400, 17, 16, 9, &mvs_64xx_dispatch, },
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[chip_1320] = { 2, 4, 0x800, 17, 64, 9, &mvs_94xx_dispatch, },
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[chip_6320] = { 1, 2, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
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[chip_6440] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
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[chip_6485] = { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, },
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[chip_9180] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
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[chip_9480] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
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[chip_9445] = { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
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[chip_9485] = { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
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[chip_1300] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
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[chip_1320] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
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};
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struct device_attribute *mvst_host_attrs[];
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@ -466,7 +466,7 @@ static int __devinit mvs_prep_sas_ha_init(struct Scsi_Host *shost,
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((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr;
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shost->transportt = mvs_stt;
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shost->max_id = 128;
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shost->max_id = MVS_MAX_DEVICES;
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shost->max_lun = ~0;
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shost->max_channel = 1;
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shost->max_cmd_len = 16;
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@ -512,6 +512,7 @@ static void __devinit mvs_post_sas_ha_init(struct Scsi_Host *shost,
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can_queue = MVS_CHIP_SLOT_SZ;
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sha->lldd_queue_size = can_queue;
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shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG);
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shost->can_queue = can_queue;
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mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE;
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sha->core.shost = mvi->shost;
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@ -203,12 +203,12 @@ int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
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tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id);
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if (tmp & PHY_RST_HARD)
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break;
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MVS_CHIP_DISP->phy_reset(mvi, phy_id, 1);
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MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_HARD_RESET);
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break;
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case PHY_FUNC_LINK_RESET:
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MVS_CHIP_DISP->phy_enable(mvi, phy_id);
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MVS_CHIP_DISP->phy_reset(mvi, phy_id, 0);
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MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_SOFT_RESET);
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break;
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case PHY_FUNC_DISABLE:
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@ -1758,12 +1758,63 @@ static int mvs_sata_done(struct mvs_info *mvi, struct sas_task *task,
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return stat;
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}
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void mvs_set_sense(u8 *buffer, int len, int d_sense,
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int key, int asc, int ascq)
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{
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memset(buffer, 0, len);
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if (d_sense) {
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/* Descriptor format */
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if (len < 4) {
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mv_printk("Length %d of sense buffer too small to "
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"fit sense %x:%x:%x", len, key, asc, ascq);
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}
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buffer[0] = 0x72; /* Response Code */
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if (len > 1)
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buffer[1] = key; /* Sense Key */
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if (len > 2)
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buffer[2] = asc; /* ASC */
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if (len > 3)
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buffer[3] = ascq; /* ASCQ */
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} else {
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if (len < 14) {
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mv_printk("Length %d of sense buffer too small to "
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"fit sense %x:%x:%x", len, key, asc, ascq);
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}
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buffer[0] = 0x70; /* Response Code */
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if (len > 2)
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buffer[2] = key; /* Sense Key */
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if (len > 7)
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buffer[7] = 0x0a; /* Additional Sense Length */
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if (len > 12)
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buffer[12] = asc; /* ASC */
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if (len > 13)
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buffer[13] = ascq; /* ASCQ */
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}
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return;
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}
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void mvs_fill_ssp_resp_iu(struct ssp_response_iu *iu,
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u8 key, u8 asc, u8 asc_q)
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{
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iu->datapres = 2;
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iu->response_data_len = 0;
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iu->sense_data_len = 17;
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iu->status = 02;
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mvs_set_sense(iu->sense_data, 17, 0,
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key, asc, asc_q);
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}
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static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
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u32 slot_idx)
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{
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struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
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int stat;
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u32 err_dw0 = le32_to_cpu(*(u32 *) (slot->response));
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u32 err_dw1 = le32_to_cpu(*((u32 *)slot->response + 1));
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u32 tfs = 0;
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enum mvs_port_type type = PORT_TYPE_SAS;
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@ -1775,8 +1826,19 @@ static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
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stat = SAM_STAT_CHECK_CONDITION;
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switch (task->task_proto) {
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case SAS_PROTOCOL_SSP:
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{
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stat = SAS_ABORTED_TASK;
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if ((err_dw0 & NO_DEST) || err_dw1 & bit(31)) {
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struct ssp_response_iu *iu = slot->response +
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sizeof(struct mvs_err_info);
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mvs_fill_ssp_resp_iu(iu, NOT_READY, 0x04, 01);
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sas_ssp_task_response(mvi->dev, task, iu);
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stat = SAM_STAT_CHECK_CONDITION;
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}
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if (err_dw1 & bit(31))
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mv_printk("reuse same slot, retry command.\n");
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break;
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}
|
||||
case SAS_PROTOCOL_SMP:
|
||||
stat = SAM_STAT_CHECK_CONDITION;
|
||||
break;
|
||||
|
|
@ -1974,13 +2036,13 @@ static void mvs_work_queue(struct work_struct *work)
|
|||
struct mvs_wq *mwq = container_of(dw, struct mvs_wq, work_q);
|
||||
struct mvs_info *mvi = mwq->mvi;
|
||||
unsigned long flags;
|
||||
u32 phy_no = (unsigned long) mwq->data;
|
||||
struct sas_ha_struct *sas_ha = mvi->sas;
|
||||
struct mvs_phy *phy = &mvi->phy[phy_no];
|
||||
struct asd_sas_phy *sas_phy = &phy->sas_phy;
|
||||
|
||||
spin_lock_irqsave(&mvi->lock, flags);
|
||||
if (mwq->handler & PHY_PLUG_EVENT) {
|
||||
u32 phy_no = (unsigned long) mwq->data;
|
||||
struct sas_ha_struct *sas_ha = mvi->sas;
|
||||
struct mvs_phy *phy = &mvi->phy[phy_no];
|
||||
struct asd_sas_phy *sas_phy = &phy->sas_phy;
|
||||
|
||||
if (phy->phy_event & PHY_PLUG_OUT) {
|
||||
u32 tmp;
|
||||
|
|
@ -2002,6 +2064,11 @@ static void mvs_work_queue(struct work_struct *work)
|
|||
mv_dprintk("phy%d Attached Device\n", phy_no);
|
||||
}
|
||||
}
|
||||
} else if (mwq->handler & EXP_BRCT_CHG) {
|
||||
phy->phy_event &= ~EXP_BRCT_CHG;
|
||||
sas_ha->notify_port_event(sas_phy,
|
||||
PORTE_BROADCAST_RCVD);
|
||||
mv_dprintk("phy%d Got Broadcast Change\n", phy_no);
|
||||
}
|
||||
list_del(&mwq->entry);
|
||||
spin_unlock_irqrestore(&mvi->lock, flags);
|
||||
|
|
@ -2037,7 +2104,7 @@ static void mvs_sig_time_out(unsigned long tphy)
|
|||
if (&mvi->phy[phy_no] == phy) {
|
||||
mv_dprintk("Get signature time out, reset phy %d\n",
|
||||
phy_no+mvi->id*mvi->chip->n_phy);
|
||||
MVS_CHIP_DISP->phy_reset(mvi, phy_no, 1);
|
||||
MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_HARD_RESET);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -2045,9 +2112,7 @@ static void mvs_sig_time_out(unsigned long tphy)
|
|||
void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
|
||||
{
|
||||
u32 tmp;
|
||||
struct sas_ha_struct *sas_ha = mvi->sas;
|
||||
struct mvs_phy *phy = &mvi->phy[phy_no];
|
||||
struct asd_sas_phy *sas_phy = &phy->sas_phy;
|
||||
|
||||
phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no);
|
||||
mv_dprintk("port %d ctrl sts=0x%X.\n", phy_no+mvi->id*mvi->chip->n_phy,
|
||||
|
|
@ -2086,7 +2151,7 @@ void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
|
|||
phy_no);
|
||||
else
|
||||
MVS_CHIP_DISP->phy_reset(mvi,
|
||||
phy_no, 0);
|
||||
phy_no, MVS_SOFT_RESET);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
|
@ -2118,14 +2183,14 @@ void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
|
|||
}
|
||||
mvs_update_phyinfo(mvi, phy_no, 0);
|
||||
if (phy->phy_type & PORT_TYPE_SAS) {
|
||||
MVS_CHIP_DISP->phy_reset(mvi, phy_no, 2);
|
||||
MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_PHY_TUNE);
|
||||
mdelay(10);
|
||||
}
|
||||
|
||||
mvs_bytes_dmaed(mvi, phy_no);
|
||||
/* whether driver is going to handle hot plug */
|
||||
if (phy->phy_event & PHY_PLUG_OUT) {
|
||||
mvs_port_notify_formed(sas_phy, 0);
|
||||
mvs_port_notify_formed(&phy->sas_phy, 0);
|
||||
phy->phy_event &= ~PHY_PLUG_OUT;
|
||||
}
|
||||
} else {
|
||||
|
|
@ -2135,9 +2200,8 @@ void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
|
|||
} else if (phy->irq_status & PHYEV_BROAD_CH) {
|
||||
mv_dprintk("port %d broadcast change.\n",
|
||||
phy_no + mvi->id*mvi->chip->n_phy);
|
||||
/* exception for Samsung disk drive*/
|
||||
mdelay(1000);
|
||||
sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
|
||||
mvs_handle_event(mvi, (void *)(unsigned long)phy_no,
|
||||
EXP_BRCT_CHG);
|
||||
}
|
||||
MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -96,6 +96,11 @@ enum dev_status {
|
|||
MVS_DEV_EH = 0x1,
|
||||
};
|
||||
|
||||
enum dev_reset {
|
||||
MVS_SOFT_RESET = 0,
|
||||
MVS_HARD_RESET = 1,
|
||||
MVS_PHY_TUNE = 2,
|
||||
};
|
||||
|
||||
struct mvs_info;
|
||||
|
||||
|
|
@ -176,9 +181,11 @@ struct mvs_chip_info {
|
|||
u32 fis_offs;
|
||||
u32 fis_count;
|
||||
u32 srs_sz;
|
||||
u32 sg_width;
|
||||
u32 slot_width;
|
||||
const struct mvs_dispatch *dispatch;
|
||||
};
|
||||
#define MVS_MAX_SG (1U << mvi->chip->sg_width)
|
||||
#define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width)
|
||||
#define MVS_RX_FISL_SZ \
|
||||
(mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100))
|
||||
|
|
|
|||
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