drm/i915/selftests: Exercise CS TLB invalidation
Check that we are correctly invalidating the TLB at the start of a batch after updating the GTT. v2: Comments and hold the request reference while spinning Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190919131414.7495-1-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
Родитель
37fa0de3c1
Коммит
a47e788c23
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@ -25,13 +25,16 @@
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#include <linux/list_sort.h>
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#include <linux/prime_numbers.h>
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#include "gem/i915_gem_context.h"
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#include "gem/selftests/mock_context.h"
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#include "gt/intel_context.h"
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#include "i915_random.h"
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#include "i915_selftest.h"
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#include "mock_drm.h"
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#include "mock_gem_device.h"
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#include "igt_flush_test.h"
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static void cleanup_freed_objects(struct drm_i915_private *i915)
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{
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@ -1705,6 +1708,310 @@ out_put:
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return err;
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}
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static int context_sync(struct intel_context *ce)
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{
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struct i915_request *rq;
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long timeout;
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rq = intel_context_create_request(ce);
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if (IS_ERR(rq))
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return PTR_ERR(rq);
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i915_request_get(rq);
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i915_request_add(rq);
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timeout = i915_request_wait(rq, 0, HZ / 5);
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i915_request_put(rq);
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return timeout < 0 ? -EIO : 0;
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}
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static struct i915_request *
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submit_batch(struct intel_context *ce, u64 addr)
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{
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struct i915_request *rq;
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int err;
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rq = intel_context_create_request(ce);
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if (IS_ERR(rq))
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return rq;
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err = 0;
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if (rq->engine->emit_init_breadcrumb) /* detect a hang */
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err = rq->engine->emit_init_breadcrumb(rq);
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if (err == 0)
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err = rq->engine->emit_bb_start(rq, addr, 0, 0);
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if (err == 0)
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i915_request_get(rq);
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i915_request_add(rq);
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return err ? ERR_PTR(err) : rq;
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}
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static u32 *spinner(u32 *batch, int i)
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{
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return batch + i * 64 / sizeof(*batch) + 4;
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}
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static void end_spin(u32 *batch, int i)
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{
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*spinner(batch, i) = MI_BATCH_BUFFER_END;
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wmb();
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}
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static int igt_cs_tlb(void *arg)
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{
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const unsigned int count = PAGE_SIZE / 64;
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const unsigned int chunk_size = count * PAGE_SIZE;
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struct drm_i915_private *i915 = arg;
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struct drm_i915_gem_object *bbe, *act, *out;
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struct i915_gem_engines_iter it;
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struct i915_address_space *vm;
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struct i915_gem_context *ctx;
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struct intel_context *ce;
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struct drm_file *file;
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struct i915_vma *vma;
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unsigned int i;
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u32 *result;
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u32 *batch;
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int err = 0;
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/*
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* Our mission here is to fool the hardware to execute something
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* from scratch as it has not seen the batch move (due to missing
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* the TLB invalidate).
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*/
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file = mock_file(i915);
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if (IS_ERR(file))
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return PTR_ERR(file);
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mutex_lock(&i915->drm.struct_mutex);
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ctx = live_context(i915, file);
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if (IS_ERR(ctx)) {
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err = PTR_ERR(ctx);
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goto out_unlock;
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}
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vm = ctx->vm;
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if (!vm)
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goto out_unlock;
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/* Create two pages; dummy we prefill the TLB, and intended */
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bbe = i915_gem_object_create_internal(i915, PAGE_SIZE);
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if (IS_ERR(bbe)) {
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err = PTR_ERR(bbe);
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goto out_unlock;
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}
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batch = i915_gem_object_pin_map(bbe, I915_MAP_WC);
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if (IS_ERR(batch)) {
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err = PTR_ERR(batch);
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goto out_put_bbe;
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}
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memset32(batch, MI_BATCH_BUFFER_END, PAGE_SIZE / sizeof(u32));
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i915_gem_object_flush_map(bbe);
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i915_gem_object_unpin_map(bbe);
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act = i915_gem_object_create_internal(i915, PAGE_SIZE);
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if (IS_ERR(act)) {
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err = PTR_ERR(act);
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goto out_put_bbe;
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}
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/* Track the execution of each request by writing into different slot */
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batch = i915_gem_object_pin_map(act, I915_MAP_WC);
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if (IS_ERR(batch)) {
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err = PTR_ERR(batch);
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goto out_put_act;
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}
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for (i = 0; i < count; i++) {
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u32 *cs = batch + i * 64 / sizeof(*cs);
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u64 addr = (vm->total - PAGE_SIZE) + i * sizeof(u32);
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GEM_BUG_ON(INTEL_GEN(i915) < 6);
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cs[0] = MI_STORE_DWORD_IMM_GEN4;
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if (INTEL_GEN(i915) >= 8) {
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cs[1] = lower_32_bits(addr);
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cs[2] = upper_32_bits(addr);
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cs[3] = i;
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cs[4] = MI_NOOP;
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cs[5] = MI_BATCH_BUFFER_START_GEN8;
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} else {
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cs[1] = 0;
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cs[2] = lower_32_bits(addr);
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cs[3] = i;
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cs[4] = MI_NOOP;
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cs[5] = MI_BATCH_BUFFER_START;
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}
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}
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out = i915_gem_object_create_internal(i915, PAGE_SIZE);
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if (IS_ERR(out)) {
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err = PTR_ERR(out);
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goto out_put_batch;
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}
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i915_gem_object_set_cache_coherency(out, I915_CACHING_CACHED);
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vma = i915_vma_instance(out, vm, NULL);
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if (IS_ERR(vma)) {
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err = PTR_ERR(vma);
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goto out_put_batch;
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}
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err = i915_vma_pin(vma, 0, 0,
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PIN_USER |
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PIN_OFFSET_FIXED |
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(vm->total - PAGE_SIZE));
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if (err)
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goto out_put_out;
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GEM_BUG_ON(vma->node.start != vm->total - PAGE_SIZE);
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result = i915_gem_object_pin_map(out, I915_MAP_WB);
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if (IS_ERR(result)) {
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err = PTR_ERR(result);
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goto out_put_out;
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}
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for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
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IGT_TIMEOUT(end_time);
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unsigned long pass = 0;
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if (!intel_engine_can_store_dword(ce->engine))
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continue;
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while (!__igt_timeout(end_time, NULL)) {
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struct i915_request *rq;
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u64 offset;
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offset = random_offset(0, vm->total - PAGE_SIZE,
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chunk_size, PAGE_SIZE);
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err = vm->allocate_va_range(vm, offset, chunk_size);
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if (err)
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goto end;
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memset32(result, STACK_MAGIC, PAGE_SIZE / sizeof(u32));
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vma = i915_vma_instance(bbe, vm, NULL);
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if (IS_ERR(vma)) {
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err = PTR_ERR(vma);
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goto end;
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}
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err = vma->ops->set_pages(vma);
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if (err)
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goto end;
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/* Prime the TLB with the dummy pages */
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for (i = 0; i < count; i++) {
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vma->node.start = offset + i * PAGE_SIZE;
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vm->insert_entries(vm, vma, I915_CACHE_NONE, 0);
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rq = submit_batch(ce, vma->node.start);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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goto end;
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}
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i915_request_put(rq);
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}
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vma->ops->clear_pages(vma);
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err = context_sync(ce);
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if (err) {
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pr_err("%s: dummy setup timed out\n",
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ce->engine->name);
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goto end;
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}
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vma = i915_vma_instance(act, vm, NULL);
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if (IS_ERR(vma)) {
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err = PTR_ERR(vma);
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goto end;
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}
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err = vma->ops->set_pages(vma);
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if (err)
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goto end;
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/* Replace the TLB with target batches */
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for (i = 0; i < count; i++) {
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struct i915_request *rq;
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u32 *cs = batch + i * 64 / sizeof(*cs);
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u64 addr;
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vma->node.start = offset + i * PAGE_SIZE;
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vm->insert_entries(vm, vma, I915_CACHE_NONE, 0);
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addr = vma->node.start + i * 64;
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cs[4] = MI_NOOP;
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cs[6] = lower_32_bits(addr);
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cs[7] = upper_32_bits(addr);
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wmb();
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rq = submit_batch(ce, addr);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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goto end;
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}
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/* Wait until the context chain has started */
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if (i == 0) {
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while (READ_ONCE(result[i]) &&
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!i915_request_completed(rq))
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cond_resched();
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} else {
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end_spin(batch, i - 1);
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}
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i915_request_put(rq);
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}
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end_spin(batch, count - 1);
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vma->ops->clear_pages(vma);
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err = context_sync(ce);
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if (err) {
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pr_err("%s: writes timed out\n",
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ce->engine->name);
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goto end;
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}
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for (i = 0; i < count; i++) {
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if (result[i] != i) {
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pr_err("%s: Write lost on pass %lu, at offset %llx, index %d, found %x, expected %x\n",
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ce->engine->name, pass,
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offset, i, result[i], i);
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err = -EINVAL;
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goto end;
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}
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}
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vm->clear_range(vm, offset, chunk_size);
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pass++;
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}
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}
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end:
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if (igt_flush_test(i915, I915_WAIT_LOCKED))
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err = -EIO;
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i915_gem_context_unlock_engines(ctx);
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i915_gem_object_unpin_map(out);
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out_put_out:
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i915_gem_object_put(out);
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out_put_batch:
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i915_gem_object_unpin_map(act);
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out_put_act:
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i915_gem_object_put(act);
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out_put_bbe:
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i915_gem_object_put(bbe);
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out_unlock:
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mutex_unlock(&i915->drm.struct_mutex);
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mock_file_free(i915, file);
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return err;
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}
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int i915_gem_gtt_live_selftests(struct drm_i915_private *i915)
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{
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static const struct i915_subtest tests[] = {
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@ -1722,6 +2029,7 @@ int i915_gem_gtt_live_selftests(struct drm_i915_private *i915)
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SUBTEST(igt_ggtt_pot),
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SUBTEST(igt_ggtt_fill),
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SUBTEST(igt_ggtt_page),
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SUBTEST(igt_cs_tlb),
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};
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GEM_BUG_ON(offset_in_page(i915->ggtt.vm.total));
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