Merge branch 'pci/virtualization'
- probe for device reset support during enumeration instead of runtime
(Bjorn Helgaas)
- add ACS quirk for Ampere (née APM) root ports (Feng Kan)
- add function 1 DMA alias quirk for Marvell 88SE9220 (Thomas
Vincent-Cross)
- protect device restore with device lock (Sinan Kaya)
- handle failure of FLR gracefully (Sinan Kaya)
- handle CRS (config retry status) after device resets (Sinan Kaya)
- skip various config reads for SR-IOV VFs as an optimization (KarimAllah
Ahmed)
* pci/virtualization:
PCI/IOV: Add missing prototypes for powerpc pcibios interfaces
PCI/IOV: Use VF0 cached config registers for other VFs
PCI/IOV: Skip BAR sizing for VFs
PCI/IOV: Skip INTx config reads for VFs
PCI: Wait for device to become ready after secondary bus reset
PCI: Add a return type for pci_reset_bridge_secondary_bus()
PCI: Wait for device to become ready after a power management reset
PCI: Rename pci_flr_wait() to pci_dev_wait() and make it generic
PCI: Handle FLR failure and allow other reset types
PCI: Protect restore with device lock to be consistent
PCI: Add function 1 DMA alias quirk for Marvell 88SE9220
PCI: Add ACS quirk for Ampere root ports
PCI: Remove redundant probes for device reset support
PCI: Probe for device reset support during enumeration
Conflicts:
include/linux/pci.h
This commit is contained in:
Bjorn Helgaas
Bjorn Helgaas
Коммит
a4b88505ac
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@ -112,6 +112,29 @@ resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
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return dev->sriov->barsz[resno - PCI_IOV_RESOURCES];
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}
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static void pci_read_vf_config_common(struct pci_dev *virtfn)
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{
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struct pci_dev *physfn = virtfn->physfn;
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/*
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* Some config registers are the same across all associated VFs.
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* Read them once from VF0 so we can skip reading them from the
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* other VFs.
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*
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* PCIe r4.0, sec 9.3.4.1, technically doesn't require all VFs to
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* have the same Revision ID and Subsystem ID, but we assume they
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* do.
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*/
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pci_read_config_dword(virtfn, PCI_CLASS_REVISION,
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&physfn->sriov->class);
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pci_read_config_byte(virtfn, PCI_HEADER_TYPE,
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&physfn->sriov->hdr_type);
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pci_read_config_word(virtfn, PCI_SUBSYSTEM_VENDOR_ID,
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&physfn->sriov->subsystem_vendor);
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pci_read_config_word(virtfn, PCI_SUBSYSTEM_ID,
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&physfn->sriov->subsystem_device);
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}
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int pci_iov_add_virtfn(struct pci_dev *dev, int id)
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{
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int i;
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@ -134,13 +157,17 @@ int pci_iov_add_virtfn(struct pci_dev *dev, int id)
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virtfn->devfn = pci_iov_virtfn_devfn(dev, id);
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virtfn->vendor = dev->vendor;
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virtfn->device = iov->vf_device;
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virtfn->is_virtfn = 1;
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virtfn->physfn = pci_dev_get(dev);
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if (id == 0)
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pci_read_vf_config_common(virtfn);
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rc = pci_setup_device(virtfn);
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if (rc)
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goto failed0;
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goto failed1;
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virtfn->dev.parent = dev->dev.parent;
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virtfn->physfn = pci_dev_get(dev);
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virtfn->is_virtfn = 1;
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virtfn->multifunction = 0;
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for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
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@ -161,10 +188,10 @@ int pci_iov_add_virtfn(struct pci_dev *dev, int id)
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sprintf(buf, "virtfn%u", id);
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rc = sysfs_create_link(&dev->dev.kobj, &virtfn->dev.kobj, buf);
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if (rc)
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goto failed1;
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goto failed2;
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rc = sysfs_create_link(&virtfn->dev.kobj, &dev->dev.kobj, "physfn");
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if (rc)
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goto failed2;
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goto failed3;
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kobject_uevent(&virtfn->dev.kobj, KOBJ_CHANGE);
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@ -172,11 +199,12 @@ int pci_iov_add_virtfn(struct pci_dev *dev, int id)
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return 0;
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failed2:
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failed3:
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sysfs_remove_link(&dev->dev.kobj, buf);
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failed2:
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pci_stop_and_remove_bus_device(virtfn);
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failed1:
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pci_dev_put(dev);
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pci_stop_and_remove_bus_device(virtfn);
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failed0:
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virtfn_remove_bus(dev->bus, bus);
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failed:
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@ -1515,11 +1515,10 @@ static int pci_create_capabilities_sysfs(struct pci_dev *dev)
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/* Active State Power Management */
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pcie_aspm_create_sysfs_dev_files(dev);
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if (!pci_probe_reset_function(dev)) {
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if (dev->reset_fn) {
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retval = device_create_file(&dev->dev, &reset_attr);
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if (retval)
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goto error;
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dev->reset_fn = 1;
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}
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return 0;
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@ -127,6 +127,9 @@ static int __init pcie_port_pm_setup(char *str)
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}
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__setup("pcie_port_pm=", pcie_port_pm_setup);
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/* Time to wait after a reset for device to become responsive */
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#define PCIE_RESET_READY_POLL_MS 60000
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/**
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* pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
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* @bus: pointer to PCI bus structure to search
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@ -3969,20 +3972,13 @@ int pci_wait_for_pending_transaction(struct pci_dev *dev)
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}
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EXPORT_SYMBOL(pci_wait_for_pending_transaction);
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static void pci_flr_wait(struct pci_dev *dev)
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static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
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{
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int delay = 1, timeout = 60000;
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int delay = 1;
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u32 id;
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/*
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* Per PCIe r3.1, sec 6.6.2, a device must complete an FLR within
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* 100ms, but may silently discard requests while the FLR is in
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* progress. Wait 100ms before trying to access the device.
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*/
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msleep(100);
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/*
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* After 100ms, the device should not silently discard config
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* After reset, the device should not silently discard config
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* requests, but it may still indicate that it needs more time by
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* responding to them with CRS completions. The Root Port will
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* generally synthesize ~0 data to complete the read (except when
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@ -3996,14 +3992,14 @@ static void pci_flr_wait(struct pci_dev *dev)
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pci_read_config_dword(dev, PCI_COMMAND, &id);
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while (id == ~0) {
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if (delay > timeout) {
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pci_warn(dev, "not ready %dms after FLR; giving up\n",
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100 + delay - 1);
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return;
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pci_warn(dev, "not ready %dms after %s; giving up\n",
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delay - 1, reset_type);
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return -ENOTTY;
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}
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if (delay > 1000)
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pci_info(dev, "not ready %dms after FLR; waiting\n",
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100 + delay - 1);
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pci_info(dev, "not ready %dms after %s; waiting\n",
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delay - 1, reset_type);
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msleep(delay);
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delay *= 2;
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@ -4011,7 +4007,10 @@ static void pci_flr_wait(struct pci_dev *dev)
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}
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if (delay > 1000)
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pci_info(dev, "ready %dms after FLR\n", 100 + delay - 1);
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pci_info(dev, "ready %dms after %s\n", delay - 1,
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reset_type);
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return 0;
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}
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/**
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@ -4040,13 +4039,21 @@ static bool pcie_has_flr(struct pci_dev *dev)
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* device supports FLR before calling this function, e.g. by using the
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* pcie_has_flr() helper.
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*/
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void pcie_flr(struct pci_dev *dev)
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int pcie_flr(struct pci_dev *dev)
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{
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if (!pci_wait_for_pending_transaction(dev))
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pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
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pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
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pci_flr_wait(dev);
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/*
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* Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
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* 100ms, but may silently discard requests while the FLR is in
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* progress. Wait 100ms before trying to access the device.
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*/
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msleep(100);
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return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
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}
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EXPORT_SYMBOL_GPL(pcie_flr);
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@ -4079,8 +4086,16 @@ static int pci_af_flr(struct pci_dev *dev, int probe)
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pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
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pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
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pci_flr_wait(dev);
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return 0;
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/*
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* Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
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* updated 27 July 2006; a device must complete an FLR within
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* 100ms, but may silently discard requests while the FLR is in
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* progress. Wait 100ms before trying to access the device.
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*/
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msleep(100);
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return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
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}
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/**
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@ -4125,7 +4140,7 @@ static int pci_pm_reset(struct pci_dev *dev, int probe)
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pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
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pci_dev_d3_sleep(dev);
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return 0;
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return pci_dev_wait(dev, "PM D3->D0", PCIE_RESET_READY_POLL_MS);
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}
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void pci_reset_secondary_bus(struct pci_dev *dev)
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@ -4167,9 +4182,11 @@ void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
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* Use the bridge control register to assert reset on the secondary bus.
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* Devices on the secondary bus are left in power-on state.
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*/
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void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
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int pci_reset_bridge_secondary_bus(struct pci_dev *dev)
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{
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pcibios_reset_secondary_bus(dev);
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return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
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}
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EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
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@ -4332,8 +4349,9 @@ int __pci_reset_function_locked(struct pci_dev *dev)
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if (rc != -ENOTTY)
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return rc;
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if (pcie_has_flr(dev)) {
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pcie_flr(dev);
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return 0;
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rc = pcie_flr(dev);
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if (rc != -ENOTTY)
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return rc;
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}
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rc = pci_af_flr(dev, 0);
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if (rc != -ENOTTY)
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@ -4403,9 +4421,8 @@ int pci_reset_function(struct pci_dev *dev)
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{
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int rc;
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rc = pci_probe_reset_function(dev);
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if (rc)
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return rc;
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if (!dev->reset_fn)
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return -ENOTTY;
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|
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pci_dev_lock(dev);
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pci_dev_save_and_disable(dev);
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@ -4440,9 +4457,8 @@ int pci_reset_function_locked(struct pci_dev *dev)
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{
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int rc;
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|
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rc = pci_probe_reset_function(dev);
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if (rc)
|
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return rc;
|
||||
if (!dev->reset_fn)
|
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return -ENOTTY;
|
||||
|
||||
pci_dev_save_and_disable(dev);
|
||||
|
||||
|
|
@ -4464,18 +4480,17 @@ int pci_try_reset_function(struct pci_dev *dev)
|
|||
{
|
||||
int rc;
|
||||
|
||||
rc = pci_probe_reset_function(dev);
|
||||
if (rc)
|
||||
return rc;
|
||||
if (!dev->reset_fn)
|
||||
return -ENOTTY;
|
||||
|
||||
if (!pci_dev_trylock(dev))
|
||||
return -EAGAIN;
|
||||
|
||||
pci_dev_save_and_disable(dev);
|
||||
rc = __pci_reset_function_locked(dev);
|
||||
pci_dev_restore(dev);
|
||||
pci_dev_unlock(dev);
|
||||
|
||||
pci_dev_restore(dev);
|
||||
return rc;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_try_reset_function);
|
||||
|
|
@ -4683,7 +4698,9 @@ static void pci_slot_restore(struct pci_slot *slot)
|
|||
list_for_each_entry(dev, &slot->bus->devices, bus_list) {
|
||||
if (!dev->slot || dev->slot != slot)
|
||||
continue;
|
||||
pci_dev_lock(dev);
|
||||
pci_dev_restore(dev);
|
||||
pci_dev_unlock(dev);
|
||||
if (dev->subordinate)
|
||||
pci_bus_restore(dev->subordinate);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -293,6 +293,10 @@ struct pci_sriov {
|
|||
u16 driver_max_VFs; /* Max num VFs driver supports */
|
||||
struct pci_dev *dev; /* Lowest numbered PF */
|
||||
struct pci_dev *self; /* This PF */
|
||||
u32 class; /* VF device */
|
||||
u8 hdr_type; /* VF header type */
|
||||
u16 subsystem_vendor; /* VF subsystem vendor */
|
||||
u16 subsystem_device; /* VF subsystem device */
|
||||
resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
|
||||
bool drivers_autoprobe; /* Auto probing of VFs by driver */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -329,6 +329,10 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
|
|||
if (dev->non_compliant_bars)
|
||||
return;
|
||||
|
||||
/* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
|
||||
if (dev->is_virtfn)
|
||||
return;
|
||||
|
||||
for (pos = 0; pos < howmany; pos++) {
|
||||
struct resource *res = &dev->resource[pos];
|
||||
reg = PCI_BASE_ADDRESS_0 + (pos << 2);
|
||||
|
|
@ -1240,6 +1244,13 @@ static void pci_read_irq(struct pci_dev *dev)
|
|||
{
|
||||
unsigned char irq;
|
||||
|
||||
/* VFs are not allowed to use INTx, so skip the config reads */
|
||||
if (dev->is_virtfn) {
|
||||
dev->pin = 0;
|
||||
dev->irq = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
|
||||
dev->pin = irq;
|
||||
if (irq)
|
||||
|
|
@ -1399,6 +1410,43 @@ int pci_cfg_space_size(struct pci_dev *dev)
|
|||
return PCI_CFG_SPACE_SIZE;
|
||||
}
|
||||
|
||||
static u32 pci_class(struct pci_dev *dev)
|
||||
{
|
||||
u32 class;
|
||||
|
||||
#ifdef CONFIG_PCI_IOV
|
||||
if (dev->is_virtfn)
|
||||
return dev->physfn->sriov->class;
|
||||
#endif
|
||||
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
|
||||
return class;
|
||||
}
|
||||
|
||||
static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
|
||||
{
|
||||
#ifdef CONFIG_PCI_IOV
|
||||
if (dev->is_virtfn) {
|
||||
*vendor = dev->physfn->sriov->subsystem_vendor;
|
||||
*device = dev->physfn->sriov->subsystem_device;
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
|
||||
pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
|
||||
}
|
||||
|
||||
static u8 pci_hdr_type(struct pci_dev *dev)
|
||||
{
|
||||
u8 hdr_type;
|
||||
|
||||
#ifdef CONFIG_PCI_IOV
|
||||
if (dev->is_virtfn)
|
||||
return dev->physfn->sriov->hdr_type;
|
||||
#endif
|
||||
pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
|
||||
return hdr_type;
|
||||
}
|
||||
|
||||
#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
|
||||
|
||||
static void pci_msi_setup_pci_dev(struct pci_dev *dev)
|
||||
|
|
@ -1464,8 +1512,7 @@ int pci_setup_device(struct pci_dev *dev)
|
|||
struct pci_bus_region region;
|
||||
struct resource *res;
|
||||
|
||||
if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
|
||||
return -EIO;
|
||||
hdr_type = pci_hdr_type(dev);
|
||||
|
||||
dev->sysdata = dev->bus->sysdata;
|
||||
dev->dev.parent = dev->bus->bridge;
|
||||
|
|
@ -1487,7 +1534,8 @@ int pci_setup_device(struct pci_dev *dev)
|
|||
dev->bus->number, PCI_SLOT(dev->devfn),
|
||||
PCI_FUNC(dev->devfn));
|
||||
|
||||
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
|
||||
class = pci_class(dev);
|
||||
|
||||
dev->revision = class & 0xff;
|
||||
dev->class = class >> 8; /* upper 3 bytes */
|
||||
|
||||
|
|
@ -1527,8 +1575,8 @@ int pci_setup_device(struct pci_dev *dev)
|
|||
goto bad;
|
||||
pci_read_irq(dev);
|
||||
pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
|
||||
pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
|
||||
pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
|
||||
|
||||
pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
|
||||
|
||||
/*
|
||||
* Do the ugly legacy mode stuff here rather than broken chip
|
||||
|
|
@ -2131,6 +2179,9 @@ static void pci_init_capabilities(struct pci_dev *dev)
|
|||
|
||||
/* Advanced Error Reporting */
|
||||
pci_aer_init(dev);
|
||||
|
||||
if (pci_probe_reset_function(dev) == 0)
|
||||
dev->reset_fn = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -3888,6 +3888,9 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
|
|||
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
|
||||
quirk_dma_func1_alias);
|
||||
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
|
||||
quirk_dma_func1_alias);
|
||||
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
|
||||
quirk_dma_func1_alias);
|
||||
|
|
@ -4506,6 +4509,15 @@ static const struct pci_dev_acs_enabled {
|
|||
{ PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
|
||||
/* APM X-Gene */
|
||||
{ PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
|
||||
/* Ampere Computing */
|
||||
{ PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
|
||||
{ PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
|
||||
{ PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
|
||||
{ PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
|
||||
{ PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
|
||||
{ PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
|
||||
{ PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
|
||||
{ PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1085,7 +1085,7 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
|
|||
enum pci_bus_speed *speed,
|
||||
enum pcie_link_width *width);
|
||||
void pcie_print_link_status(struct pci_dev *dev);
|
||||
void pcie_flr(struct pci_dev *dev);
|
||||
int pcie_flr(struct pci_dev *dev);
|
||||
int __pci_reset_function_locked(struct pci_dev *dev);
|
||||
int pci_reset_function(struct pci_dev *dev);
|
||||
int pci_reset_function_locked(struct pci_dev *dev);
|
||||
|
|
@ -1098,7 +1098,7 @@ int pci_reset_bus(struct pci_bus *bus);
|
|||
int pci_try_reset_bus(struct pci_bus *bus);
|
||||
void pci_reset_secondary_bus(struct pci_dev *dev);
|
||||
void pcibios_reset_secondary_bus(struct pci_dev *dev);
|
||||
void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
|
||||
int pci_reset_bridge_secondary_bus(struct pci_dev *dev);
|
||||
void pci_update_resource(struct pci_dev *dev, int resno);
|
||||
int __must_check pci_assign_resource(struct pci_dev *dev, int i);
|
||||
int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
|
||||
|
|
@ -1299,7 +1299,6 @@ unsigned char pci_bus_max_busnr(struct pci_bus *bus);
|
|||
void pci_setup_bridge(struct pci_bus *bus);
|
||||
resource_size_t pcibios_window_alignment(struct pci_bus *bus,
|
||||
unsigned long type);
|
||||
resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
|
||||
|
||||
#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
|
||||
#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
|
||||
|
|
@ -1922,6 +1921,7 @@ void pcibios_release_device(struct pci_dev *dev);
|
|||
void pcibios_penalize_isa_irq(int irq, int active);
|
||||
int pcibios_alloc_irq(struct pci_dev *dev);
|
||||
void pcibios_free_irq(struct pci_dev *dev);
|
||||
resource_size_t pcibios_default_alignment(void);
|
||||
|
||||
#ifdef CONFIG_HIBERNATE_CALLBACKS
|
||||
extern struct dev_pm_ops pcibios_pm_ops;
|
||||
|
|
@ -1954,6 +1954,11 @@ int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
|
|||
int pci_sriov_get_totalvfs(struct pci_dev *dev);
|
||||
resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
|
||||
void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
|
||||
|
||||
/* Arch may override these (weak) */
|
||||
int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
|
||||
int pcibios_sriov_disable(struct pci_dev *pdev);
|
||||
resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
|
||||
#else
|
||||
static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1333,6 +1333,7 @@
|
|||
#define PCI_DEVICE_ID_IMS_TT3D 0x9135
|
||||
|
||||
#define PCI_VENDOR_ID_AMCC 0x10e8
|
||||
#define PCI_VENDOR_ID_AMPERE 0x1def
|
||||
|
||||
#define PCI_VENDOR_ID_INTERG 0x10ea
|
||||
#define PCI_DEVICE_ID_INTERG_1682 0x1682
|
||||
|
|
|
|||
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