OMAP: DMA: Replace read/write macros with functions
Prepare DMA library to get converted into DMA driver using platform device model and hwmod infrastucture(for omap2+, resource structures for omap1) The low level read/write macros are replaced with static inline functions and register offsets are handled through static register offset tables mapped through enumeration constants. These low level read/write functions along with static register offset tables will be moved to respective mach-omap dma files in the later patches of this series. There are no functionality changes with these changes except change in logic for handling 16bit registers of OMAP1. Signed-off-by: G, Manjunath Kondaiah <manjugk@ti.com> Tested-by: Kevin Hilman <khilman@deeprootsystems.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
G, Manjunath Kondaiah
Tony Lindgren
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447b8da5d7
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@ -27,136 +27,14 @@
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/* Hardware registers for omap1 */
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#define OMAP1_DMA_BASE (0xfffed800)
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#define OMAP1_DMA_GCR 0x400
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#define OMAP1_DMA_GSCR 0x404
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#define OMAP1_DMA_GRST 0x408
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#define OMAP1_DMA_HW_ID 0x442
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#define OMAP1_DMA_PCH2_ID 0x444
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#define OMAP1_DMA_PCH0_ID 0x446
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#define OMAP1_DMA_PCH1_ID 0x448
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#define OMAP1_DMA_PCHG_ID 0x44a
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#define OMAP1_DMA_PCHD_ID 0x44c
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#define OMAP1_DMA_CAPS_0_U 0x44e
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#define OMAP1_DMA_CAPS_0_L 0x450
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#define OMAP1_DMA_CAPS_1_U 0x452
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#define OMAP1_DMA_CAPS_1_L 0x454
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#define OMAP1_DMA_CAPS_2 0x456
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#define OMAP1_DMA_CAPS_3 0x458
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#define OMAP1_DMA_CAPS_4 0x45a
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#define OMAP1_DMA_PCH2_SR 0x460
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#define OMAP1_DMA_PCH0_SR 0x480
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#define OMAP1_DMA_PCH1_SR 0x482
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#define OMAP1_DMA_PCHD_SR 0x4c0
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/* Hardware registers for omap2 and omap3 */
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#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000)
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#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000)
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#define OMAP44XX_DMA4_BASE (L4_44XX_BASE + 0x56000)
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#define OMAP_DMA4_REVISION 0x00
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#define OMAP_DMA4_GCR 0x78
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#define OMAP_DMA4_IRQSTATUS_L0 0x08
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#define OMAP_DMA4_IRQSTATUS_L1 0x0c
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#define OMAP_DMA4_IRQSTATUS_L2 0x10
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#define OMAP_DMA4_IRQSTATUS_L3 0x14
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#define OMAP_DMA4_IRQENABLE_L0 0x18
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#define OMAP_DMA4_IRQENABLE_L1 0x1c
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#define OMAP_DMA4_IRQENABLE_L2 0x20
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#define OMAP_DMA4_IRQENABLE_L3 0x24
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#define OMAP_DMA4_SYSSTATUS 0x28
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#define OMAP_DMA4_OCP_SYSCONFIG 0x2c
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#define OMAP_DMA4_CAPS_0 0x64
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#define OMAP_DMA4_CAPS_2 0x6c
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#define OMAP_DMA4_CAPS_3 0x70
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#define OMAP_DMA4_CAPS_4 0x74
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#define OMAP1_LOGICAL_DMA_CH_COUNT 17
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#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
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/* Common channel specific registers for omap1 */
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#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00)
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#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00)
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#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02)
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#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04)
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#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06)
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#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10)
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#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12)
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#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14)
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#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16)
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#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */
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#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18)
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#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a)
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#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c)
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#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e)
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#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28)
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/* Common channel specific registers for omap2 */
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#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80)
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#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80)
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#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84)
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#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88)
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#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c)
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#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90)
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#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94)
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#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98)
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#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4)
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#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8)
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#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac)
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#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0)
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#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4)
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#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8)
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/* Channel specific registers only on omap1 */
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#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08)
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#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a)
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#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c)
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#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e)
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#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20)
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#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22)
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#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24)
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#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */
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#define OMAP1_DMA_CCEN(n) 0
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#define OMAP1_DMA_CCFN(n) 0
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/* Channel specific registers only on omap2 */
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#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c)
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#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0)
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#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc)
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#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0)
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#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4)
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/* Additional registers available on OMAP4 */
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#define OMAP_DMA4_CDP(n) (0x60 * (n) + 0xd0)
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#define OMAP_DMA4_CNDP(n) (0x60 * (n) + 0xd4)
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#define OMAP_DMA4_CCDN(n) (0x60 * (n) + 0xd8)
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/* Dummy defines to keep multi-omap compiles happy */
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#define OMAP1_DMA_REVISION 0
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#define OMAP1_DMA_IRQSTATUS_L0 0
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#define OMAP1_DMA_IRQENABLE_L0 0
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#define OMAP1_DMA_OCP_SYSCONFIG 0
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#define OMAP_DMA4_HW_ID 0
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#define OMAP_DMA4_CAPS_0_L 0
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#define OMAP_DMA4_CAPS_0_U 0
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#define OMAP_DMA4_CAPS_1_L 0
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#define OMAP_DMA4_CAPS_1_U 0
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#define OMAP_DMA4_GSCR 0
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#define OMAP_DMA4_CPC(n) 0
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#define OMAP_DMA4_LCH_CTRL(n) 0
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#define OMAP_DMA4_COLOR_L(n) 0
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#define OMAP_DMA4_COLOR_U(n) 0
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#define OMAP_DMA4_CCR2(n) 0
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#define OMAP1_DMA_CSSA(n) 0
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#define OMAP1_DMA_CDSA(n) 0
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#define OMAP_DMA4_CSSA_L(n) 0
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#define OMAP_DMA4_CSSA_U(n) 0
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#define OMAP_DMA4_CDSA_L(n) 0
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#define OMAP_DMA4_CDSA_U(n) 0
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#define OMAP1_DMA_COLOR(n) 0
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/*----------------------------------------------------------------------------*/
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/* DMA channels for omap1 */
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#define OMAP_DMA_NO_DEVICE 0
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#define OMAP_DMA_MCSI1_TX 1
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@ -405,6 +283,35 @@
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#define DMA_CH_PRIO_HIGH 0x1
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#define DMA_CH_PRIO_LOW 0x0 /* Def */
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enum omap_reg_offsets {
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GCR, GSCR, GRST1, HW_ID,
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PCH2_ID, PCH0_ID, PCH1_ID, PCHG_ID,
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PCHD_ID, CAPS_0, CAPS_1, CAPS_2,
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CAPS_3, CAPS_4, PCH2_SR, PCH0_SR,
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PCH1_SR, PCHD_SR, REVISION, IRQSTATUS_L0,
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IRQSTATUS_L1, IRQSTATUS_L2, IRQSTATUS_L3, IRQENABLE_L0,
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IRQENABLE_L1, IRQENABLE_L2, IRQENABLE_L3, SYSSTATUS,
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OCP_SYSCONFIG,
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/* omap1+ specific */
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CPC, CCR2, LCH_CTRL,
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/* Common registers for all omap's */
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CSDP, CCR, CICR, CSR,
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CEN, CFN, CSFI, CSEI,
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CSAC, CDAC, CDEI,
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CDFI, CLNK_CTRL,
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/* Channel specific registers */
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CSSA, CDSA, COLOR,
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CCEN, CCFN,
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/* omap3630 and omap4 specific */
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CDP, CNDP, CCDN,
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};
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enum omap_dma_burst_mode {
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OMAP_DMA_DATA_BURST_DIS = 0,
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OMAP_DMA_DATA_BURST_4,
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