iwlwifi: move ICT data to agn part of union
Since the ICT data is all AGN specific, it can be the first data to create the _agn part of the device-specific union in the priv struct. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
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Коммит
a4c8b2a692
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@ -42,11 +42,12 @@
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/* Free dram table */
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void iwl_free_isr_ict(struct iwl_priv *priv)
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{
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if (priv->ict_tbl_vir) {
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if (priv->_agn.ict_tbl_vir) {
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dma_free_coherent(&priv->pci_dev->dev,
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(sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
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priv->ict_tbl_vir, priv->ict_tbl_dma);
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priv->ict_tbl_vir = NULL;
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priv->_agn.ict_tbl_vir,
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priv->_agn.ict_tbl_dma);
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priv->_agn.ict_tbl_vir = NULL;
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}
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}
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@ -60,30 +61,31 @@ int iwl_alloc_isr_ict(struct iwl_priv *priv)
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if (priv->cfg->use_isr_legacy)
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return 0;
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/* allocate shrared data table */
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priv->ict_tbl_vir = dma_alloc_coherent(&priv->pci_dev->dev,
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(sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
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&priv->ict_tbl_dma, GFP_KERNEL);
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if (!priv->ict_tbl_vir)
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priv->_agn.ict_tbl_vir =
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dma_alloc_coherent(&priv->pci_dev->dev,
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(sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
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&priv->_agn.ict_tbl_dma, GFP_KERNEL);
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if (!priv->_agn.ict_tbl_vir)
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return -ENOMEM;
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/* align table to PAGE_SIZE boundry */
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priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE);
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priv->_agn.aligned_ict_tbl_dma = ALIGN(priv->_agn.ict_tbl_dma, PAGE_SIZE);
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IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
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(unsigned long long)priv->ict_tbl_dma,
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(unsigned long long)priv->aligned_ict_tbl_dma,
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(int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
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(unsigned long long)priv->_agn.ict_tbl_dma,
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(unsigned long long)priv->_agn.aligned_ict_tbl_dma,
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(int)(priv->_agn.aligned_ict_tbl_dma - priv->_agn.ict_tbl_dma));
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priv->ict_tbl = priv->ict_tbl_vir +
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(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma);
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priv->_agn.ict_tbl = priv->_agn.ict_tbl_vir +
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(priv->_agn.aligned_ict_tbl_dma - priv->_agn.ict_tbl_dma);
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IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
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priv->ict_tbl, priv->ict_tbl_vir,
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(int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
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priv->_agn.ict_tbl, priv->_agn.ict_tbl_vir,
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(int)(priv->_agn.aligned_ict_tbl_dma - priv->_agn.ict_tbl_dma));
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/* reset table and index to all 0 */
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memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
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priv->ict_index = 0;
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memset(priv->_agn.ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
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priv->_agn.ict_index = 0;
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/* add periodic RX interrupt */
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priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
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@ -98,26 +100,26 @@ int iwl_reset_ict(struct iwl_priv *priv)
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u32 val;
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unsigned long flags;
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if (!priv->ict_tbl_vir)
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if (!priv->_agn.ict_tbl_vir)
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return 0;
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spin_lock_irqsave(&priv->lock, flags);
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iwl_disable_interrupts(priv);
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memset(&priv->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
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memset(&priv->_agn.ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
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val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT;
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val = priv->_agn.aligned_ict_tbl_dma >> PAGE_SHIFT;
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val |= CSR_DRAM_INT_TBL_ENABLE;
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val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
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IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
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"aligned dma address %Lx\n",
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val, (unsigned long long)priv->aligned_ict_tbl_dma);
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val, (unsigned long long)priv->_agn.aligned_ict_tbl_dma);
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iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
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priv->use_ict = true;
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priv->ict_index = 0;
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priv->_agn.use_ict = true;
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priv->_agn.ict_index = 0;
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iwl_write32(priv, CSR_INT, priv->inta_mask);
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iwl_enable_interrupts(priv);
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spin_unlock_irqrestore(&priv->lock, flags);
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@ -131,7 +133,7 @@ void iwl_disable_ict(struct iwl_priv *priv)
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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priv->use_ict = false;
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priv->_agn.use_ict = false;
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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@ -180,11 +182,11 @@ static irqreturn_t iwl_isr(int irq, void *data)
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}
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#endif
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priv->inta |= inta;
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priv->_agn.inta |= inta;
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/* iwl_irq_tasklet() will service interrupts and re-enable them */
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if (likely(inta))
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tasklet_schedule(&priv->irq_tasklet);
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else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
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else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta)
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iwl_enable_interrupts(priv);
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unplugged:
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@ -194,7 +196,7 @@ static irqreturn_t iwl_isr(int irq, void *data)
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none:
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/* re-enable interrupts here since we don't have anything to service. */
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/* only Re-enable if diabled by irq and no schedules tasklet. */
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if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
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if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta)
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iwl_enable_interrupts(priv);
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spin_unlock(&priv->lock);
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@ -221,7 +223,7 @@ irqreturn_t iwl_isr_ict(int irq, void *data)
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/* dram interrupt table not set yet,
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* use legacy interrupt.
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*/
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if (!priv->use_ict)
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if (!priv->_agn.use_ict)
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return iwl_isr(irq, data);
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spin_lock(&priv->lock);
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@ -238,20 +240,20 @@ irqreturn_t iwl_isr_ict(int irq, void *data)
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/* Ignore interrupt if there's nothing in NIC to service.
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* This may be due to IRQ shared with another device,
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* or due to sporadic interrupts thrown from our NIC. */
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if (!priv->ict_tbl[priv->ict_index]) {
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if (!priv->_agn.ict_tbl[priv->_agn.ict_index]) {
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IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
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goto none;
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}
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/* read all entries that not 0 start with ict_index */
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while (priv->ict_tbl[priv->ict_index]) {
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while (priv->_agn.ict_tbl[priv->_agn.ict_index]) {
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val |= le32_to_cpu(priv->ict_tbl[priv->ict_index]);
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val |= le32_to_cpu(priv->_agn.ict_tbl[priv->_agn.ict_index]);
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IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
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priv->ict_index,
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le32_to_cpu(priv->ict_tbl[priv->ict_index]));
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priv->ict_tbl[priv->ict_index] = 0;
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priv->ict_index = iwl_queue_inc_wrap(priv->ict_index,
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priv->_agn.ict_index,
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le32_to_cpu(priv->_agn.ict_tbl[priv->_agn.ict_index]));
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priv->_agn.ict_tbl[priv->_agn.ict_index] = 0;
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priv->_agn.ict_index = iwl_queue_inc_wrap(priv->_agn.ict_index,
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ICT_COUNT);
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}
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@ -275,12 +277,12 @@ irqreturn_t iwl_isr_ict(int irq, void *data)
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inta, inta_mask, val);
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inta &= priv->inta_mask;
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priv->inta |= inta;
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priv->_agn.inta |= inta;
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/* iwl_irq_tasklet() will service interrupts and re-enable them */
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if (likely(inta))
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tasklet_schedule(&priv->irq_tasklet);
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else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) {
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else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta) {
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/* Allow interrupt if was disabled by this handler and
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* no tasklet was schedules, We should not enable interrupt,
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* tasklet will enable it.
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@ -295,7 +297,7 @@ irqreturn_t iwl_isr_ict(int irq, void *data)
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/* re-enable interrupts here since we don't have anything to service.
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* only Re-enable if disabled by irq.
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*/
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if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
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if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta)
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iwl_enable_interrupts(priv);
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spin_unlock(&priv->lock);
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@ -1259,9 +1259,9 @@ static void iwl_irq_tasklet(struct iwl_priv *priv)
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/* Ack/clear/reset pending uCode interrupts.
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* Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
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*/
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iwl_write32(priv, CSR_INT, priv->inta);
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iwl_write32(priv, CSR_INT, priv->_agn.inta);
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inta = priv->inta;
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inta = priv->_agn.inta;
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#ifdef CONFIG_IWLWIFI_DEBUG
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if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
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@ -1274,8 +1274,8 @@ static void iwl_irq_tasklet(struct iwl_priv *priv)
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spin_unlock_irqrestore(&priv->lock, flags);
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/* saved interrupt in inta variable now we can reset priv->inta */
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priv->inta = 0;
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/* saved interrupt in inta variable now we can reset priv->_agn.inta */
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priv->_agn.inta = 0;
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/* Now service all interrupt bits discovered above. */
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if (inta & CSR_INT_BIT_HW_ERR) {
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@ -1275,20 +1275,23 @@ struct iwl_priv {
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u32 sta_supp_rates;
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} _3945;
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#endif
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#if defined(CONFIG_IWLAGN) || defined(CONFIG_IWLAGN_MODULE)
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struct {
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/* INT ICT Table */
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__le32 *ict_tbl;
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void *ict_tbl_vir;
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dma_addr_t ict_tbl_dma;
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dma_addr_t aligned_ict_tbl_dma;
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int ict_index;
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u32 inta;
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bool use_ict;
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} _agn;
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#endif
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};
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struct iwl_hw_params hw_params;
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/* INT ICT Table */
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__le32 *ict_tbl;
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dma_addr_t ict_tbl_dma;
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dma_addr_t aligned_ict_tbl_dma;
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int ict_index;
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void *ict_tbl_vir;
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u32 inta;
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bool use_ict;
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u32 inta_mask;
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/* Current association information needed to configure the
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* hardware */
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