ARM: Marvell MMP SoC patches for v5.5
This tag includes initial support for the Marvell MMP3 processor. MMP3 is used in OLPC XO-4 laptops, Panasonic Toughpad FZ-A1 tablet and Dell Wyse 3020/Tx0D thin clients. -----BEGIN PGP SIGNATURE----- iQFDBAABCAAtFiEENyn6vISEy07peidTpxZjkszkJRYFAl2ofPMPHGxrdW5kcmFr QHYzLnNrAAoJEKcWY5LM5CUWcI4H/RlhFZ1Nngu8P19ZPb66GCf27SKgAXvucocN na6EPBmL+vB0BnlpkXTOtvsOL6riSat/DnUgg4gyCQFVV1SAZdEjnnVAFCEyWSWU Omc4XDxh6b/geelCElGVCcnomCWvibrkKny1a8bViJdJbVb3lvSou4ZLNNv55uoh OamyM2yxCgDNQRlvaizfGNbzOCedfCHnFV3eyNx1kMe+OGcSuJe+AZ6Toh045fb9 GWTMeG80AJhWtowcpB5Ivrh31XR3PScOGDOwOlqbyAOao/MalRsBx2Yz+XQ/IceL RivJ/ImeY/czjFSn2DrsV/nlQDhHP3fjxrtZyUNFV6A8EkHSX0M= =1Ju7 -----END PGP SIGNATURE----- Merge tag 'mmp-soc-for-v5.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp into arm/soc ARM: Marvell MMP SoC patches for v5.5 This tag includes initial support for the Marvell MMP3 processor. MMP3 is used in OLPC XO-4 laptops, Panasonic Toughpad FZ-A1 tablet and Dell Wyse 3020/Tx0D thin clients. * tag 'mmp-soc-for-v5.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp: MAINTAINERS: mmp: add Git repository ARM: mmp: remove MMP3 USB PHY registers from regs-usb.h ARM: mmp: move cputype.h to include/linux/soc/ ARM: mmp: add SMP support ARM: mmp: add support for MMP3 SoC ARM: mmp: define MMP_CHIPID by the means of CIU_REG() ARM: mmp: DT: convert timer driver to use TIMER_OF_DECLARE ARM: mmp: map the PGU as well ARM: mmp: don't select CACHE_TAUROS2 on all ARCH_MMP ARM: l2c: add definition for FWA in PL310 aux register Link: https://lore.kernel.org/r/3a035bed90f9d8acc49b2d11d20089b546062aea.camel@v3.sk Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
Коммит
a4e86630a1
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@ -10909,9 +10909,11 @@ F: drivers/media/radio/radio-miropcm20*
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MMP SUPPORT
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R: Lubomir Rintel <lkundrak@v3.sk>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp.git
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S: Odd Fixes
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F: arch/arm/boot/dts/mmp*
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F: arch/arm/mach-mmp/
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F: linux/soc/mmp/
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MMU GATHER AND TLB INVALIDATION
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M: Will Deacon <will@kernel.org>
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@ -118,6 +118,8 @@
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#define L310_AUX_CTRL_STORE_LIMITATION BIT(11) /* R2P0+ */
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#define L310_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
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#define L310_AUX_CTRL_ASSOCIATIVITY_16 BIT(16)
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#define L310_AUX_CTRL_FWA_SHIFT 23
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#define L310_AUX_CTRL_FWA_MASK (3 << 23)
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#define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */
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#define L310_AUX_CTRL_NS_LOCKDOWN BIT(26)
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#define L310_AUX_CTRL_NS_INT_CTRL BIT(27)
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@ -1,13 +1,13 @@
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# SPDX-License-Identifier: GPL-2.0-only
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menuconfig ARCH_MMP
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bool "Marvell PXA168/910/MMP2"
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bool "Marvell PXA168/910/MMP2/MMP3"
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depends on ARCH_MULTI_V5 || ARCH_MULTI_V7
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select GPIO_PXA
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select GPIOLIB
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select PINCTRL
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select PLAT_PXA
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help
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Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
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Support for Marvell's PXA168/PXA910(MMP), MMP2, and MMP3 processor lines.
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if ARCH_MMP
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@ -129,6 +129,24 @@ config MACH_MMP2_DT
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Include support for Marvell MMP2 based platforms using
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the device tree.
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config MACH_MMP3_DT
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bool "Support MMP3 (ARMv7) platforms"
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depends on ARCH_MULTI_V7
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select ARM_GIC
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select HAVE_ARM_SCU if SMP
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select HAVE_ARM_TWD if SMP
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select CACHE_L2X0
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select PINCTRL
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select PINCTRL_SINGLE
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select ARCH_HAS_RESET_CONTROLLER
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select CPU_PJ4B
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select PM_GENERIC_DOMAINS if PM
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select PM_GENERIC_DOMAINS_OF if PM && OF
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help
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Say 'Y' here if you want to include support for platforms
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with Marvell MMP3 processor, also known as PXA2128 or
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Armada 620.
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endmenu
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config CPU_PXA168
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@ -22,6 +22,9 @@ ifeq ($(CONFIG_PM),y)
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obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o
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obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o
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endif
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ifeq ($(CONFIG_SMP),y)
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obj-$(CONFIG_MACH_MMP3_DT) += platsmp.o
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endif
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# board support
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obj-$(CONFIG_MACH_ASPENITE) += aspenite.o
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@ -34,5 +37,6 @@ obj-$(CONFIG_MACH_FLINT) += flint.o
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obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
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obj-$(CONFIG_MACH_MMP_DT) += mmp-dt.o
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obj-$(CONFIG_MACH_MMP2_DT) += mmp2-dt.o
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obj-$(CONFIG_MACH_MMP3_DT) += mmp3.o
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obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o
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obj-$(CONFIG_MACH_GPLUGD) += gplugd.o
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@ -20,6 +20,10 @@
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#define AXI_VIRT_BASE IOMEM(0xfe200000)
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#define AXI_PHYS_SIZE 0x00200000
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#define PGU_PHYS_BASE 0xe0000000
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#define PGU_VIRT_BASE IOMEM(0xfe400000)
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#define PGU_PHYS_SIZE 0x00100000
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/* Static Memory Controller - Chip Select 0 and 1 */
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#define SMC_CS0_PHYS_BASE 0x80000000
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#define SMC_CS0_PHYS_SIZE 0x10000000
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@ -38,4 +42,7 @@
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#define CIU_VIRT_BASE (AXI_VIRT_BASE + 0x82c00)
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#define CIU_REG(x) (CIU_VIRT_BASE + (x))
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#define SCU_VIRT_BASE (PGU_VIRT_BASE)
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#define SCU_REG(x) (SCU_VIRT_BASE + (x))
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#endif /* __ASM_MACH_ADDR_MAP_H */
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@ -13,11 +13,11 @@
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#include <asm/mach/map.h>
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#include <asm/system_misc.h>
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#include "addr-map.h"
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#include "cputype.h"
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#include <linux/soc/mmp/cputype.h>
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#include "common.h"
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#define MMP_CHIPID (AXI_VIRT_BASE + 0x82c00)
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#define MMP_CHIPID CIU_REG(0x00)
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unsigned int mmp_chip_id;
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EXPORT_SYMBOL(mmp_chip_id);
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@ -36,6 +36,15 @@ static struct map_desc standard_io_desc[] __initdata = {
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},
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};
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static struct map_desc mmp2_io_desc[] __initdata = {
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{
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.pfn = __phys_to_pfn(PGU_PHYS_BASE),
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.virtual = (unsigned long)PGU_VIRT_BASE,
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.length = PGU_PHYS_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init mmp_map_io(void)
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{
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iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
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@ -44,6 +53,12 @@ void __init mmp_map_io(void)
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mmp_chip_id = __raw_readl(MMP_CHIPID);
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}
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void __init mmp2_map_io(void)
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{
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mmp_map_io();
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iotable_init(mmp2_io_desc, ARRAY_SIZE(mmp2_io_desc));
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}
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void mmp_restart(enum reboot_mode mode, const char *cmd)
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{
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soft_restart(0);
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@ -5,4 +5,5 @@
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extern void mmp_timer_init(int irq, unsigned long rate);
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extern void __init mmp_map_io(void);
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extern void __init mmp2_map_io(void);
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extern void mmp_restart(enum reboot_mode, const char *);
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@ -11,7 +11,7 @@
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#include <asm/irq.h>
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#include "irqs.h"
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#include "devices.h"
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#include "cputype.h"
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#include <linux/soc/mmp/cputype.h>
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#include "regs-usb.h"
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int __init pxa_register_device(struct pxa_device_desc *desc,
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@ -9,14 +9,13 @@
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#include <linux/irqchip.h>
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#include <linux/of_platform.h>
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#include <linux/clk-provider.h>
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#include <linux/clocksource.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include <asm/hardware/cache-tauros2.h>
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#include "common.h"
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extern void __init mmp_dt_init_timer(void);
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static const char *const pxa168_dt_board_compat[] __initconst = {
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"mrvl,pxa168-aspenite",
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NULL,
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@ -32,8 +31,8 @@ static void __init mmp_init_time(void)
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#ifdef CONFIG_CACHE_TAUROS2
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tauros2_init(0);
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#endif
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mmp_dt_init_timer();
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of_clk_init(NULL);
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timer_probe();
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}
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DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
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@ -10,21 +10,20 @@
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#include <linux/irqchip.h>
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#include <linux/of_platform.h>
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#include <linux/clk-provider.h>
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#include <linux/clocksource.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include <asm/hardware/cache-tauros2.h>
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#include "common.h"
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extern void __init mmp_dt_init_timer(void);
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static void __init mmp_init_time(void)
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{
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#ifdef CONFIG_CACHE_TAUROS2
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tauros2_init(0);
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#endif
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of_clk_init(NULL);
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mmp_dt_init_timer();
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timer_probe();
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}
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static const char *const mmp2_dt_board_compat[] __initconst = {
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@ -33,7 +32,7 @@ static const char *const mmp2_dt_board_compat[] __initconst = {
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};
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DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
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.map_io = mmp_map_io,
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.map_io = mmp2_map_io,
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.init_time = mmp_init_time,
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.dt_compat = mmp2_dt_board_compat,
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MACHINE_END
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@ -20,7 +20,7 @@
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#include <asm/mach/time.h>
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#include "addr-map.h"
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#include "regs-apbc.h"
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#include "cputype.h"
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#include <linux/soc/mmp/cputype.h>
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#include "irqs.h"
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#include "mfp.h"
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#include "devices.h"
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@ -0,0 +1,29 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Marvell MMP3 aka PXA2128 aka 88AP2128 support
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*
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* Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
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*/
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/of_platform.h>
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#include <linux/clk-provider.h>
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#include <asm/mach/arch.h>
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#include <asm/hardware/cache-l2x0.h>
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#include "common.h"
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static const char *const mmp3_dt_board_compat[] __initconst = {
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"marvell,mmp3",
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NULL,
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};
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DT_MACHINE_START(MMP2_DT, "Marvell MMP3")
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.map_io = mmp2_map_io,
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.dt_compat = mmp3_dt_board_compat,
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.l2c_aux_val = 1 << L310_AUX_CTRL_FWA_SHIFT |
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L310_AUX_CTRL_DATA_PREFETCH |
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L310_AUX_CTRL_INSTR_PREFETCH,
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.l2c_aux_mask = 0xc20fffff,
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MACHINE_END
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@ -0,0 +1,32 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
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*/
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#include <linux/io.h>
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#include <asm/smp_scu.h>
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#include <asm/smp.h>
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#include "addr-map.h"
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#define SW_BRANCH_VIRT_ADDR CIU_REG(0x24)
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static int mmp3_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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/*
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* Apparently, the boot ROM on the second core spins on this
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* register becoming non-zero and then jumps to the address written
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* there. No IPIs involved.
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*/
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__raw_writel(__pa_symbol(secondary_startup), SW_BRANCH_VIRT_ADDR);
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return 0;
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}
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static void mmp3_smp_prepare_cpus(unsigned int max_cpus)
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{
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scu_enable(SCU_VIRT_BASE);
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}
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static const struct smp_operations mmp3_smp_ops __initconst = {
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.smp_prepare_cpus = mmp3_smp_prepare_cpus,
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.smp_boot_secondary = mmp3_boot_secondary,
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};
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CPU_METHOD_OF_DECLARE(mmp3_smp, "marvell,mmp3-smp", &mmp3_smp_ops);
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@ -17,7 +17,7 @@
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#include <linux/interrupt.h>
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#include <asm/mach-types.h>
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#include "cputype.h"
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#include <linux/soc/mmp/cputype.h>
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#include "addr-map.h"
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#include "pm-mmp2.h"
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#include "regs-icu.h"
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@ -18,7 +18,7 @@
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#include <asm/mach-types.h>
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#include <asm/outercache.h>
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#include "cputype.h"
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#include <linux/soc/mmp/cputype.h>
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#include "addr-map.h"
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#include "pm-pxa910.h"
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#include "regs-icu.h"
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@ -21,7 +21,7 @@
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#include "addr-map.h"
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#include "clock.h"
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#include "common.h"
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#include "cputype.h"
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#include <linux/soc/mmp/cputype.h>
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#include "devices.h"
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#include "irqs.h"
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#include "mfp.h"
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@ -18,7 +18,7 @@
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#include <asm/mach/time.h>
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#include "addr-map.h"
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#include "regs-apbc.h"
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#include "cputype.h"
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#include <linux/soc/mmp/cputype.h>
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#include "irqs.h"
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#include "mfp.h"
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#include "devices.h"
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@ -121,100 +121,6 @@
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#define UTMI_OTG_ADDON_OTG_ON (1 << 0)
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/* For MMP3 USB Phy */
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#define USB2_PLL_REG0 0x4
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#define USB2_PLL_REG1 0x8
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#define USB2_TX_REG0 0x10
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#define USB2_TX_REG1 0x14
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#define USB2_TX_REG2 0x18
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#define USB2_RX_REG0 0x20
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#define USB2_RX_REG1 0x24
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#define USB2_RX_REG2 0x28
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#define USB2_ANA_REG0 0x30
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#define USB2_ANA_REG1 0x34
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#define USB2_ANA_REG2 0x38
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#define USB2_DIG_REG0 0x3C
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#define USB2_DIG_REG1 0x40
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#define USB2_DIG_REG2 0x44
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#define USB2_DIG_REG3 0x48
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#define USB2_TEST_REG0 0x4C
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#define USB2_TEST_REG1 0x50
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#define USB2_TEST_REG2 0x54
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#define USB2_CHARGER_REG0 0x58
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#define USB2_OTG_REG0 0x5C
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#define USB2_PHY_MON0 0x60
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#define USB2_RESETVE_REG0 0x64
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#define USB2_ICID_REG0 0x78
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#define USB2_ICID_REG1 0x7C
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/* USB2_PLL_REG0 */
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/* This is for Ax stepping */
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#define USB2_PLL_FBDIV_SHIFT_MMP3 0
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#define USB2_PLL_FBDIV_MASK_MMP3 (0xFF << 0)
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#define USB2_PLL_REFDIV_SHIFT_MMP3 8
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#define USB2_PLL_REFDIV_MASK_MMP3 (0xF << 8)
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#define USB2_PLL_VDD12_SHIFT_MMP3 12
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#define USB2_PLL_VDD18_SHIFT_MMP3 14
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/* This is for B0 stepping */
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#define USB2_PLL_FBDIV_SHIFT_MMP3_B0 0
|
||||
#define USB2_PLL_REFDIV_SHIFT_MMP3_B0 9
|
||||
#define USB2_PLL_VDD18_SHIFT_MMP3_B0 14
|
||||
#define USB2_PLL_FBDIV_MASK_MMP3_B0 0x01FF
|
||||
#define USB2_PLL_REFDIV_MASK_MMP3_B0 0x3E00
|
||||
|
||||
#define USB2_PLL_CAL12_SHIFT_MMP3 0
|
||||
#define USB2_PLL_CALI12_MASK_MMP3 (0x3 << 0)
|
||||
|
||||
#define USB2_PLL_VCOCAL_START_SHIFT_MMP3 2
|
||||
|
||||
#define USB2_PLL_KVCO_SHIFT_MMP3 4
|
||||
#define USB2_PLL_KVCO_MASK_MMP3 (0x7<<4)
|
||||
|
||||
#define USB2_PLL_ICP_SHIFT_MMP3 8
|
||||
#define USB2_PLL_ICP_MASK_MMP3 (0x7<<8)
|
||||
|
||||
#define USB2_PLL_LOCK_BYPASS_SHIFT_MMP3 12
|
||||
|
||||
#define USB2_PLL_PU_PLL_SHIFT_MMP3 13
|
||||
#define USB2_PLL_PU_PLL_MASK (0x1 << 13)
|
||||
|
||||
#define USB2_PLL_READY_MASK_MMP3 (0x1 << 15)
|
||||
|
||||
/* USB2_TX_REG0 */
|
||||
#define USB2_TX_IMPCAL_VTH_SHIFT_MMP3 8
|
||||
#define USB2_TX_IMPCAL_VTH_MASK_MMP3 (0x7 << 8)
|
||||
|
||||
#define USB2_TX_RCAL_START_SHIFT_MMP3 13
|
||||
|
||||
/* USB2_TX_REG1 */
|
||||
#define USB2_TX_CK60_PHSEL_SHIFT_MMP3 0
|
||||
#define USB2_TX_CK60_PHSEL_MASK_MMP3 (0xf << 0)
|
||||
|
||||
#define USB2_TX_AMP_SHIFT_MMP3 4
|
||||
#define USB2_TX_AMP_MASK_MMP3 (0x7 << 4)
|
||||
|
||||
#define USB2_TX_VDD12_SHIFT_MMP3 8
|
||||
#define USB2_TX_VDD12_MASK_MMP3 (0x3 << 8)
|
||||
|
||||
/* USB2_TX_REG2 */
|
||||
#define USB2_TX_DRV_SLEWRATE_SHIFT 10
|
||||
|
||||
/* USB2_RX_REG0 */
|
||||
#define USB2_RX_SQ_THRESH_SHIFT_MMP3 4
|
||||
#define USB2_RX_SQ_THRESH_MASK_MMP3 (0xf << 4)
|
||||
|
||||
#define USB2_RX_SQ_LENGTH_SHIFT_MMP3 10
|
||||
#define USB2_RX_SQ_LENGTH_MASK_MMP3 (0x3 << 10)
|
||||
|
||||
/* USB2_ANA_REG1*/
|
||||
#define USB2_ANA_PU_ANA_SHIFT_MMP3 14
|
||||
|
||||
/* USB2_OTG_REG0 */
|
||||
#define USB2_OTG_PU_OTG_SHIFT_MMP3 3
|
||||
|
||||
/* fsic registers */
|
||||
#define FSIC_MISC 0x4
|
||||
#define FSIC_INT 0x28
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@
|
|||
#include "regs-timers.h"
|
||||
#include "regs-apbc.h"
|
||||
#include "irqs.h"
|
||||
#include "cputype.h"
|
||||
#include <linux/soc/mmp/cputype.h>
|
||||
#include "clock.h"
|
||||
|
||||
#define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
|
||||
|
|
@ -155,7 +155,8 @@ static void __init timer_config(void)
|
|||
|
||||
__raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
|
||||
|
||||
ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
|
||||
ccr &= (cpu_is_mmp2() || cpu_is_mmp3()) ?
|
||||
(TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
|
||||
(TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
|
||||
__raw_writel(ccr, mmp_timer_base + TMR_CCR);
|
||||
|
||||
|
|
@ -195,30 +196,17 @@ void __init mmp_timer_init(int irq, unsigned long rate)
|
|||
clockevents_config_and_register(&ckevt, rate, MIN_DELTA, MAX_DELTA);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static const struct of_device_id mmp_timer_dt_ids[] = {
|
||||
{ .compatible = "mrvl,mmp-timer", },
|
||||
{}
|
||||
};
|
||||
|
||||
void __init mmp_dt_init_timer(void)
|
||||
static int __init mmp_dt_init_timer(struct device_node *np)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct clk *clk;
|
||||
int irq, ret;
|
||||
unsigned long rate;
|
||||
|
||||
np = of_find_matching_node(NULL, mmp_timer_dt_ids);
|
||||
if (!np) {
|
||||
ret = -ENODEV;
|
||||
goto out;
|
||||
}
|
||||
|
||||
clk = of_clk_get(np, 0);
|
||||
if (!IS_ERR(clk)) {
|
||||
ret = clk_prepare_enable(clk);
|
||||
if (ret)
|
||||
goto out;
|
||||
return ret;
|
||||
rate = clk_get_rate(clk) / 2;
|
||||
} else if (cpu_is_pj4()) {
|
||||
rate = 6500000;
|
||||
|
|
@ -227,18 +215,15 @@ void __init mmp_dt_init_timer(void)
|
|||
}
|
||||
|
||||
irq = irq_of_parse_and_map(np, 0);
|
||||
if (!irq) {
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
if (!irq)
|
||||
return -EINVAL;
|
||||
|
||||
mmp_timer_base = of_iomap(np, 0);
|
||||
if (!mmp_timer_base) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
if (!mmp_timer_base)
|
||||
return -ENOMEM;
|
||||
|
||||
mmp_timer_init(irq, rate);
|
||||
return;
|
||||
out:
|
||||
pr_err("Failed to get timer from device tree with error:%d\n", ret);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
TIMER_OF_DECLARE(mmp_timer, "mrvl,mmp-timer", mmp_dt_init_timer);
|
||||
|
|
|
|||
|
|
@ -1041,7 +1041,7 @@ endif
|
|||
|
||||
config CACHE_TAUROS2
|
||||
bool "Enable the Tauros2 L2 cache controller"
|
||||
depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
|
||||
depends on (CPU_MOHAWK || CPU_PJ4)
|
||||
default y
|
||||
select OUTER_CACHE
|
||||
help
|
||||
|
|
|
|||
|
|
@ -292,6 +292,11 @@ config COMMON_CLK_STM32H7
|
|||
help
|
||||
Support for stm32h7 SoC family clocks
|
||||
|
||||
config COMMON_CLK_MMP2
|
||||
def_bool COMMON_CLK && (MACH_MMP2_DT || MACH_MMP3_DT)
|
||||
help
|
||||
Support for Marvell MMP2 and MMP3 SoC clocks
|
||||
|
||||
config COMMON_CLK_BD718XX
|
||||
tristate "Clock driver for ROHM BD718x7 PMIC"
|
||||
depends on MFD_ROHM_BD718XX || MFD_ROHM_BD70528
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o clk.o
|
|||
obj-$(CONFIG_RESET_CONTROLLER) += reset.o
|
||||
|
||||
obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o
|
||||
obj-$(CONFIG_MACH_MMP2_DT) += clk-of-mmp2.o
|
||||
obj-$(CONFIG_COMMON_CLK_MMP2) += clk-of-mmp2.o
|
||||
|
||||
obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
|
||||
obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
|
||||
|
|
|
|||
|
|
@ -633,6 +633,7 @@ header-test- += linux/soc/amlogic/meson-canvas.h
|
|||
header-test- += linux/soc/brcmstb/brcmstb.h
|
||||
header-test- += linux/soc/ixp4xx/npe.h
|
||||
header-test- += linux/soc/mediatek/infracfg.h
|
||||
header-test- += linux/soc/mmp/cputype.h
|
||||
header-test- += linux/soc/qcom/smd-rpm.h
|
||||
header-test- += linux/soc/qcom/smem.h
|
||||
header-test- += linux/soc/qcom/smem_state.h
|
||||
|
|
|
|||
|
|
@ -18,6 +18,8 @@
|
|||
* MMP2 Z0 0x560f5811 0x00F00410
|
||||
* MMP2 Z1 0x560f5811 0x00E00410
|
||||
* MMP2 A0 0x560f5811 0x00A0A610
|
||||
* MMP3 A0 0x562f5842 0x00A02128
|
||||
* MMP3 B0 0x562f5842 0x00B02128
|
||||
*/
|
||||
|
||||
extern unsigned int mmp_chip_id;
|
||||
|
|
@ -55,4 +57,29 @@ static inline int cpu_is_mmp2(void)
|
|||
#define cpu_is_mmp2() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_MMP3_DT
|
||||
static inline int cpu_is_mmp3(void)
|
||||
{
|
||||
return (((read_cpuid_id() >> 8) & 0xff) == 0x58) &&
|
||||
((mmp_chip_id & 0xffff) == 0x2128);
|
||||
}
|
||||
|
||||
static inline int cpu_is_mmp3_a0(void)
|
||||
{
|
||||
return (cpu_is_mmp3() &&
|
||||
((mmp_chip_id & 0x00ff0000) == 0x00a00000));
|
||||
}
|
||||
|
||||
static inline int cpu_is_mmp3_b0(void)
|
||||
{
|
||||
return (cpu_is_mmp3() &&
|
||||
((mmp_chip_id & 0x00ff0000) == 0x00b00000));
|
||||
}
|
||||
|
||||
#else
|
||||
#define cpu_is_mmp3() (0)
|
||||
#define cpu_is_mmp3_a0() (0)
|
||||
#define cpu_is_mmp3_b0() (0)
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_MACH_CPUTYPE_H */
|
||||
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