ASoC: Changes for v4.1
A selection of changes for v4.1 so far. The main things are: - Move of jack registration to the card where it belongs. - Support for DAPM routes specified by both the machine driver and DT. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJU960DAAoJECTWi3JdVIfQkKIH/RDvxRn8dvKOPF5U9Uix3chH JWKkzqfsMP0EpmQTzCQPp0ShAyYcWSbYsopicynPxUem5vS4Z8+UmOgEEgkj59pK USbF6v1jCQXA6BcbKyUcRRBD9FtRkfVDc7mYbRs2CcwQz2CGCgee41cvPM+2BT+z QdNC9UJARSweGvE1IUJSfpfYOly+BJ2s0/28RaQ0PGt+I0auoYx7IMFgMSDjv2p6 PY0kyQiwm3Kyj2uNXPZ5gEuPxlw/t8n4fbQNrBYAvxzN+EF5NrGdKE3N7MI1xRV/ EkFhzy+uM3X9c37tb2lT2fgPFlBc9rgPuLPSyoQ6nxa5ghCqAlgRhzpxRem8hhU= =VlCw -----END PGP SIGNATURE----- Merge tag 'asoc-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-next ASoC: Changes for v4.1 A selection of changes for v4.1 so far. The main things are: - Move of jack registration to the card where it belongs. - Support for DAPM routes specified by both the machine driver and DT.
This commit is contained in:
Коммит
a52afea68f
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@ -404,8 +404,8 @@ supported and the interface files "release_agent" and
|
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be understood as an underflow into the highest possible value, -2 or
|
||||
-10M etc. do not work, so it's not consistent.
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||||
|
||||
memory.low, memory.high, and memory.max will use the string
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||||
"infinity" to indicate and set the highest possible value.
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||||
memory.low, memory.high, and memory.max will use the string "max" to
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indicate and set the highest possible value.
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5. Planned Changes
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@ -18,6 +18,7 @@ Required properties:
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* Headphones
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* Speakers
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* Mic Jack
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* Int Mic
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- nvidia,i2s-controller : The phandle of the Tegra I2S controller that's
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connected to the CODEC.
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@ -5,8 +5,8 @@ system.
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dlmfs is built with OCFS2 as it requires most of its infrastructure.
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Project web page: http://oss.oracle.com/projects/ocfs2
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Tools web page: http://oss.oracle.com/projects/ocfs2-tools
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Project web page: http://ocfs2.wiki.kernel.org
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Tools web page: https://github.com/markfasheh/ocfs2-tools
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OCFS2 mailing lists: http://oss.oracle.com/projects/ocfs2/mailman/
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All code copyright 2005 Oracle except when otherwise noted.
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|
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@ -8,8 +8,8 @@ also make it attractive for non-clustered use.
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You'll want to install the ocfs2-tools package in order to at least
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get "mount.ocfs2" and "ocfs2_hb_ctl".
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Project web page: http://oss.oracle.com/projects/ocfs2
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Tools web page: http://oss.oracle.com/projects/ocfs2-tools
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Project web page: http://ocfs2.wiki.kernel.org
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Tools git tree: https://github.com/markfasheh/ocfs2-tools
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OCFS2 mailing lists: http://oss.oracle.com/projects/ocfs2/mailman/
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All code copyright 2005 Oracle except when otherwise noted.
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@ -7213,8 +7213,7 @@ ORACLE CLUSTER FILESYSTEM 2 (OCFS2)
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M: Mark Fasheh <mfasheh@suse.com>
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M: Joel Becker <jlbec@evilplan.org>
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L: ocfs2-devel@oss.oracle.com (moderated for non-subscribers)
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W: http://oss.oracle.com/projects/ocfs2/
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/jlbec/ocfs2.git
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W: http://ocfs2.wiki.kernel.org
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S: Supported
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F: Documentation/filesystems/ocfs2.txt
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F: Documentation/filesystems/dlmfs.txt
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2
Makefile
2
Makefile
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@ -1,7 +1,7 @@
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VERSION = 4
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PATCHLEVEL = 0
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SUBLEVEL = 0
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EXTRAVERSION = -rc1
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EXTRAVERSION = -rc2
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NAME = Hurr durr I'ma sheep
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# *DOCUMENTATION*
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|
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@ -195,6 +195,7 @@
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&usb0 {
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status = "okay";
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dr_mode = "peripheral";
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};
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&usb1 {
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@ -133,20 +133,6 @@
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>;
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};
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i2c1_pins_default: i2c1_pins_default {
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pinctrl-single,pins = <
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0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
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0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
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>;
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};
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|
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i2c1_pins_sleep: i2c1_pins_sleep {
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pinctrl-single,pins = <
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0x15c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_cs0.i2c1_scl */
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0x158 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d1.i2c1_sda */
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>;
|
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};
|
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|
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mmc1_pins_default: pinmux_mmc1_pins_default {
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pinctrl-single,pins = <
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0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
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|
@ -254,7 +240,7 @@
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status = "okay";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&i2c0_pins_default>;
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pinctrl-1 = <&i2c0_pins_default>;
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pinctrl-1 = <&i2c0_pins_sleep>;
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clock-frequency = <400000>;
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|
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at24@50 {
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|
@ -262,17 +248,10 @@
|
|||
pagesize = <64>;
|
||||
reg = <0x50>;
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||||
};
|
||||
};
|
||||
|
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&i2c1 {
|
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status = "okay";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&i2c1_pins_default>;
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pinctrl-1 = <&i2c1_pins_default>;
|
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clock-frequency = <400000>;
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|
||||
tps: tps62362@60 {
|
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compatible = "ti,tps62362";
|
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reg = <0x60>;
|
||||
regulator-name = "VDD_MPU";
|
||||
regulator-min-microvolt = <950000>;
|
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regulator-max-microvolt = <1330000>;
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|
|
|
@ -549,14 +549,6 @@
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pinctrl-0 = <&usb1_pins>;
|
||||
};
|
||||
|
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&omap_dwc3_1 {
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extcon = <&extcon_usb1>;
|
||||
};
|
||||
|
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&omap_dwc3_2 {
|
||||
extcon = <&extcon_usb2>;
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
|
|
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@ -35,6 +35,18 @@
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DM816X_IOPAD(0x0aac, PIN_INPUT | MUX_MODE0) /* SPI_D1 */
|
||||
>;
|
||||
};
|
||||
|
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usb0_pins: pinmux_usb0_pins {
|
||||
pinctrl-single,pins = <
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DM816X_IOPAD(0x0d00, MUX_MODE0) /* USB0_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
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usb1_pins: pinmux_usb0_pins {
|
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pinctrl-single,pins = <
|
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DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB1_DRVVBUS */
|
||||
>;
|
||||
};
|
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};
|
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|
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&i2c1 {
|
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|
@ -127,3 +139,16 @@
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&mmc1 {
|
||||
vmmc-supply = <&vmmcsd_fixed>;
|
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};
|
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|
||||
/* At least dm8168-evm rev c won't support multipoint, later may */
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&usb0 {
|
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pinctrl-names = "default";
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pinctrl-0 = <&usb0_pins>;
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mentor,multipoint = <0>;
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};
|
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|
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&usb1 {
|
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pinctrl-names = "default";
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pinctrl-0 = <&usb1_pins>;
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mentor,multipoint = <0>;
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||||
};
|
||||
|
|
|
@ -97,10 +97,31 @@
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|||
|
||||
/* Device Configuration Registers */
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scm_conf: syscon@600 {
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compatible = "syscon";
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compatible = "syscon", "simple-bus";
|
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reg = <0x600 0x110>;
|
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#address-cells = <1>;
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#size-cells = <1>;
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||||
ranges = <0 0x600 0x110>;
|
||||
|
||||
usb_phy0: usb-phy@20 {
|
||||
compatible = "ti,dm8168-usb-phy";
|
||||
reg = <0x20 0x8>;
|
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reg-names = "phy";
|
||||
clocks = <&main_fapll 6>;
|
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clock-names = "refclk";
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#phy-cells = <0>;
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syscon = <&scm_conf>;
|
||||
};
|
||||
|
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usb_phy1: usb-phy@28 {
|
||||
compatible = "ti,dm8168-usb-phy";
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reg = <0x28 0x8>;
|
||||
reg-names = "phy";
|
||||
clocks = <&main_fapll 6>;
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clock-names = "refclk";
|
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#phy-cells = <0>;
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syscon = <&scm_conf>;
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};
|
||||
};
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scrm_clocks: clocks {
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|
@ -357,7 +378,10 @@
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reg-names = "mc", "control";
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interrupts = <18>;
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interrupt-names = "mc";
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dr_mode = "otg";
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dr_mode = "host";
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interface-type = <0>;
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phys = <&usb_phy0>;
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phy-names = "usb2-phy";
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mentor,multipoint = <1>;
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mentor,num-eps = <16>;
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mentor,ram-bits = <12>;
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|
@ -366,13 +390,15 @@
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|||
|
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usb1: usb@47401800 {
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compatible = "ti,musb-am33xx";
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status = "disabled";
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reg = <0x47401c00 0x400
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0x47401800 0x200>;
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reg-names = "mc", "control";
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interrupts = <19>;
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interrupt-names = "mc";
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dr_mode = "otg";
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dr_mode = "host";
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interface-type = <0>;
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phys = <&usb_phy1>;
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phy-names = "usb2-phy";
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mentor,multipoint = <1>;
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mentor,num-eps = <16>;
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mentor,ram-bits = <12>;
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|
|
|
@ -543,14 +543,6 @@
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|||
};
|
||||
};
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||||
|
||||
&omap_dwc3_1 {
|
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extcon = <&extcon_usb1>;
|
||||
};
|
||||
|
||||
&omap_dwc3_2 {
|
||||
extcon = <&extcon_usb2>;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "peripheral";
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||||
pinctrl-names = "default";
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||||
|
|
|
@ -249,8 +249,8 @@
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|||
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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||||
#dma-cells = <1>;
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#dma-channels = <32>;
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||||
#dma-requests = <127>;
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||||
dma-channels = <32>;
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||||
dma-requests = <127>;
|
||||
};
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||||
|
||||
gpio1: gpio@4ae10000 {
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||||
|
@ -1090,8 +1090,8 @@
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|||
<0x4A096800 0x40>; /* pll_ctrl */
|
||||
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
|
||||
ctrl-module = <&omap_control_sata>;
|
||||
clocks = <&sys_clkin1>;
|
||||
clock-names = "sysclk";
|
||||
clocks = <&sys_clkin1>, <&sata_ref_clk>;
|
||||
clock-names = "sysclk", "refclk";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
|
|
|
@ -380,14 +380,6 @@
|
|||
phy-supply = <&ldo4_reg>;
|
||||
};
|
||||
|
||||
&omap_dwc3_1 {
|
||||
extcon = <&extcon_usb1>;
|
||||
};
|
||||
|
||||
&omap_dwc3_2 {
|
||||
extcon = <&extcon_usb2>;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "peripheral";
|
||||
pinctrl-names = "default";
|
||||
|
|
|
@ -87,8 +87,8 @@
|
|||
<14>,
|
||||
<15>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <32>;
|
||||
#dma-requests = <64>;
|
||||
dma-channels = <32>;
|
||||
dma-requests = <64>;
|
||||
};
|
||||
|
||||
i2c1: i2c@48070000 {
|
||||
|
|
|
@ -16,6 +16,13 @@
|
|||
model = "Nokia N900";
|
||||
compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3";
|
||||
|
||||
aliases {
|
||||
i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
cpu0-supply = <&vcc>;
|
||||
|
@ -704,7 +711,7 @@
|
|||
compatible = "smsc,lan91c94";
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
|
||||
reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */
|
||||
reg = <1 0 0xf>; /* 16 byte IO range */
|
||||
bank-width = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <ðernet_pins>;
|
||||
|
|
|
@ -155,8 +155,8 @@
|
|||
<14>,
|
||||
<15>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <32>;
|
||||
#dma-requests = <96>;
|
||||
dma-channels = <32>;
|
||||
dma-requests = <96>;
|
||||
};
|
||||
|
||||
omap3_pmx_core: pinmux@48002030 {
|
||||
|
|
|
@ -223,8 +223,8 @@
|
|||
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <32>;
|
||||
#dma-requests = <127>;
|
||||
dma-channels = <32>;
|
||||
dma-requests = <127>;
|
||||
};
|
||||
|
||||
gpio1: gpio@4a310000 {
|
||||
|
|
|
@ -238,8 +238,8 @@
|
|||
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <32>;
|
||||
#dma-requests = <127>;
|
||||
dma-channels = <32>;
|
||||
dma-requests = <127>;
|
||||
};
|
||||
|
||||
gpio1: gpio@4ae10000 {
|
||||
|
@ -929,8 +929,8 @@
|
|||
<0x4A096800 0x40>; /* pll_ctrl */
|
||||
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
|
||||
ctrl-module = <&omap_control_sata>;
|
||||
clocks = <&sys_clkin>;
|
||||
clock-names = "sysclk";
|
||||
clocks = <&sys_clkin>, <&sata_ref_clk>;
|
||||
clock-names = "sysclk", "refclk";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -62,6 +62,17 @@ CONFIG_MACH_SPEAR1340=y
|
|||
CONFIG_ARCH_STI=y
|
||||
CONFIG_ARCH_EXYNOS=y
|
||||
CONFIG_EXYNOS5420_MCPM=y
|
||||
CONFIG_ARCH_SHMOBILE_MULTI=y
|
||||
CONFIG_ARCH_EMEV2=y
|
||||
CONFIG_ARCH_R7S72100=y
|
||||
CONFIG_ARCH_R8A73A4=y
|
||||
CONFIG_ARCH_R8A7740=y
|
||||
CONFIG_ARCH_R8A7779=y
|
||||
CONFIG_ARCH_R8A7790=y
|
||||
CONFIG_ARCH_R8A7791=y
|
||||
CONFIG_ARCH_R8A7794=y
|
||||
CONFIG_ARCH_SH73A0=y
|
||||
CONFIG_MACH_MARZEN=y
|
||||
CONFIG_ARCH_SUNXI=y
|
||||
CONFIG_ARCH_SIRF=y
|
||||
CONFIG_ARCH_TEGRA=y
|
||||
|
@ -84,6 +95,8 @@ CONFIG_PCI_KEYSTONE=y
|
|||
CONFIG_PCI_MSI=y
|
||||
CONFIG_PCI_MVEBU=y
|
||||
CONFIG_PCI_TEGRA=y
|
||||
CONFIG_PCI_RCAR_GEN2=y
|
||||
CONFIG_PCI_RCAR_GEN2_PCIE=y
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_NR_CPUS=8
|
||||
|
@ -130,6 +143,7 @@ CONFIG_DEVTMPFS_MOUNT=y
|
|||
CONFIG_DMA_CMA=y
|
||||
CONFIG_CMA_SIZE_MBYTES=64
|
||||
CONFIG_OMAP_OCP2SCP=y
|
||||
CONFIG_SIMPLE_PM_BUS=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
|
@ -157,6 +171,7 @@ CONFIG_AHCI_SUNXI=y
|
|||
CONFIG_AHCI_TEGRA=y
|
||||
CONFIG_SATA_HIGHBANK=y
|
||||
CONFIG_SATA_MV=y
|
||||
CONFIG_SATA_RCAR=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_HIX5HD2_GMAC=y
|
||||
CONFIG_SUN4I_EMAC=y
|
||||
|
@ -167,14 +182,17 @@ CONFIG_MV643XX_ETH=y
|
|||
CONFIG_MVNETA=y
|
||||
CONFIG_KS8851=y
|
||||
CONFIG_R8169=y
|
||||
CONFIG_SH_ETH=y
|
||||
CONFIG_SMSC911X=y
|
||||
CONFIG_STMMAC_ETH=y
|
||||
CONFIG_TI_CPSW=y
|
||||
CONFIG_XILINX_EMACLITE=y
|
||||
CONFIG_AT803X_PHY=y
|
||||
CONFIG_MARVELL_PHY=y
|
||||
CONFIG_SMSC_PHY=y
|
||||
CONFIG_BROADCOM_PHY=y
|
||||
CONFIG_ICPLUS_PHY=y
|
||||
CONFIG_MICREL_PHY=y
|
||||
CONFIG_USB_PEGASUS=y
|
||||
CONFIG_USB_USBNET=y
|
||||
CONFIG_USB_NET_SMSC75XX=y
|
||||
|
@ -192,15 +210,18 @@ CONFIG_KEYBOARD_CROS_EC=y
|
|||
CONFIG_MOUSE_PS2_ELANTECH=y
|
||||
CONFIG_INPUT_TOUCHSCREEN=y
|
||||
CONFIG_TOUCHSCREEN_ATMEL_MXT=y
|
||||
CONFIG_TOUCHSCREEN_ST1232=m
|
||||
CONFIG_TOUCHSCREEN_STMPE=y
|
||||
CONFIG_TOUCHSCREEN_SUN4I=y
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_MPU3050=y
|
||||
CONFIG_INPUT_AXP20X_PEK=y
|
||||
CONFIG_INPUT_ADXL34X=m
|
||||
CONFIG_SERIO_AMBAKMI=y
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_SERIAL_8250_EM=y
|
||||
CONFIG_SERIAL_8250_MT6577=y
|
||||
CONFIG_SERIAL_AMBA_PL011=y
|
||||
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
||||
|
@ -213,6 +234,9 @@ CONFIG_SERIAL_SIRFSOC_CONSOLE=y
|
|||
CONFIG_SERIAL_TEGRA=y
|
||||
CONFIG_SERIAL_IMX=y
|
||||
CONFIG_SERIAL_IMX_CONSOLE=y
|
||||
CONFIG_SERIAL_SH_SCI=y
|
||||
CONFIG_SERIAL_SH_SCI_NR_UARTS=20
|
||||
CONFIG_SERIAL_SH_SCI_CONSOLE=y
|
||||
CONFIG_SERIAL_MSM=y
|
||||
CONFIG_SERIAL_MSM_CONSOLE=y
|
||||
CONFIG_SERIAL_VT8500=y
|
||||
|
@ -233,19 +257,26 @@ CONFIG_I2C_MUX_PCA954x=y
|
|||
CONFIG_I2C_MUX_PINCTRL=y
|
||||
CONFIG_I2C_CADENCE=y
|
||||
CONFIG_I2C_DESIGNWARE_PLATFORM=y
|
||||
CONFIG_I2C_GPIO=m
|
||||
CONFIG_I2C_EXYNOS5=y
|
||||
CONFIG_I2C_MV64XXX=y
|
||||
CONFIG_I2C_RIIC=y
|
||||
CONFIG_I2C_S3C2410=y
|
||||
CONFIG_I2C_SH_MOBILE=y
|
||||
CONFIG_I2C_SIRF=y
|
||||
CONFIG_I2C_TEGRA=y
|
||||
CONFIG_I2C_ST=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_I2C_TEGRA=y
|
||||
CONFIG_I2C_XILINX=y
|
||||
CONFIG_SPI_DAVINCI=y
|
||||
CONFIG_I2C_RCAR=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_CADENCE=y
|
||||
CONFIG_SPI_DAVINCI=y
|
||||
CONFIG_SPI_OMAP24XX=y
|
||||
CONFIG_SPI_ORION=y
|
||||
CONFIG_SPI_PL022=y
|
||||
CONFIG_SPI_RSPI=y
|
||||
CONFIG_SPI_SH_MSIOF=m
|
||||
CONFIG_SPI_SH_HSPI=y
|
||||
CONFIG_SPI_SIRF=y
|
||||
CONFIG_SPI_SUN4I=y
|
||||
CONFIG_SPI_SUN6I=y
|
||||
|
@ -259,12 +290,15 @@ CONFIG_PINCTRL_PALMAS=y
|
|||
CONFIG_PINCTRL_APQ8084=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_GENERIC_PLATFORM=y
|
||||
CONFIG_GPIO_DWAPB=y
|
||||
CONFIG_GPIO_DAVINCI=y
|
||||
CONFIG_GPIO_DWAPB=y
|
||||
CONFIG_GPIO_EM=y
|
||||
CONFIG_GPIO_RCAR=y
|
||||
CONFIG_GPIO_XILINX=y
|
||||
CONFIG_GPIO_ZYNQ=y
|
||||
CONFIG_GPIO_PCA953X=y
|
||||
CONFIG_GPIO_PCA953X_IRQ=y
|
||||
CONFIG_GPIO_PCF857X=y
|
||||
CONFIG_GPIO_TWL4030=y
|
||||
CONFIG_GPIO_PALMAS=y
|
||||
CONFIG_GPIO_SYSCON=y
|
||||
|
@ -276,10 +310,12 @@ CONFIG_POWER_RESET_AS3722=y
|
|||
CONFIG_POWER_RESET_GPIO=y
|
||||
CONFIG_POWER_RESET_KEYSTONE=y
|
||||
CONFIG_POWER_RESET_SUN6I=y
|
||||
CONFIG_POWER_RESET_RMOBILE=y
|
||||
CONFIG_SENSORS_LM90=y
|
||||
CONFIG_SENSORS_LM95245=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_CPU_THERMAL=y
|
||||
CONFIG_RCAR_THERMAL=y
|
||||
CONFIG_ARMADA_THERMAL=y
|
||||
CONFIG_DAVINCI_WATCHDOG
|
||||
CONFIG_ST_THERMAL_SYSCFG=y
|
||||
|
@ -290,6 +326,7 @@ CONFIG_ARM_SP805_WATCHDOG=y
|
|||
CONFIG_ORION_WATCHDOG=y
|
||||
CONFIG_SUNXI_WATCHDOG=y
|
||||
CONFIG_MESON_WATCHDOG=y
|
||||
CONFIG_MFD_AS3711=y
|
||||
CONFIG_MFD_AS3722=y
|
||||
CONFIG_MFD_BCM590XX=y
|
||||
CONFIG_MFD_AXP20X=y
|
||||
|
@ -304,13 +341,16 @@ CONFIG_MFD_TPS65090=y
|
|||
CONFIG_MFD_TPS6586X=y
|
||||
CONFIG_MFD_TPS65910=y
|
||||
CONFIG_REGULATOR_AB8500=y
|
||||
CONFIG_REGULATOR_AS3711=y
|
||||
CONFIG_REGULATOR_AS3722=y
|
||||
CONFIG_REGULATOR_AXP20X=y
|
||||
CONFIG_REGULATOR_BCM590XX=y
|
||||
CONFIG_REGULATOR_DA9210=y
|
||||
CONFIG_REGULATOR_GPIO=y
|
||||
CONFIG_MFD_SYSCON=y
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
CONFIG_REGULATOR_MAX8907=y
|
||||
CONFIG_REGULATOR_MAX8973=y
|
||||
CONFIG_REGULATOR_MAX77686=y
|
||||
CONFIG_REGULATOR_PALMAS=y
|
||||
CONFIG_REGULATOR_S2MPS11=y
|
||||
|
@ -324,18 +364,32 @@ CONFIG_REGULATOR_TWL4030=y
|
|||
CONFIG_REGULATOR_VEXPRESS=y
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
CONFIG_MEDIA_CAMERA_SUPPORT=y
|
||||
CONFIG_MEDIA_CONTROLLER=y
|
||||
CONFIG_VIDEO_V4L2_SUBDEV_API=y
|
||||
CONFIG_MEDIA_USB_SUPPORT=y
|
||||
CONFIG_USB_VIDEO_CLASS=y
|
||||
CONFIG_USB_GSPCA=y
|
||||
CONFIG_V4L_PLATFORM_DRIVERS=y
|
||||
CONFIG_SOC_CAMERA=m
|
||||
CONFIG_SOC_CAMERA_PLATFORM=m
|
||||
CONFIG_VIDEO_RCAR_VIN=m
|
||||
CONFIG_V4L_MEM2MEM_DRIVERS=y
|
||||
CONFIG_VIDEO_RENESAS_VSP1=m
|
||||
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
|
||||
CONFIG_VIDEO_ADV7180=m
|
||||
CONFIG_DRM=y
|
||||
CONFIG_DRM_RCAR_DU=m
|
||||
CONFIG_DRM_TEGRA=y
|
||||
CONFIG_DRM_PANEL_SIMPLE=y
|
||||
CONFIG_FB_ARMCLCD=y
|
||||
CONFIG_FB_WM8505=y
|
||||
CONFIG_FB_SH_MOBILE_LCDC=y
|
||||
CONFIG_FB_SIMPLE=y
|
||||
CONFIG_FB_SH_MOBILE_MERAM=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
CONFIG_BACKLIGHT_PWM=y
|
||||
CONFIG_BACKLIGHT_AS3711=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
|
||||
CONFIG_SOUND=y
|
||||
|
@ -343,6 +397,8 @@ CONFIG_SND=y
|
|||
CONFIG_SND_DYNAMIC_MINORS=y
|
||||
CONFIG_SND_USB_AUDIO=y
|
||||
CONFIG_SND_SOC=y
|
||||
CONFIG_SND_SOC_SH4_FSI=m
|
||||
CONFIG_SND_SOC_RCAR=m
|
||||
CONFIG_SND_SOC_TEGRA=y
|
||||
CONFIG_SND_SOC_TEGRA_RT5640=y
|
||||
CONFIG_SND_SOC_TEGRA_WM8753=y
|
||||
|
@ -350,6 +406,8 @@ CONFIG_SND_SOC_TEGRA_WM8903=y
|
|||
CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
|
||||
CONFIG_SND_SOC_TEGRA_ALC5632=y
|
||||
CONFIG_SND_SOC_TEGRA_MAX98090=y
|
||||
CONFIG_SND_SOC_AK4642=m
|
||||
CONFIG_SND_SOC_WM8978=m
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_MVEBU=y
|
||||
|
@ -362,6 +420,8 @@ CONFIG_USB_ISP1760_HCD=y
|
|||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD_STI=y
|
||||
CONFIG_USB_OHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_R8A66597_HCD=m
|
||||
CONFIG_USB_RENESAS_USBHS=m
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_CHIPIDEA=y
|
||||
|
@ -374,6 +434,10 @@ CONFIG_SAMSUNG_USB3PHY=y
|
|||
CONFIG_USB_GPIO_VBUS=y
|
||||
CONFIG_USB_ISP1301=y
|
||||
CONFIG_USB_MXS_PHY=y
|
||||
CONFIG_USB_RCAR_PHY=m
|
||||
CONFIG_USB_RCAR_GEN2_PHY=m
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_RENESAS_USBHS_UDC=m
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK_MINORS=16
|
||||
CONFIG_MMC_ARMMMCI=y
|
||||
|
@ -392,12 +456,14 @@ CONFIG_MMC_SDHCI_ST=y
|
|||
CONFIG_MMC_OMAP=y
|
||||
CONFIG_MMC_OMAP_HS=y
|
||||
CONFIG_MMC_MVSDIO=y
|
||||
CONFIG_MMC_SUNXI=y
|
||||
CONFIG_MMC_SDHI=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_IDMAC=y
|
||||
CONFIG_MMC_DW_PLTFM=y
|
||||
CONFIG_MMC_DW_EXYNOS=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SH_MMCIF=y
|
||||
CONFIG_MMC_SUNXI=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_GPIO=y
|
||||
|
@ -421,10 +487,12 @@ CONFIG_RTC_DRV_AS3722=y
|
|||
CONFIG_RTC_DRV_DS1307=y
|
||||
CONFIG_RTC_DRV_MAX8907=y
|
||||
CONFIG_RTC_DRV_MAX77686=y
|
||||
CONFIG_RTC_DRV_RS5C372=m
|
||||
CONFIG_RTC_DRV_PALMAS=y
|
||||
CONFIG_RTC_DRV_TWL4030=y
|
||||
CONFIG_RTC_DRV_TPS6586X=y
|
||||
CONFIG_RTC_DRV_TPS65910=y
|
||||
CONFIG_RTC_DRV_S35390A=m
|
||||
CONFIG_RTC_DRV_EM3027=y
|
||||
CONFIG_RTC_DRV_PL031=y
|
||||
CONFIG_RTC_DRV_VT8500=y
|
||||
|
@ -436,6 +504,9 @@ CONFIG_DMADEVICES=y
|
|||
CONFIG_DW_DMAC=y
|
||||
CONFIG_MV_XOR=y
|
||||
CONFIG_TEGRA20_APB_DMA=y
|
||||
CONFIG_SH_DMAE=y
|
||||
CONFIG_RCAR_AUDMAC_PP=m
|
||||
CONFIG_RCAR_DMAC=y
|
||||
CONFIG_STE_DMA40=y
|
||||
CONFIG_SIRF_DMA=y
|
||||
CONFIG_TI_EDMA=y
|
||||
|
@ -468,6 +539,7 @@ CONFIG_IIO=y
|
|||
CONFIG_XILINX_XADC=y
|
||||
CONFIG_AK8975=y
|
||||
CONFIG_PWM=y
|
||||
CONFIG_PWM_RENESAS_TPU=y
|
||||
CONFIG_PWM_TEGRA=y
|
||||
CONFIG_PWM_VT8500=y
|
||||
CONFIG_PHY_HIX5HD2_SATA=y
|
||||
|
|
|
@ -114,6 +114,7 @@ CONFIG_MTD_PHYSMAP_OF=y
|
|||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_ECC_BCH=y
|
||||
CONFIG_MTD_NAND_OMAP2=y
|
||||
CONFIG_MTD_NAND_OMAP_BCH=y
|
||||
CONFIG_MTD_ONENAND=y
|
||||
CONFIG_MTD_ONENAND_VERIFY_WRITE=y
|
||||
CONFIG_MTD_ONENAND_OMAP2=y
|
||||
|
@ -248,6 +249,7 @@ CONFIG_TWL6040_CORE=y
|
|||
CONFIG_REGULATOR_PALMAS=y
|
||||
CONFIG_REGULATOR_PBIAS=y
|
||||
CONFIG_REGULATOR_TI_ABB=y
|
||||
CONFIG_REGULATOR_TPS62360=m
|
||||
CONFIG_REGULATOR_TPS65023=y
|
||||
CONFIG_REGULATOR_TPS6507X=y
|
||||
CONFIG_REGULATOR_TPS65217=y
|
||||
|
@ -374,7 +376,7 @@ CONFIG_PWM_TIEHRPWM=m
|
|||
CONFIG_PWM_TWL=m
|
||||
CONFIG_PWM_TWL_LED=m
|
||||
CONFIG_OMAP_USB2=m
|
||||
CONFIG_TI_PIPE3=m
|
||||
CONFIG_TI_PIPE3=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_FS_XATTR is not set
|
||||
|
|
|
@ -2,5 +2,7 @@ config MACH_ASM9260
|
|||
bool "Alphascale ASM9260"
|
||||
depends on ARCH_MULTI_V5
|
||||
select CPU_ARM926T
|
||||
select ASM9260_TIMER
|
||||
select GENERIC_CLOCKEVENTS
|
||||
help
|
||||
Support for Alphascale ASM9260 based platform.
|
||||
|
|
|
@ -34,6 +34,7 @@
|
|||
reg = <0x0 0x0>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x8000fff8>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
|
@ -41,6 +42,7 @@
|
|||
reg = <0x0 0x1>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x8000fff8>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
|
@ -48,6 +50,7 @@
|
|||
reg = <0x0 0x2>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x8000fff8>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
|
@ -55,6 +58,11 @@
|
|||
reg = <0x0 0x3>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x8000fff8>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -39,6 +39,7 @@
|
|||
reg = <0x0 0x0>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A57_L2>;
|
||||
};
|
||||
|
||||
A57_1: cpu@1 {
|
||||
|
@ -46,6 +47,7 @@
|
|||
reg = <0x0 0x1>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A57_L2>;
|
||||
};
|
||||
|
||||
A53_0: cpu@100 {
|
||||
|
@ -53,6 +55,7 @@
|
|||
reg = <0x0 0x100>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
};
|
||||
|
||||
A53_1: cpu@101 {
|
||||
|
@ -60,6 +63,7 @@
|
|||
reg = <0x0 0x101>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
};
|
||||
|
||||
A53_2: cpu@102 {
|
||||
|
@ -67,6 +71,7 @@
|
|||
reg = <0x0 0x102>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
};
|
||||
|
||||
A53_3: cpu@103 {
|
||||
|
@ -74,6 +79,15 @@
|
|||
reg = <0x0 0x103>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
};
|
||||
|
||||
A57_L2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
|
||||
A53_L2: l2-cache1 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -37,6 +37,7 @@
|
|||
reg = <0x0 0x0>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x8000fff8>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
|
@ -44,6 +45,7 @@
|
|||
reg = <0x0 0x1>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x8000fff8>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
|
@ -51,6 +53,7 @@
|
|||
reg = <0x0 0x2>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x8000fff8>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
|
@ -58,6 +61,11 @@
|
|||
reg = <0x0 0x3>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x8000fff8>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -29,7 +29,7 @@ aes-ce-blk-y := aes-glue-ce.o aes-ce.o
|
|||
obj-$(CONFIG_CRYPTO_AES_ARM64_NEON_BLK) += aes-neon-blk.o
|
||||
aes-neon-blk-y := aes-glue-neon.o aes-neon.o
|
||||
|
||||
AFLAGS_aes-ce.o := -DINTERLEAVE=2 -DINTERLEAVE_INLINE
|
||||
AFLAGS_aes-ce.o := -DINTERLEAVE=4
|
||||
AFLAGS_aes-neon.o := -DINTERLEAVE=4
|
||||
|
||||
CFLAGS_aes-glue-ce.o := -DUSE_V8_CRYPTO_EXTENSIONS
|
||||
|
|
|
@ -20,6 +20,9 @@
|
|||
#error "Only include this from assembly code"
|
||||
#endif
|
||||
|
||||
#ifndef __ASM_ASSEMBLER_H
|
||||
#define __ASM_ASSEMBLER_H
|
||||
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/thread_info.h>
|
||||
|
||||
|
@ -155,3 +158,5 @@ lr .req x30 // link register
|
|||
#endif
|
||||
orr \rd, \lbits, \hbits, lsl #32
|
||||
.endm
|
||||
|
||||
#endif /* __ASM_ASSEMBLER_H */
|
||||
|
|
|
@ -1,6 +1,8 @@
|
|||
#ifndef __ASM_CPUIDLE_H
|
||||
#define __ASM_CPUIDLE_H
|
||||
|
||||
#include <asm/proc-fns.h>
|
||||
|
||||
#ifdef CONFIG_CPU_IDLE
|
||||
extern int cpu_init_idle(unsigned int cpu);
|
||||
extern int cpu_suspend(unsigned long arg);
|
||||
|
|
|
@ -264,8 +264,10 @@ __AARCH64_INSN_FUNCS(ands, 0x7F200000, 0x6A000000)
|
|||
__AARCH64_INSN_FUNCS(bics, 0x7F200000, 0x6A200000)
|
||||
__AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000)
|
||||
__AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000)
|
||||
__AARCH64_INSN_FUNCS(cbz, 0xFE000000, 0x34000000)
|
||||
__AARCH64_INSN_FUNCS(cbnz, 0xFE000000, 0x35000000)
|
||||
__AARCH64_INSN_FUNCS(cbz, 0x7F000000, 0x34000000)
|
||||
__AARCH64_INSN_FUNCS(cbnz, 0x7F000000, 0x35000000)
|
||||
__AARCH64_INSN_FUNCS(tbz, 0x7F000000, 0x36000000)
|
||||
__AARCH64_INSN_FUNCS(tbnz, 0x7F000000, 0x37000000)
|
||||
__AARCH64_INSN_FUNCS(bcond, 0xFF000010, 0x54000000)
|
||||
__AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001)
|
||||
__AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002)
|
||||
|
|
|
@ -460,7 +460,7 @@ static inline pud_t *pud_offset(pgd_t *pgd, unsigned long addr)
|
|||
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
|
||||
{
|
||||
const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
|
||||
PTE_PROT_NONE | PTE_VALID | PTE_WRITE;
|
||||
PTE_PROT_NONE | PTE_WRITE | PTE_TYPE_MASK;
|
||||
pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
|
||||
return pte;
|
||||
}
|
||||
|
|
|
@ -45,7 +45,8 @@
|
|||
#define STACK_TOP STACK_TOP_MAX
|
||||
#endif /* CONFIG_COMPAT */
|
||||
|
||||
#define ARCH_LOW_ADDRESS_LIMIT PHYS_MASK
|
||||
extern phys_addr_t arm64_dma_phys_limit;
|
||||
#define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
struct debug_info {
|
||||
|
|
|
@ -24,11 +24,6 @@
|
|||
#include <linux/sched.h>
|
||||
#include <asm/cputype.h>
|
||||
|
||||
extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
|
||||
extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
|
||||
|
||||
extern struct cpu_tlb_fns cpu_tlb;
|
||||
|
||||
/*
|
||||
* TLB Management
|
||||
* ==============
|
||||
|
|
|
@ -15,8 +15,9 @@ CFLAGS_REMOVE_return_address.o = -pg
|
|||
arm64-obj-y := cputable.o debug-monitors.o entry.o irq.o fpsimd.o \
|
||||
entry-fpsimd.o process.o ptrace.o setup.o signal.o \
|
||||
sys.o stacktrace.o time.o traps.o io.o vdso.o \
|
||||
hyp-stub.o psci.o cpu_ops.o insn.o return_address.o \
|
||||
cpuinfo.o cpu_errata.o alternative.o cacheinfo.o
|
||||
hyp-stub.o psci.o psci-call.o cpu_ops.o insn.o \
|
||||
return_address.o cpuinfo.o cpu_errata.o \
|
||||
alternative.o cacheinfo.o
|
||||
|
||||
arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \
|
||||
sys_compat.o entry32.o \
|
||||
|
|
|
@ -156,7 +156,7 @@ static int ftrace_modify_graph_caller(bool enable)
|
|||
|
||||
branch = aarch64_insn_gen_branch_imm(pc,
|
||||
(unsigned long)ftrace_graph_caller,
|
||||
AARCH64_INSN_BRANCH_LINK);
|
||||
AARCH64_INSN_BRANCH_NOLINK);
|
||||
nop = aarch64_insn_gen_nop();
|
||||
|
||||
if (enable)
|
||||
|
|
|
@ -87,8 +87,10 @@ static void __kprobes *patch_map(void *addr, int fixmap)
|
|||
|
||||
if (module && IS_ENABLED(CONFIG_DEBUG_SET_MODULE_RONX))
|
||||
page = vmalloc_to_page(addr);
|
||||
else
|
||||
else if (!module && IS_ENABLED(CONFIG_DEBUG_RODATA))
|
||||
page = virt_to_page(addr);
|
||||
else
|
||||
return addr;
|
||||
|
||||
BUG_ON(!page);
|
||||
set_fixmap(fixmap, page_to_phys(page));
|
||||
|
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Copyright (C) 2015 ARM Limited
|
||||
*
|
||||
* Author: Will Deacon <will.deacon@arm.com>
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
|
||||
/* int __invoke_psci_fn_hvc(u64 function_id, u64 arg0, u64 arg1, u64 arg2) */
|
||||
ENTRY(__invoke_psci_fn_hvc)
|
||||
hvc #0
|
||||
ret
|
||||
ENDPROC(__invoke_psci_fn_hvc)
|
||||
|
||||
/* int __invoke_psci_fn_smc(u64 function_id, u64 arg0, u64 arg1, u64 arg2) */
|
||||
ENTRY(__invoke_psci_fn_smc)
|
||||
smc #0
|
||||
ret
|
||||
ENDPROC(__invoke_psci_fn_smc)
|
|
@ -57,6 +57,9 @@ static struct psci_operations psci_ops;
|
|||
static int (*invoke_psci_fn)(u64, u64, u64, u64);
|
||||
typedef int (*psci_initcall_t)(const struct device_node *);
|
||||
|
||||
asmlinkage int __invoke_psci_fn_hvc(u64, u64, u64, u64);
|
||||
asmlinkage int __invoke_psci_fn_smc(u64, u64, u64, u64);
|
||||
|
||||
enum psci_function {
|
||||
PSCI_FN_CPU_SUSPEND,
|
||||
PSCI_FN_CPU_ON,
|
||||
|
@ -109,40 +112,6 @@ static void psci_power_state_unpack(u32 power_state,
|
|||
PSCI_0_2_POWER_STATE_AFFL_SHIFT;
|
||||
}
|
||||
|
||||
/*
|
||||
* The following two functions are invoked via the invoke_psci_fn pointer
|
||||
* and will not be inlined, allowing us to piggyback on the AAPCS.
|
||||
*/
|
||||
static noinline int __invoke_psci_fn_hvc(u64 function_id, u64 arg0, u64 arg1,
|
||||
u64 arg2)
|
||||
{
|
||||
asm volatile(
|
||||
__asmeq("%0", "x0")
|
||||
__asmeq("%1", "x1")
|
||||
__asmeq("%2", "x2")
|
||||
__asmeq("%3", "x3")
|
||||
"hvc #0\n"
|
||||
: "+r" (function_id)
|
||||
: "r" (arg0), "r" (arg1), "r" (arg2));
|
||||
|
||||
return function_id;
|
||||
}
|
||||
|
||||
static noinline int __invoke_psci_fn_smc(u64 function_id, u64 arg0, u64 arg1,
|
||||
u64 arg2)
|
||||
{
|
||||
asm volatile(
|
||||
__asmeq("%0", "x0")
|
||||
__asmeq("%1", "x1")
|
||||
__asmeq("%2", "x2")
|
||||
__asmeq("%3", "x3")
|
||||
"smc #0\n"
|
||||
: "+r" (function_id)
|
||||
: "r" (arg0), "r" (arg1), "r" (arg2));
|
||||
|
||||
return function_id;
|
||||
}
|
||||
|
||||
static int psci_get_version(void)
|
||||
{
|
||||
int err;
|
||||
|
|
|
@ -154,8 +154,7 @@ int copy_siginfo_to_user32(compat_siginfo_t __user *to, const siginfo_t *from)
|
|||
case __SI_TIMER:
|
||||
err |= __put_user(from->si_tid, &to->si_tid);
|
||||
err |= __put_user(from->si_overrun, &to->si_overrun);
|
||||
err |= __put_user((compat_uptr_t)(unsigned long)from->si_ptr,
|
||||
&to->si_ptr);
|
||||
err |= __put_user(from->si_int, &to->si_int);
|
||||
break;
|
||||
case __SI_POLL:
|
||||
err |= __put_user(from->si_band, &to->si_band);
|
||||
|
@ -184,7 +183,7 @@ int copy_siginfo_to_user32(compat_siginfo_t __user *to, const siginfo_t *from)
|
|||
case __SI_MESGQ: /* But this is */
|
||||
err |= __put_user(from->si_pid, &to->si_pid);
|
||||
err |= __put_user(from->si_uid, &to->si_uid);
|
||||
err |= __put_user((compat_uptr_t)(unsigned long)from->si_ptr, &to->si_ptr);
|
||||
err |= __put_user(from->si_int, &to->si_int);
|
||||
break;
|
||||
case __SI_SYS:
|
||||
err |= __put_user((compat_uptr_t)(unsigned long)
|
||||
|
|
|
@ -174,8 +174,6 @@ ENDPROC(__kernel_clock_gettime)
|
|||
/* int __kernel_clock_getres(clockid_t clock_id, struct timespec *res); */
|
||||
ENTRY(__kernel_clock_getres)
|
||||
.cfi_startproc
|
||||
cbz w1, 3f
|
||||
|
||||
cmp w0, #CLOCK_REALTIME
|
||||
ccmp w0, #CLOCK_MONOTONIC, #0x4, ne
|
||||
b.ne 1f
|
||||
|
@ -188,6 +186,7 @@ ENTRY(__kernel_clock_getres)
|
|||
b.ne 4f
|
||||
ldr x2, 6f
|
||||
2:
|
||||
cbz w1, 3f
|
||||
stp xzr, x2, [x1]
|
||||
|
||||
3: /* res == NULL. */
|
||||
|
|
|
@ -348,8 +348,6 @@ static struct dma_map_ops swiotlb_dma_ops = {
|
|||
.mapping_error = swiotlb_dma_mapping_error,
|
||||
};
|
||||
|
||||
extern int swiotlb_late_init_with_default_size(size_t default_size);
|
||||
|
||||
static int __init atomic_pool_init(void)
|
||||
{
|
||||
pgprot_t prot = __pgprot(PROT_NORMAL_NC);
|
||||
|
@ -411,21 +409,13 @@ out:
|
|||
return -ENOMEM;
|
||||
}
|
||||
|
||||
static int __init swiotlb_late_init(void)
|
||||
static int __init arm64_dma_init(void)
|
||||
{
|
||||
size_t swiotlb_size = min(SZ_64M, MAX_ORDER_NR_PAGES << PAGE_SHIFT);
|
||||
int ret;
|
||||
|
||||
dma_ops = &swiotlb_dma_ops;
|
||||
|
||||
return swiotlb_late_init_with_default_size(swiotlb_size);
|
||||
}
|
||||
|
||||
static int __init arm64_dma_init(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
ret |= swiotlb_late_init();
|
||||
ret |= atomic_pool_init();
|
||||
ret = atomic_pool_init();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -33,6 +33,7 @@
|
|||
#include <linux/dma-mapping.h>
|
||||
#include <linux/dma-contiguous.h>
|
||||
#include <linux/efi.h>
|
||||
#include <linux/swiotlb.h>
|
||||
|
||||
#include <asm/fixmap.h>
|
||||
#include <asm/memory.h>
|
||||
|
@ -45,6 +46,7 @@
|
|||
#include "mm.h"
|
||||
|
||||
phys_addr_t memstart_addr __read_mostly = 0;
|
||||
phys_addr_t arm64_dma_phys_limit __read_mostly;
|
||||
|
||||
#ifdef CONFIG_BLK_DEV_INITRD
|
||||
static int __init early_initrd(char *p)
|
||||
|
@ -85,7 +87,7 @@ static void __init zone_sizes_init(unsigned long min, unsigned long max)
|
|||
|
||||
/* 4GB maximum for 32-bit only capable devices */
|
||||
if (IS_ENABLED(CONFIG_ZONE_DMA)) {
|
||||
max_dma = PFN_DOWN(max_zone_dma_phys());
|
||||
max_dma = PFN_DOWN(arm64_dma_phys_limit);
|
||||
zone_size[ZONE_DMA] = max_dma - min;
|
||||
}
|
||||
zone_size[ZONE_NORMAL] = max - max_dma;
|
||||
|
@ -156,8 +158,6 @@ early_param("mem", early_mem);
|
|||
|
||||
void __init arm64_memblock_init(void)
|
||||
{
|
||||
phys_addr_t dma_phys_limit = 0;
|
||||
|
||||
memblock_enforce_memory_limit(memory_limit);
|
||||
|
||||
/*
|
||||
|
@ -174,8 +174,10 @@ void __init arm64_memblock_init(void)
|
|||
|
||||
/* 4GB maximum for 32-bit only capable devices */
|
||||
if (IS_ENABLED(CONFIG_ZONE_DMA))
|
||||
dma_phys_limit = max_zone_dma_phys();
|
||||
dma_contiguous_reserve(dma_phys_limit);
|
||||
arm64_dma_phys_limit = max_zone_dma_phys();
|
||||
else
|
||||
arm64_dma_phys_limit = PHYS_MASK + 1;
|
||||
dma_contiguous_reserve(arm64_dma_phys_limit);
|
||||
|
||||
memblock_allow_resize();
|
||||
memblock_dump_all();
|
||||
|
@ -276,6 +278,8 @@ static void __init free_unused_memmap(void)
|
|||
*/
|
||||
void __init mem_init(void)
|
||||
{
|
||||
swiotlb_init(1);
|
||||
|
||||
set_max_mapnr(pfn_to_page(max_pfn) - mem_map);
|
||||
|
||||
#ifndef CONFIG_SPARSEMEM_VMEMMAP
|
||||
|
|
|
@ -123,12 +123,14 @@ extern unsigned long empty_zero_page;
|
|||
#define PGDIR_MASK (~(PGDIR_SIZE - 1))
|
||||
#define PTRS_PER_PGD 64
|
||||
|
||||
#define __PAGETABLE_PUD_FOLDED
|
||||
#define PUD_SHIFT 26
|
||||
#define PTRS_PER_PUD 1
|
||||
#define PUD_SIZE (1UL << PUD_SHIFT)
|
||||
#define PUD_MASK (~(PUD_SIZE - 1))
|
||||
#define PUE_SIZE 256
|
||||
|
||||
#define __PAGETABLE_PMD_FOLDED
|
||||
#define PMD_SHIFT 26
|
||||
#define PMD_SIZE (1UL << PMD_SHIFT)
|
||||
#define PMD_MASK (~(PMD_SIZE - 1))
|
||||
|
|
|
@ -13,6 +13,7 @@
|
|||
* the M32R is two-level, so we don't really have any
|
||||
* PMD directory physically.
|
||||
*/
|
||||
#define __PAGETABLE_PMD_FOLDED
|
||||
#define PMD_SHIFT 22
|
||||
#define PTRS_PER_PMD 1
|
||||
|
||||
|
|
|
@ -54,10 +54,12 @@
|
|||
*/
|
||||
#ifdef CONFIG_SUN3
|
||||
#define PTRS_PER_PTE 16
|
||||
#define __PAGETABLE_PMD_FOLDED
|
||||
#define PTRS_PER_PMD 1
|
||||
#define PTRS_PER_PGD 2048
|
||||
#elif defined(CONFIG_COLDFIRE)
|
||||
#define PTRS_PER_PTE 512
|
||||
#define __PAGETABLE_PMD_FOLDED
|
||||
#define PTRS_PER_PMD 1
|
||||
#define PTRS_PER_PGD 1024
|
||||
#else
|
||||
|
|
|
@ -149,8 +149,8 @@ extern void exit_thread(void);
|
|||
|
||||
unsigned long get_wchan(struct task_struct *p);
|
||||
|
||||
#define KSTK_EIP(tsk) ((tsk)->thread.kernel_context->CurrPC)
|
||||
#define KSTK_ESP(tsk) ((tsk)->thread.kernel_context->AX[0].U0)
|
||||
#define KSTK_EIP(tsk) (task_pt_regs(tsk)->ctx.CurrPC)
|
||||
#define KSTK_ESP(tsk) (task_pt_regs(tsk)->ctx.AX[0].U0)
|
||||
|
||||
#define user_stack_pointer(regs) ((regs)->ctx.AX[0].U0)
|
||||
|
||||
|
|
|
@ -56,7 +56,9 @@ extern void paging_init(void);
|
|||
#define PGDIR_SHIFT 22
|
||||
#define PTRS_PER_PGD 1024
|
||||
#define PTRS_PER_PUD 1 /* we don't really have any PUD physically */
|
||||
#define __PAGETABLE_PUD_FOLDED
|
||||
#define PTRS_PER_PMD 1 /* we don't really have any PMD physically */
|
||||
#define __PAGETABLE_PMD_FOLDED
|
||||
#define PTRS_PER_PTE 1024
|
||||
|
||||
#define PGD_SIZE PAGE_SIZE
|
||||
|
|
|
@ -96,6 +96,7 @@ extern void purge_tlb_entries(struct mm_struct *, unsigned long);
|
|||
#if PT_NLEVELS == 3
|
||||
#define BITS_PER_PMD (PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY)
|
||||
#else
|
||||
#define __PAGETABLE_PMD_FOLDED
|
||||
#define BITS_PER_PMD 0
|
||||
#endif
|
||||
#define PTRS_PER_PMD (1UL << BITS_PER_PMD)
|
||||
|
|
|
@ -91,7 +91,9 @@ extern unsigned long zero_page_mask;
|
|||
*/
|
||||
#define PTRS_PER_PTE 256
|
||||
#ifndef CONFIG_64BIT
|
||||
#define __PAGETABLE_PUD_FOLDED
|
||||
#define PTRS_PER_PMD 1
|
||||
#define __PAGETABLE_PMD_FOLDED
|
||||
#define PTRS_PER_PUD 1
|
||||
#else /* CONFIG_64BIT */
|
||||
#define PTRS_PER_PMD 2048
|
||||
|
|
|
@ -1396,6 +1396,12 @@ void cpu_init(void)
|
|||
|
||||
wait_for_master_cpu(cpu);
|
||||
|
||||
/*
|
||||
* Initialize the CR4 shadow before doing anything that could
|
||||
* try to read it.
|
||||
*/
|
||||
cr4_init_shadow();
|
||||
|
||||
show_ucode_info_early();
|
||||
|
||||
printk(KERN_INFO "Initializing CPU#%d\n", cpu);
|
||||
|
|
|
@ -565,8 +565,8 @@ static const struct _tlb_table intel_tlb_table[] = {
|
|||
{ 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
|
||||
{ 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
|
||||
{ 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
|
||||
{ 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set ssociative" },
|
||||
{ 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set ssociative" },
|
||||
{ 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
|
||||
{ 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
|
||||
{ 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
|
||||
{ 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
|
||||
{ 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
|
||||
|
|
|
@ -982,6 +982,9 @@ ENTRY(xen_hypervisor_callback)
|
|||
ENTRY(xen_do_upcall)
|
||||
1: mov %esp, %eax
|
||||
call xen_evtchn_do_upcall
|
||||
#ifndef CONFIG_PREEMPT
|
||||
call xen_maybe_preempt_hcall
|
||||
#endif
|
||||
jmp ret_from_intr
|
||||
CFI_ENDPROC
|
||||
ENDPROC(xen_hypervisor_callback)
|
||||
|
|
|
@ -1208,6 +1208,9 @@ ENTRY(xen_do_hypervisor_callback) # do_hypervisor_callback(struct *pt_regs)
|
|||
popq %rsp
|
||||
CFI_DEF_CFA_REGISTER rsp
|
||||
decl PER_CPU_VAR(irq_count)
|
||||
#ifndef CONFIG_PREEMPT
|
||||
call xen_maybe_preempt_hcall
|
||||
#endif
|
||||
jmp error_exit
|
||||
CFI_ENDPROC
|
||||
END(xen_do_hypervisor_callback)
|
||||
|
|
|
@ -223,27 +223,48 @@ static unsigned long
|
|||
__recover_probed_insn(kprobe_opcode_t *buf, unsigned long addr)
|
||||
{
|
||||
struct kprobe *kp;
|
||||
unsigned long faddr;
|
||||
|
||||
kp = get_kprobe((void *)addr);
|
||||
/* There is no probe, return original address */
|
||||
if (!kp)
|
||||
faddr = ftrace_location(addr);
|
||||
/*
|
||||
* Addresses inside the ftrace location are refused by
|
||||
* arch_check_ftrace_location(). Something went terribly wrong
|
||||
* if such an address is checked here.
|
||||
*/
|
||||
if (WARN_ON(faddr && faddr != addr))
|
||||
return 0UL;
|
||||
/*
|
||||
* Use the current code if it is not modified by Kprobe
|
||||
* and it cannot be modified by ftrace.
|
||||
*/
|
||||
if (!kp && !faddr)
|
||||
return addr;
|
||||
|
||||
/*
|
||||
* Basically, kp->ainsn.insn has an original instruction.
|
||||
* However, RIP-relative instruction can not do single-stepping
|
||||
* at different place, __copy_instruction() tweaks the displacement of
|
||||
* that instruction. In that case, we can't recover the instruction
|
||||
* from the kp->ainsn.insn.
|
||||
* Basically, kp->ainsn.insn has an original instruction.
|
||||
* However, RIP-relative instruction can not do single-stepping
|
||||
* at different place, __copy_instruction() tweaks the displacement of
|
||||
* that instruction. In that case, we can't recover the instruction
|
||||
* from the kp->ainsn.insn.
|
||||
*
|
||||
* On the other hand, kp->opcode has a copy of the first byte of
|
||||
* the probed instruction, which is overwritten by int3. And
|
||||
* the instruction at kp->addr is not modified by kprobes except
|
||||
* for the first byte, we can recover the original instruction
|
||||
* from it and kp->opcode.
|
||||
* On the other hand, in case on normal Kprobe, kp->opcode has a copy
|
||||
* of the first byte of the probed instruction, which is overwritten
|
||||
* by int3. And the instruction at kp->addr is not modified by kprobes
|
||||
* except for the first byte, we can recover the original instruction
|
||||
* from it and kp->opcode.
|
||||
*
|
||||
* In case of Kprobes using ftrace, we do not have a copy of
|
||||
* the original instruction. In fact, the ftrace location might
|
||||
* be modified at anytime and even could be in an inconsistent state.
|
||||
* Fortunately, we know that the original code is the ideal 5-byte
|
||||
* long NOP.
|
||||
*/
|
||||
memcpy(buf, kp->addr, MAX_INSN_SIZE * sizeof(kprobe_opcode_t));
|
||||
buf[0] = kp->opcode;
|
||||
memcpy(buf, (void *)addr, MAX_INSN_SIZE * sizeof(kprobe_opcode_t));
|
||||
if (faddr)
|
||||
memcpy(buf, ideal_nops[NOP_ATOMIC5], 5);
|
||||
else
|
||||
buf[0] = kp->opcode;
|
||||
return (unsigned long)buf;
|
||||
}
|
||||
|
||||
|
@ -251,6 +272,7 @@ __recover_probed_insn(kprobe_opcode_t *buf, unsigned long addr)
|
|||
* Recover the probed instruction at addr for further analysis.
|
||||
* Caller must lock kprobes by kprobe_mutex, or disable preemption
|
||||
* for preventing to release referencing kprobes.
|
||||
* Returns zero if the instruction can not get recovered.
|
||||
*/
|
||||
unsigned long recover_probed_instruction(kprobe_opcode_t *buf, unsigned long addr)
|
||||
{
|
||||
|
@ -285,6 +307,8 @@ static int can_probe(unsigned long paddr)
|
|||
* normally used, we just go through if there is no kprobe.
|
||||
*/
|
||||
__addr = recover_probed_instruction(buf, addr);
|
||||
if (!__addr)
|
||||
return 0;
|
||||
kernel_insn_init(&insn, (void *)__addr, MAX_INSN_SIZE);
|
||||
insn_get_length(&insn);
|
||||
|
||||
|
@ -333,6 +357,8 @@ int __copy_instruction(u8 *dest, u8 *src)
|
|||
unsigned long recovered_insn =
|
||||
recover_probed_instruction(buf, (unsigned long)src);
|
||||
|
||||
if (!recovered_insn)
|
||||
return 0;
|
||||
kernel_insn_init(&insn, (void *)recovered_insn, MAX_INSN_SIZE);
|
||||
insn_get_length(&insn);
|
||||
/* Another subsystem puts a breakpoint, failed to recover */
|
||||
|
|
|
@ -259,6 +259,8 @@ static int can_optimize(unsigned long paddr)
|
|||
*/
|
||||
return 0;
|
||||
recovered_insn = recover_probed_instruction(buf, addr);
|
||||
if (!recovered_insn)
|
||||
return 0;
|
||||
kernel_insn_init(&insn, (void *)recovered_insn, MAX_INSN_SIZE);
|
||||
insn_get_length(&insn);
|
||||
/* Another subsystem puts a breakpoint */
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
config LGUEST_GUEST
|
||||
bool "Lguest guest support"
|
||||
depends on X86_32 && PARAVIRT
|
||||
depends on X86_32 && PARAVIRT && PCI
|
||||
select TTY
|
||||
select VIRTUALIZATION
|
||||
select VIRTIO
|
||||
|
@ -8,7 +8,7 @@ config LGUEST_GUEST
|
|||
help
|
||||
Lguest is a tiny in-kernel hypervisor. Selecting this will
|
||||
allow your kernel to boot under lguest. This option will increase
|
||||
your kernel size by about 6k. If in doubt, say N.
|
||||
your kernel size by about 10k. If in doubt, say N.
|
||||
|
||||
If you say Y here, make sure you say Y (or M) to the virtio block
|
||||
and net drivers which lguest needs.
|
||||
|
|
|
@ -130,7 +130,7 @@ static void intel_mid_arch_setup(void)
|
|||
intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip]();
|
||||
else {
|
||||
intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL]();
|
||||
pr_info("ARCH: Uknown SoC, assuming PENWELL!\n");
|
||||
pr_info("ARCH: Unknown SoC, assuming PENWELL!\n");
|
||||
}
|
||||
|
||||
out:
|
||||
|
|
|
@ -1070,6 +1070,23 @@ static inline void xen_write_cr8(unsigned long val)
|
|||
BUG_ON(val);
|
||||
}
|
||||
#endif
|
||||
|
||||
static u64 xen_read_msr_safe(unsigned int msr, int *err)
|
||||
{
|
||||
u64 val;
|
||||
|
||||
val = native_read_msr_safe(msr, err);
|
||||
switch (msr) {
|
||||
case MSR_IA32_APICBASE:
|
||||
#ifdef CONFIG_X86_X2APIC
|
||||
if (!(cpuid_ecx(1) & (1 << (X86_FEATURE_X2APIC & 31))))
|
||||
#endif
|
||||
val &= ~X2APIC_ENABLE;
|
||||
break;
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
static int xen_write_msr_safe(unsigned int msr, unsigned low, unsigned high)
|
||||
{
|
||||
int ret;
|
||||
|
@ -1240,7 +1257,7 @@ static const struct pv_cpu_ops xen_cpu_ops __initconst = {
|
|||
|
||||
.wbinvd = native_wbinvd,
|
||||
|
||||
.read_msr = native_read_msr_safe,
|
||||
.read_msr = xen_read_msr_safe,
|
||||
.write_msr = xen_write_msr_safe,
|
||||
|
||||
.read_tsc = native_read_tsc,
|
||||
|
@ -1741,6 +1758,7 @@ asmlinkage __visible void __init xen_start_kernel(void)
|
|||
#ifdef CONFIG_X86_32
|
||||
i386_start_kernel();
|
||||
#else
|
||||
cr4_init_shadow(); /* 32b kernel does this in i386_start_kernel() */
|
||||
x86_64_start_reservations((char *)__pa_symbol(&boot_params));
|
||||
#endif
|
||||
}
|
||||
|
|
|
@ -482,6 +482,7 @@ static int nvme_error_status(u16 status)
|
|||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_BLK_DEV_INTEGRITY
|
||||
static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
|
||||
{
|
||||
if (be32_to_cpu(pi->ref_tag) == v)
|
||||
|
@ -538,6 +539,58 @@ static void nvme_dif_remap(struct request *req,
|
|||
kunmap_atomic(pmap);
|
||||
}
|
||||
|
||||
static int nvme_noop_verify(struct blk_integrity_iter *iter)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nvme_noop_generate(struct blk_integrity_iter *iter)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct blk_integrity nvme_meta_noop = {
|
||||
.name = "NVME_META_NOOP",
|
||||
.generate_fn = nvme_noop_generate,
|
||||
.verify_fn = nvme_noop_verify,
|
||||
};
|
||||
|
||||
static void nvme_init_integrity(struct nvme_ns *ns)
|
||||
{
|
||||
struct blk_integrity integrity;
|
||||
|
||||
switch (ns->pi_type) {
|
||||
case NVME_NS_DPS_PI_TYPE3:
|
||||
integrity = t10_pi_type3_crc;
|
||||
break;
|
||||
case NVME_NS_DPS_PI_TYPE1:
|
||||
case NVME_NS_DPS_PI_TYPE2:
|
||||
integrity = t10_pi_type1_crc;
|
||||
break;
|
||||
default:
|
||||
integrity = nvme_meta_noop;
|
||||
break;
|
||||
}
|
||||
integrity.tuple_size = ns->ms;
|
||||
blk_integrity_register(ns->disk, &integrity);
|
||||
blk_queue_max_integrity_segments(ns->queue, 1);
|
||||
}
|
||||
#else /* CONFIG_BLK_DEV_INTEGRITY */
|
||||
static void nvme_dif_remap(struct request *req,
|
||||
void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
|
||||
{
|
||||
}
|
||||
static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
|
||||
{
|
||||
}
|
||||
static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
|
||||
{
|
||||
}
|
||||
static void nvme_init_integrity(struct nvme_ns *ns)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
static void req_completion(struct nvme_queue *nvmeq, void *ctx,
|
||||
struct nvme_completion *cqe)
|
||||
{
|
||||
|
@ -1959,43 +2012,6 @@ static void nvme_config_discard(struct nvme_ns *ns)
|
|||
queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
|
||||
}
|
||||
|
||||
static int nvme_noop_verify(struct blk_integrity_iter *iter)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nvme_noop_generate(struct blk_integrity_iter *iter)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct blk_integrity nvme_meta_noop = {
|
||||
.name = "NVME_META_NOOP",
|
||||
.generate_fn = nvme_noop_generate,
|
||||
.verify_fn = nvme_noop_verify,
|
||||
};
|
||||
|
||||
static void nvme_init_integrity(struct nvme_ns *ns)
|
||||
{
|
||||
struct blk_integrity integrity;
|
||||
|
||||
switch (ns->pi_type) {
|
||||
case NVME_NS_DPS_PI_TYPE3:
|
||||
integrity = t10_pi_type3_crc;
|
||||
break;
|
||||
case NVME_NS_DPS_PI_TYPE1:
|
||||
case NVME_NS_DPS_PI_TYPE2:
|
||||
integrity = t10_pi_type1_crc;
|
||||
break;
|
||||
default:
|
||||
integrity = nvme_meta_noop;
|
||||
break;
|
||||
}
|
||||
integrity.tuple_size = ns->ms;
|
||||
blk_integrity_register(ns->disk, &integrity);
|
||||
blk_queue_max_integrity_segments(ns->queue, 1);
|
||||
}
|
||||
|
||||
static int nvme_revalidate_disk(struct gendisk *disk)
|
||||
{
|
||||
struct nvme_ns *ns = disk->private_data;
|
||||
|
@ -2036,7 +2052,8 @@ static int nvme_revalidate_disk(struct gendisk *disk)
|
|||
pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
|
||||
id->dps & NVME_NS_DPS_PI_MASK : 0;
|
||||
|
||||
if (disk->integrity && (ns->pi_type != pi_type || ns->ms != old_ms ||
|
||||
if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
|
||||
ns->ms != old_ms ||
|
||||
bs != queue_logical_block_size(disk->queue) ||
|
||||
(ns->ms && id->flbas & NVME_NS_FLBAS_META_EXT)))
|
||||
blk_integrity_unregister(disk);
|
||||
|
@ -2044,11 +2061,11 @@ static int nvme_revalidate_disk(struct gendisk *disk)
|
|||
ns->pi_type = pi_type;
|
||||
blk_queue_logical_block_size(ns->queue, bs);
|
||||
|
||||
if (ns->ms && !disk->integrity && (disk->flags & GENHD_FL_UP) &&
|
||||
if (ns->ms && !blk_get_integrity(disk) && (disk->flags & GENHD_FL_UP) &&
|
||||
!(id->flbas & NVME_NS_FLBAS_META_EXT))
|
||||
nvme_init_integrity(ns);
|
||||
|
||||
if (id->ncap == 0 || (ns->ms && !disk->integrity))
|
||||
if (id->ncap == 0 || (ns->ms && !blk_get_integrity(disk)))
|
||||
set_capacity(disk, 0);
|
||||
else
|
||||
set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
|
||||
|
@ -2652,7 +2669,7 @@ static void nvme_dev_remove(struct nvme_dev *dev)
|
|||
|
||||
list_for_each_entry(ns, &dev->namespaces, list) {
|
||||
if (ns->disk->flags & GENHD_FL_UP) {
|
||||
if (ns->disk->integrity)
|
||||
if (blk_get_integrity(ns->disk))
|
||||
blk_integrity_unregister(ns->disk);
|
||||
del_gendisk(ns->disk);
|
||||
}
|
||||
|
|
|
@ -528,7 +528,7 @@ out_cleanup:
|
|||
static inline void update_used_max(struct zram *zram,
|
||||
const unsigned long pages)
|
||||
{
|
||||
int old_max, cur_max;
|
||||
unsigned long old_max, cur_max;
|
||||
|
||||
old_max = atomic_long_read(&zram->stats.max_used_pages);
|
||||
|
||||
|
|
|
@ -63,6 +63,11 @@ config VT8500_TIMER
|
|||
config CADENCE_TTC_TIMER
|
||||
bool
|
||||
|
||||
config ASM9260_TIMER
|
||||
bool
|
||||
select CLKSRC_MMIO
|
||||
select CLKSRC_OF
|
||||
|
||||
config CLKSRC_NOMADIK_MTU
|
||||
bool
|
||||
depends on (ARCH_NOMADIK || ARCH_U8500)
|
||||
|
@ -245,15 +250,4 @@ config CLKSRC_PXA
|
|||
help
|
||||
This enables OST0 support available on PXA and SA-11x0
|
||||
platforms.
|
||||
|
||||
config ASM9260_TIMER
|
||||
bool "Alphascale ASM9260 timer driver"
|
||||
depends on GENERIC_CLOCKEVENTS
|
||||
select CLKSRC_MMIO
|
||||
select CLKSRC_OF
|
||||
default y if MACH_ASM9260
|
||||
help
|
||||
This enables build of a clocksource and clockevent driver for
|
||||
the 32-bit System Timer hardware available on a Alphascale ASM9260.
|
||||
|
||||
endmenu
|
||||
|
|
|
@ -224,6 +224,8 @@ static void __init mtk_timer_init(struct device_node *node)
|
|||
}
|
||||
rate = clk_get_rate(clk);
|
||||
|
||||
mtk_timer_global_reset(evt);
|
||||
|
||||
if (request_irq(evt->dev.irq, mtk_timer_interrupt,
|
||||
IRQF_TIMER | IRQF_IRQPOLL, "mtk_timer", evt)) {
|
||||
pr_warn("failed to setup irq %d\n", evt->dev.irq);
|
||||
|
@ -232,8 +234,6 @@ static void __init mtk_timer_init(struct device_node *node)
|
|||
|
||||
evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
|
||||
|
||||
mtk_timer_global_reset(evt);
|
||||
|
||||
/* Configure clock source */
|
||||
mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN);
|
||||
clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC),
|
||||
|
@ -241,10 +241,11 @@ static void __init mtk_timer_init(struct device_node *node)
|
|||
|
||||
/* Configure clock event */
|
||||
mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT);
|
||||
mtk_timer_enable_irq(evt, GPT_CLK_EVT);
|
||||
|
||||
clockevents_config_and_register(&evt->dev, rate, 0x3,
|
||||
0xffffffff);
|
||||
|
||||
mtk_timer_enable_irq(evt, GPT_CLK_EVT);
|
||||
|
||||
return;
|
||||
|
||||
err_clk_disable:
|
||||
|
|
|
@ -163,7 +163,7 @@ static struct irqaction pxa_ost0_irq = {
|
|||
.dev_id = &ckevt_pxa_osmr0,
|
||||
};
|
||||
|
||||
static void pxa_timer_common_init(int irq, unsigned long clock_tick_rate)
|
||||
static void __init pxa_timer_common_init(int irq, unsigned long clock_tick_rate)
|
||||
{
|
||||
timer_writel(0, OIER);
|
||||
timer_writel(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
|
||||
|
|
|
@ -26,9 +26,12 @@ struct tps65912_gpio_data {
|
|||
struct gpio_chip gpio_chip;
|
||||
};
|
||||
|
||||
#define to_tgd(gc) container_of(gc, struct tps65912_gpio_data, gpio_chip)
|
||||
|
||||
static int tps65912_gpio_get(struct gpio_chip *gc, unsigned offset)
|
||||
{
|
||||
struct tps65912 *tps65912 = container_of(gc, struct tps65912, gpio);
|
||||
struct tps65912_gpio_data *tps65912_gpio = to_tgd(gc);
|
||||
struct tps65912 *tps65912 = tps65912_gpio->tps65912;
|
||||
int val;
|
||||
|
||||
val = tps65912_reg_read(tps65912, TPS65912_GPIO1 + offset);
|
||||
|
@ -42,7 +45,8 @@ static int tps65912_gpio_get(struct gpio_chip *gc, unsigned offset)
|
|||
static void tps65912_gpio_set(struct gpio_chip *gc, unsigned offset,
|
||||
int value)
|
||||
{
|
||||
struct tps65912 *tps65912 = container_of(gc, struct tps65912, gpio);
|
||||
struct tps65912_gpio_data *tps65912_gpio = to_tgd(gc);
|
||||
struct tps65912 *tps65912 = tps65912_gpio->tps65912;
|
||||
|
||||
if (value)
|
||||
tps65912_set_bits(tps65912, TPS65912_GPIO1 + offset,
|
||||
|
@ -55,7 +59,8 @@ static void tps65912_gpio_set(struct gpio_chip *gc, unsigned offset,
|
|||
static int tps65912_gpio_output(struct gpio_chip *gc, unsigned offset,
|
||||
int value)
|
||||
{
|
||||
struct tps65912 *tps65912 = container_of(gc, struct tps65912, gpio);
|
||||
struct tps65912_gpio_data *tps65912_gpio = to_tgd(gc);
|
||||
struct tps65912 *tps65912 = tps65912_gpio->tps65912;
|
||||
|
||||
/* Set the initial value */
|
||||
tps65912_gpio_set(gc, offset, value);
|
||||
|
@ -66,7 +71,8 @@ static int tps65912_gpio_output(struct gpio_chip *gc, unsigned offset,
|
|||
|
||||
static int tps65912_gpio_input(struct gpio_chip *gc, unsigned offset)
|
||||
{
|
||||
struct tps65912 *tps65912 = container_of(gc, struct tps65912, gpio);
|
||||
struct tps65912_gpio_data *tps65912_gpio = to_tgd(gc);
|
||||
struct tps65912 *tps65912 = tps65912_gpio->tps65912;
|
||||
|
||||
return tps65912_clear_bits(tps65912, TPS65912_GPIO1 + offset,
|
||||
GPIO_CFG_MASK);
|
||||
|
|
|
@ -46,12 +46,13 @@ static int of_gpiochip_find_and_xlate(struct gpio_chip *gc, void *data)
|
|||
|
||||
ret = gc->of_xlate(gc, &gg_data->gpiospec, gg_data->flags);
|
||||
if (ret < 0) {
|
||||
/* We've found the gpio chip, but the translation failed.
|
||||
* Return true to stop looking and return the translation
|
||||
* error via out_gpio
|
||||
/* We've found a gpio chip, but the translation failed.
|
||||
* Store translation error in out_gpio.
|
||||
* Return false to keep looking, as more than one gpio chip
|
||||
* could be registered per of-node.
|
||||
*/
|
||||
gg_data->out_gpio = ERR_PTR(ret);
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
|
||||
gg_data->out_gpio = gpiochip_get_desc(gc, ret);
|
||||
|
|
|
@ -62,12 +62,18 @@ enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type)
|
|||
return KFD_MQD_TYPE_CP;
|
||||
}
|
||||
|
||||
static inline unsigned int get_first_pipe(struct device_queue_manager *dqm)
|
||||
unsigned int get_first_pipe(struct device_queue_manager *dqm)
|
||||
{
|
||||
BUG_ON(!dqm);
|
||||
BUG_ON(!dqm || !dqm->dev);
|
||||
return dqm->dev->shared_resources.first_compute_pipe;
|
||||
}
|
||||
|
||||
unsigned int get_pipes_num(struct device_queue_manager *dqm)
|
||||
{
|
||||
BUG_ON(!dqm || !dqm->dev);
|
||||
return dqm->dev->shared_resources.compute_pipe_count;
|
||||
}
|
||||
|
||||
static inline unsigned int get_pipes_num_cpsch(void)
|
||||
{
|
||||
return PIPE_PER_ME_CP_SCHEDULING;
|
||||
|
|
|
@ -163,6 +163,8 @@ void program_sh_mem_settings(struct device_queue_manager *dqm,
|
|||
struct qcm_process_device *qpd);
|
||||
int init_pipelines(struct device_queue_manager *dqm,
|
||||
unsigned int pipes_num, unsigned int first_pipe);
|
||||
unsigned int get_first_pipe(struct device_queue_manager *dqm);
|
||||
unsigned int get_pipes_num(struct device_queue_manager *dqm);
|
||||
|
||||
extern inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd)
|
||||
{
|
||||
|
@ -175,10 +177,4 @@ get_sh_mem_bases_nybble_64(struct kfd_process_device *pdd)
|
|||
return (pdd->lds_base >> 60) & 0x0E;
|
||||
}
|
||||
|
||||
extern inline unsigned int get_pipes_num(struct device_queue_manager *dqm)
|
||||
{
|
||||
BUG_ON(!dqm || !dqm->dev);
|
||||
return dqm->dev->shared_resources.compute_pipe_count;
|
||||
}
|
||||
|
||||
#endif /* KFD_DEVICE_QUEUE_MANAGER_H_ */
|
||||
|
|
|
@ -131,5 +131,5 @@ static int register_process_cik(struct device_queue_manager *dqm,
|
|||
|
||||
static int initialize_cpsch_cik(struct device_queue_manager *dqm)
|
||||
{
|
||||
return init_pipelines(dqm, get_pipes_num(dqm), 0);
|
||||
return init_pipelines(dqm, get_pipes_num(dqm), get_first_pipe(dqm));
|
||||
}
|
||||
|
|
|
@ -153,7 +153,7 @@ static int atmel_hlcdc_crtc_mode_set(struct drm_crtc *c,
|
|||
(adj->crtc_hdisplay - 1) |
|
||||
((adj->crtc_vdisplay - 1) << 16));
|
||||
|
||||
cfg = ATMEL_HLCDC_CLKPOL;
|
||||
cfg = 0;
|
||||
|
||||
prate = clk_get_rate(crtc->dc->hlcdc->sys_clk);
|
||||
mode_rate = mode->crtc_clock * 1000;
|
||||
|
|
|
@ -311,8 +311,6 @@ static int atmel_hlcdc_dc_load(struct drm_device *dev)
|
|||
|
||||
pm_runtime_enable(dev->dev);
|
||||
|
||||
pm_runtime_put_sync(dev->dev);
|
||||
|
||||
ret = atmel_hlcdc_dc_modeset_init(dev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev->dev, "failed to initialize mode setting\n");
|
||||
|
|
|
@ -311,7 +311,8 @@ int atmel_hlcdc_layer_disable(struct atmel_hlcdc_layer *layer)
|
|||
|
||||
/* Disable the layer */
|
||||
regmap_write(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_CHDR,
|
||||
ATMEL_HLCDC_LAYER_RST);
|
||||
ATMEL_HLCDC_LAYER_RST | ATMEL_HLCDC_LAYER_A2Q |
|
||||
ATMEL_HLCDC_LAYER_UPDATE);
|
||||
|
||||
/* Clear all pending interrupts */
|
||||
regmap_read(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_ISR, &isr);
|
||||
|
|
|
@ -2127,7 +2127,6 @@ int drm_mode_getconnector(struct drm_device *dev, void *data,
|
|||
DRM_DEBUG_KMS("[CONNECTOR:%d:?]\n", out_resp->connector_id);
|
||||
|
||||
mutex_lock(&dev->mode_config.mutex);
|
||||
drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
|
||||
|
||||
connector = drm_connector_find(dev, out_resp->connector_id);
|
||||
if (!connector) {
|
||||
|
@ -2157,6 +2156,8 @@ int drm_mode_getconnector(struct drm_device *dev, void *data,
|
|||
out_resp->mm_height = connector->display_info.height_mm;
|
||||
out_resp->subpixel = connector->display_info.subpixel_order;
|
||||
out_resp->connection = connector->status;
|
||||
|
||||
drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
|
||||
encoder = drm_connector_get_encoder(connector);
|
||||
if (encoder)
|
||||
out_resp->encoder_id = encoder->base.id;
|
||||
|
|
|
@ -2114,6 +2114,9 @@ void i915_gem_track_fb(struct drm_i915_gem_object *old,
|
|||
* number comparisons on buffer last_read|write_seqno. It also allows an
|
||||
* emission time to be associated with the request for tracking how far ahead
|
||||
* of the GPU the submission is.
|
||||
*
|
||||
* The requests are reference counted, so upon creation they should have an
|
||||
* initial reference taken using kref_init
|
||||
*/
|
||||
struct drm_i915_gem_request {
|
||||
struct kref ref;
|
||||
|
@ -2137,7 +2140,16 @@ struct drm_i915_gem_request {
|
|||
/** Position in the ringbuffer of the end of the whole request */
|
||||
u32 tail;
|
||||
|
||||
/** Context related to this request */
|
||||
/**
|
||||
* Context related to this request
|
||||
* Contexts are refcounted, so when this request is associated with a
|
||||
* context, we must increment the context's refcount, to guarantee that
|
||||
* it persists while any request is linked to it. Requests themselves
|
||||
* are also refcounted, so the request will only be freed when the last
|
||||
* reference to it is dismissed, and the code in
|
||||
* i915_gem_request_free() will then decrement the refcount on the
|
||||
* context.
|
||||
*/
|
||||
struct intel_context *ctx;
|
||||
|
||||
/** Batch buffer related to this request if any */
|
||||
|
@ -2374,6 +2386,7 @@ struct drm_i915_cmd_table {
|
|||
(INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
|
||||
#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
|
||||
((INTEL_DEVID(dev) & 0xf) == 0x6 || \
|
||||
(INTEL_DEVID(dev) & 0xf) == 0xb || \
|
||||
(INTEL_DEVID(dev) & 0xf) == 0xe))
|
||||
#define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
|
||||
(INTEL_DEVID(dev) & 0x00F0) == 0x0020)
|
||||
|
|
|
@ -2659,8 +2659,7 @@ static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
|
|||
if (submit_req->ctx != ring->default_context)
|
||||
intel_lr_context_unpin(ring, submit_req->ctx);
|
||||
|
||||
i915_gem_context_unreference(submit_req->ctx);
|
||||
kfree(submit_req);
|
||||
i915_gem_request_unreference(submit_req);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -485,10 +485,8 @@ i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
|
|||
stolen_offset, gtt_offset, size);
|
||||
|
||||
/* KISS and expect everything to be page-aligned */
|
||||
BUG_ON(stolen_offset & 4095);
|
||||
BUG_ON(size & 4095);
|
||||
|
||||
if (WARN_ON(size == 0))
|
||||
if (WARN_ON(size == 0) || WARN_ON(size & 4095) ||
|
||||
WARN_ON(stolen_offset & 4095))
|
||||
return NULL;
|
||||
|
||||
stolen = kzalloc(sizeof(*stolen), GFP_KERNEL);
|
||||
|
|
|
@ -335,9 +335,10 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
if (i915_gem_obj_is_pinned(obj) || obj->framebuffer_references) {
|
||||
drm_gem_object_unreference_unlocked(&obj->base);
|
||||
return -EBUSY;
|
||||
ret = -EBUSY;
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (args->tiling_mode == I915_TILING_NONE) {
|
||||
|
@ -369,7 +370,6 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
|
|||
}
|
||||
}
|
||||
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
if (args->tiling_mode != obj->tiling_mode ||
|
||||
args->stride != obj->stride) {
|
||||
/* We need to rebind the object if its current allocation
|
||||
|
@ -424,6 +424,7 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
|
|||
obj->bit_17 = NULL;
|
||||
}
|
||||
|
||||
err:
|
||||
drm_gem_object_unreference(&obj->base);
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
|
||||
|
|
|
@ -1892,6 +1892,9 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
|
|||
u32 iir, gt_iir, pm_iir;
|
||||
irqreturn_t ret = IRQ_NONE;
|
||||
|
||||
if (!intel_irqs_enabled(dev_priv))
|
||||
return IRQ_NONE;
|
||||
|
||||
while (true) {
|
||||
/* Find, clear, then process each source of interrupt */
|
||||
|
||||
|
@ -1936,6 +1939,9 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
|
|||
u32 master_ctl, iir;
|
||||
irqreturn_t ret = IRQ_NONE;
|
||||
|
||||
if (!intel_irqs_enabled(dev_priv))
|
||||
return IRQ_NONE;
|
||||
|
||||
for (;;) {
|
||||
master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
|
||||
iir = I915_READ(VLV_IIR);
|
||||
|
@ -2208,6 +2214,9 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
|
|||
u32 de_iir, gt_iir, de_ier, sde_ier = 0;
|
||||
irqreturn_t ret = IRQ_NONE;
|
||||
|
||||
if (!intel_irqs_enabled(dev_priv))
|
||||
return IRQ_NONE;
|
||||
|
||||
/* We get interrupts on unclaimed registers, so check for this before we
|
||||
* do any I915_{READ,WRITE}. */
|
||||
intel_uncore_check_errors(dev);
|
||||
|
@ -2279,6 +2288,9 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
|
|||
enum pipe pipe;
|
||||
u32 aux_mask = GEN8_AUX_CHANNEL_A;
|
||||
|
||||
if (!intel_irqs_enabled(dev_priv))
|
||||
return IRQ_NONE;
|
||||
|
||||
if (IS_GEN9(dev))
|
||||
aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
|
||||
GEN9_AUX_CHANNEL_D;
|
||||
|
@ -3771,6 +3783,9 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
|
|||
I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
|
||||
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
|
||||
|
||||
if (!intel_irqs_enabled(dev_priv))
|
||||
return IRQ_NONE;
|
||||
|
||||
iir = I915_READ16(IIR);
|
||||
if (iir == 0)
|
||||
return IRQ_NONE;
|
||||
|
@ -3951,6 +3966,9 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
|
|||
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
|
||||
int pipe, ret = IRQ_NONE;
|
||||
|
||||
if (!intel_irqs_enabled(dev_priv))
|
||||
return IRQ_NONE;
|
||||
|
||||
iir = I915_READ(IIR);
|
||||
do {
|
||||
bool irq_received = (iir & ~flip_mask) != 0;
|
||||
|
@ -4171,6 +4189,9 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
|
|||
I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
|
||||
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
|
||||
|
||||
if (!intel_irqs_enabled(dev_priv))
|
||||
return IRQ_NONE;
|
||||
|
||||
iir = I915_READ(IIR);
|
||||
|
||||
for (;;) {
|
||||
|
@ -4520,6 +4541,7 @@ void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
|
|||
{
|
||||
dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
|
||||
dev_priv->pm.irqs_enabled = false;
|
||||
synchronize_irq(dev_priv->dev->irq);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
@ -2371,13 +2371,19 @@ intel_alloc_plane_obj(struct intel_crtc *crtc,
|
|||
struct drm_device *dev = crtc->base.dev;
|
||||
struct drm_i915_gem_object *obj = NULL;
|
||||
struct drm_mode_fb_cmd2 mode_cmd = { 0 };
|
||||
u32 base = plane_config->base;
|
||||
u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
|
||||
u32 size_aligned = round_up(plane_config->base + plane_config->size,
|
||||
PAGE_SIZE);
|
||||
|
||||
size_aligned -= base_aligned;
|
||||
|
||||
if (plane_config->size == 0)
|
||||
return false;
|
||||
|
||||
obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
|
||||
plane_config->size);
|
||||
obj = i915_gem_object_create_stolen_for_preallocated(dev,
|
||||
base_aligned,
|
||||
base_aligned,
|
||||
size_aligned);
|
||||
if (!obj)
|
||||
return false;
|
||||
|
||||
|
@ -2725,10 +2731,19 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
|
|||
case DRM_FORMAT_XRGB8888:
|
||||
plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
|
||||
break;
|
||||
case DRM_FORMAT_ARGB8888:
|
||||
plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
|
||||
plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
|
||||
break;
|
||||
case DRM_FORMAT_XBGR8888:
|
||||
plane_ctl |= PLANE_CTL_ORDER_RGBX;
|
||||
plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
|
||||
break;
|
||||
case DRM_FORMAT_ABGR8888:
|
||||
plane_ctl |= PLANE_CTL_ORDER_RGBX;
|
||||
plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
|
||||
plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
|
||||
break;
|
||||
case DRM_FORMAT_XRGB2101010:
|
||||
plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
|
||||
break;
|
||||
|
@ -6627,7 +6642,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
|
|||
aligned_height = intel_fb_align_height(dev, fb->height,
|
||||
plane_config->tiling);
|
||||
|
||||
plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
|
||||
plane_config->size = fb->pitches[0] * aligned_height;
|
||||
|
||||
DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
|
||||
pipe_name(pipe), plane, fb->width, fb->height,
|
||||
|
@ -7664,7 +7679,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
|
|||
aligned_height = intel_fb_align_height(dev, fb->height,
|
||||
plane_config->tiling);
|
||||
|
||||
plane_config->size = ALIGN(fb->pitches[0] * aligned_height, PAGE_SIZE);
|
||||
plane_config->size = fb->pitches[0] * aligned_height;
|
||||
|
||||
DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
|
||||
pipe_name(pipe), fb->width, fb->height,
|
||||
|
@ -7755,7 +7770,7 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
|
|||
aligned_height = intel_fb_align_height(dev, fb->height,
|
||||
plane_config->tiling);
|
||||
|
||||
plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
|
||||
plane_config->size = fb->pitches[0] * aligned_height;
|
||||
|
||||
DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
|
||||
pipe_name(pipe), fb->width, fb->height,
|
||||
|
@ -8698,6 +8713,7 @@ retry:
|
|||
old->release_fb->funcs->destroy(old->release_fb);
|
||||
goto fail;
|
||||
}
|
||||
crtc->primary->crtc = crtc;
|
||||
|
||||
/* let the connector get through one full cycle before testing */
|
||||
intel_wait_for_vblank(dev, intel_crtc->pipe);
|
||||
|
@ -12182,9 +12198,6 @@ intel_check_cursor_plane(struct drm_plane *plane,
|
|||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if (fb == crtc->cursor->fb)
|
||||
return 0;
|
||||
|
||||
/* we only need to pin inside GTT if cursor is non-phy */
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
|
||||
|
@ -13096,6 +13109,9 @@ static struct intel_quirk intel_quirks[] = {
|
|||
|
||||
/* HP Chromebook 14 (Celeron 2955U) */
|
||||
{ 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
|
||||
|
||||
/* Dell Chromebook 11 */
|
||||
{ 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
|
||||
};
|
||||
|
||||
static void intel_init_quirks(struct drm_device *dev)
|
||||
|
|
|
@ -503,18 +503,19 @@ static int execlists_context_queue(struct intel_engine_cs *ring,
|
|||
* If there isn't a request associated with this submission,
|
||||
* create one as a temporary holder.
|
||||
*/
|
||||
WARN(1, "execlist context submission without request");
|
||||
request = kzalloc(sizeof(*request), GFP_KERNEL);
|
||||
if (request == NULL)
|
||||
return -ENOMEM;
|
||||
request->ring = ring;
|
||||
request->ctx = to;
|
||||
kref_init(&request->ref);
|
||||
request->uniq = dev_priv->request_uniq++;
|
||||
i915_gem_context_reference(request->ctx);
|
||||
} else {
|
||||
i915_gem_request_reference(request);
|
||||
WARN_ON(to != request->ctx);
|
||||
}
|
||||
request->tail = tail;
|
||||
i915_gem_request_reference(request);
|
||||
i915_gem_context_reference(request->ctx);
|
||||
|
||||
intel_runtime_pm_get(dev_priv);
|
||||
|
||||
|
@ -731,7 +732,6 @@ void intel_execlists_retire_requests(struct intel_engine_cs *ring)
|
|||
if (ctx_obj && (ctx != ring->default_context))
|
||||
intel_lr_context_unpin(ring, ctx);
|
||||
intel_runtime_pm_put(dev_priv);
|
||||
i915_gem_context_unreference(ctx);
|
||||
list_del(&req->execlist_link);
|
||||
i915_gem_request_unreference(req);
|
||||
}
|
||||
|
|
|
@ -178,6 +178,13 @@ radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
|
|||
switch (msg->request & ~DP_AUX_I2C_MOT) {
|
||||
case DP_AUX_NATIVE_WRITE:
|
||||
case DP_AUX_I2C_WRITE:
|
||||
/* The atom implementation only supports writes with a max payload of
|
||||
* 12 bytes since it uses 4 bits for the total count (header + payload)
|
||||
* in the parameter space. The atom interface supports 16 byte
|
||||
* payloads for reads. The hw itself supports up to 16 bytes of payload.
|
||||
*/
|
||||
if (WARN_ON_ONCE(msg->size > 12))
|
||||
return -E2BIG;
|
||||
/* tx_size needs to be 4 even for bare address packets since the atom
|
||||
* table needs the info in tx_buf[3].
|
||||
*/
|
||||
|
|
|
@ -731,7 +731,9 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
|
|||
dig_connector = radeon_connector->con_priv;
|
||||
if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
|
||||
(dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
|
||||
if (radeon_audio != 0 && ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
|
||||
if (radeon_audio != 0 &&
|
||||
drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
|
||||
ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
|
||||
return ATOM_ENCODER_MODE_DP_AUDIO;
|
||||
return ATOM_ENCODER_MODE_DP;
|
||||
} else if (radeon_audio != 0) {
|
||||
|
@ -747,7 +749,9 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
|
|||
}
|
||||
break;
|
||||
case DRM_MODE_CONNECTOR_eDP:
|
||||
if (radeon_audio != 0 && ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
|
||||
if (radeon_audio != 0 &&
|
||||
drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
|
||||
ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
|
||||
return ATOM_ENCODER_MODE_DP_AUDIO;
|
||||
return ATOM_ENCODER_MODE_DP;
|
||||
case DRM_MODE_CONNECTOR_DVIA:
|
||||
|
@ -1720,8 +1724,10 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
|
|||
}
|
||||
|
||||
encoder_mode = atombios_get_encoder_mode(encoder);
|
||||
if (radeon_audio != 0 &&
|
||||
(encoder_mode == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(encoder_mode)))
|
||||
if (connector && (radeon_audio != 0) &&
|
||||
((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
|
||||
(ENCODER_MODE_IS_DP(encoder_mode) &&
|
||||
drm_detect_monitor_audio(radeon_connector_edid(connector)))))
|
||||
radeon_audio_dpms(encoder, mode);
|
||||
}
|
||||
|
||||
|
@ -2136,6 +2142,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
|
|||
struct drm_device *dev = encoder->dev;
|
||||
struct radeon_device *rdev = dev->dev_private;
|
||||
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
|
||||
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
|
||||
int encoder_mode;
|
||||
|
||||
radeon_encoder->pixel_clock = adjusted_mode->clock;
|
||||
|
@ -2164,8 +2171,10 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
|
|||
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
|
||||
/* handled in dpms */
|
||||
encoder_mode = atombios_get_encoder_mode(encoder);
|
||||
if (radeon_audio != 0 &&
|
||||
(encoder_mode == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(encoder_mode)))
|
||||
if (connector && (radeon_audio != 0) &&
|
||||
((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
|
||||
(ENCODER_MODE_IS_DP(encoder_mode) &&
|
||||
drm_detect_monitor_audio(radeon_connector_edid(connector)))))
|
||||
radeon_audio_mode_set(encoder, adjusted_mode);
|
||||
break;
|
||||
case ENCODER_OBJECT_ID_INTERNAL_DDI:
|
||||
|
|
|
@ -3613,6 +3613,8 @@ static void cik_gpu_init(struct radeon_device *rdev)
|
|||
}
|
||||
|
||||
WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
|
||||
WREG32(SRBM_INT_CNTL, 0x1);
|
||||
WREG32(SRBM_INT_ACK, 0x1);
|
||||
|
||||
WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
|
||||
|
||||
|
@ -7230,6 +7232,8 @@ static void cik_disable_interrupt_state(struct radeon_device *rdev)
|
|||
WREG32(CP_ME2_PIPE3_INT_CNTL, 0);
|
||||
/* grbm */
|
||||
WREG32(GRBM_INT_CNTL, 0);
|
||||
/* SRBM */
|
||||
WREG32(SRBM_INT_CNTL, 0);
|
||||
/* vline/vblank, etc. */
|
||||
WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
|
||||
WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
|
||||
|
@ -8046,6 +8050,10 @@ restart_ih:
|
|||
break;
|
||||
}
|
||||
break;
|
||||
case 96:
|
||||
DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
|
||||
WREG32(SRBM_INT_ACK, 0x1);
|
||||
break;
|
||||
case 124: /* UVD */
|
||||
DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
|
||||
radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
|
||||
|
|
|
@ -482,6 +482,10 @@
|
|||
#define SOFT_RESET_ORB (1 << 23)
|
||||
#define SOFT_RESET_VCE (1 << 24)
|
||||
|
||||
#define SRBM_READ_ERROR 0xE98
|
||||
#define SRBM_INT_CNTL 0xEA0
|
||||
#define SRBM_INT_ACK 0xEA8
|
||||
|
||||
#define VM_L2_CNTL 0x1400
|
||||
#define ENABLE_L2_CACHE (1 << 0)
|
||||
#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
|
||||
|
|
|
@ -3253,6 +3253,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
|
|||
}
|
||||
|
||||
WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
|
||||
WREG32(SRBM_INT_CNTL, 0x1);
|
||||
WREG32(SRBM_INT_ACK, 0x1);
|
||||
|
||||
evergreen_fix_pci_max_read_req_size(rdev);
|
||||
|
||||
|
@ -4324,6 +4326,7 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
|
|||
tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
|
||||
WREG32(DMA_CNTL, tmp);
|
||||
WREG32(GRBM_INT_CNTL, 0);
|
||||
WREG32(SRBM_INT_CNTL, 0);
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
|
||||
if (rdev->num_crtc >= 4) {
|
||||
|
@ -5066,6 +5069,10 @@ restart_ih:
|
|||
DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
|
||||
break;
|
||||
}
|
||||
case 96:
|
||||
DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
|
||||
WREG32(SRBM_INT_ACK, 0x1);
|
||||
break;
|
||||
case 124: /* UVD */
|
||||
DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
|
||||
radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
|
||||
|
|
|
@ -1191,6 +1191,10 @@
|
|||
#define SOFT_RESET_REGBB (1 << 22)
|
||||
#define SOFT_RESET_ORB (1 << 23)
|
||||
|
||||
#define SRBM_READ_ERROR 0xE98
|
||||
#define SRBM_INT_CNTL 0xEA0
|
||||
#define SRBM_INT_ACK 0xEA8
|
||||
|
||||
/* display watermarks */
|
||||
#define DC_LB_MEMORY_SPLIT 0x6b0c
|
||||
#define PRIORITY_A_CNT 0x6b18
|
||||
|
|
|
@ -962,6 +962,8 @@ static void cayman_gpu_init(struct radeon_device *rdev)
|
|||
}
|
||||
|
||||
WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
|
||||
WREG32(SRBM_INT_CNTL, 0x1);
|
||||
WREG32(SRBM_INT_ACK, 0x1);
|
||||
|
||||
evergreen_fix_pci_max_read_req_size(rdev);
|
||||
|
||||
|
@ -1086,12 +1088,12 @@ static void cayman_gpu_init(struct radeon_device *rdev)
|
|||
|
||||
if ((rdev->config.cayman.max_backends_per_se == 1) &&
|
||||
(rdev->flags & RADEON_IS_IGP)) {
|
||||
if ((disabled_rb_mask & 3) == 1) {
|
||||
/* RB0 disabled, RB1 enabled */
|
||||
tmp = 0x11111111;
|
||||
} else {
|
||||
if ((disabled_rb_mask & 3) == 2) {
|
||||
/* RB1 disabled, RB0 enabled */
|
||||
tmp = 0x00000000;
|
||||
} else {
|
||||
/* RB0 disabled, RB1 enabled */
|
||||
tmp = 0x11111111;
|
||||
}
|
||||
} else {
|
||||
tmp = gb_addr_config & NUM_PIPES_MASK;
|
||||
|
|
|
@ -82,6 +82,10 @@
|
|||
#define SOFT_RESET_REGBB (1 << 22)
|
||||
#define SOFT_RESET_ORB (1 << 23)
|
||||
|
||||
#define SRBM_READ_ERROR 0xE98
|
||||
#define SRBM_INT_CNTL 0xEA0
|
||||
#define SRBM_INT_ACK 0xEA8
|
||||
|
||||
#define SRBM_STATUS2 0x0EC4
|
||||
#define DMA_BUSY (1 << 5)
|
||||
#define DMA1_BUSY (1 << 6)
|
||||
|
|
|
@ -188,7 +188,7 @@ u32 r600_dpm_get_vrefresh(struct radeon_device *rdev)
|
|||
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
|
||||
radeon_crtc = to_radeon_crtc(crtc);
|
||||
if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {
|
||||
vrefresh = radeon_crtc->hw_mode.vrefresh;
|
||||
vrefresh = drm_mode_vrefresh(&radeon_crtc->hw_mode);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -715,6 +715,7 @@ int radeon_cs_packet_parse(struct radeon_cs_parser *p,
|
|||
struct radeon_cs_chunk *ib_chunk = p->chunk_ib;
|
||||
struct radeon_device *rdev = p->rdev;
|
||||
uint32_t header;
|
||||
int ret = 0, i;
|
||||
|
||||
if (idx >= ib_chunk->length_dw) {
|
||||
DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
|
||||
|
@ -743,14 +744,25 @@ int radeon_cs_packet_parse(struct radeon_cs_parser *p,
|
|||
break;
|
||||
default:
|
||||
DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
|
||||
return -EINVAL;
|
||||
ret = -EINVAL;
|
||||
goto dump_ib;
|
||||
}
|
||||
if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
|
||||
DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
|
||||
pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
|
||||
return -EINVAL;
|
||||
ret = -EINVAL;
|
||||
goto dump_ib;
|
||||
}
|
||||
return 0;
|
||||
|
||||
dump_ib:
|
||||
for (i = 0; i < ib_chunk->length_dw; i++) {
|
||||
if (i == idx)
|
||||
printk("\t0x%08x <---\n", radeon_get_ib_value(p, i));
|
||||
else
|
||||
printk("\t0x%08x\n", radeon_get_ib_value(p, i));
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
@ -179,9 +179,12 @@ static void radeon_encoder_add_backlight(struct radeon_encoder *radeon_encoder,
|
|||
(rdev->pdev->subsystem_vendor == 0x1734) &&
|
||||
(rdev->pdev->subsystem_device == 0x1107))
|
||||
use_bl = false;
|
||||
/* Older PPC macs use on-GPU backlight controller */
|
||||
#ifndef CONFIG_PPC_PMAC
|
||||
/* disable native backlight control on older asics */
|
||||
else if (rdev->family < CHIP_R600)
|
||||
use_bl = false;
|
||||
#endif
|
||||
else
|
||||
use_bl = true;
|
||||
}
|
||||
|
|
|
@ -852,6 +852,12 @@ static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
|
|||
single_display = false;
|
||||
}
|
||||
|
||||
/* 120hz tends to be problematic even if they are under the
|
||||
* vblank limit.
|
||||
*/
|
||||
if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120))
|
||||
single_display = false;
|
||||
|
||||
/* certain older asics have a separare 3D performance state,
|
||||
* so try that first if the user selected performance
|
||||
*/
|
||||
|
|
|
@ -3162,6 +3162,8 @@ static void si_gpu_init(struct radeon_device *rdev)
|
|||
}
|
||||
|
||||
WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
|
||||
WREG32(SRBM_INT_CNTL, 1);
|
||||
WREG32(SRBM_INT_ACK, 1);
|
||||
|
||||
evergreen_fix_pci_max_read_req_size(rdev);
|
||||
|
||||
|
@ -4699,12 +4701,6 @@ int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
|
|||
switch (pkt.type) {
|
||||
case RADEON_PACKET_TYPE0:
|
||||
dev_err(rdev->dev, "Packet0 not allowed!\n");
|
||||
for (i = 0; i < ib->length_dw; i++) {
|
||||
if (i == idx)
|
||||
printk("\t0x%08x <---\n", ib->ptr[i]);
|
||||
else
|
||||
printk("\t0x%08x\n", ib->ptr[i]);
|
||||
}
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
case RADEON_PACKET_TYPE2:
|
||||
|
@ -4736,8 +4732,15 @@ int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
|
|||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
if (ret)
|
||||
if (ret) {
|
||||
for (i = 0; i < ib->length_dw; i++) {
|
||||
if (i == idx)
|
||||
printk("\t0x%08x <---\n", ib->ptr[i]);
|
||||
else
|
||||
printk("\t0x%08x\n", ib->ptr[i]);
|
||||
}
|
||||
break;
|
||||
}
|
||||
} while (idx < ib->length_dw);
|
||||
|
||||
return ret;
|
||||
|
@ -5910,6 +5913,7 @@ static void si_disable_interrupt_state(struct radeon_device *rdev)
|
|||
tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
|
||||
WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
|
||||
WREG32(GRBM_INT_CNTL, 0);
|
||||
WREG32(SRBM_INT_CNTL, 0);
|
||||
if (rdev->num_crtc >= 2) {
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
|
||||
|
@ -6609,6 +6613,10 @@ restart_ih:
|
|||
break;
|
||||
}
|
||||
break;
|
||||
case 96:
|
||||
DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
|
||||
WREG32(SRBM_INT_ACK, 0x1);
|
||||
break;
|
||||
case 124: /* UVD */
|
||||
DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
|
||||
radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
|
||||
|
|
|
@ -358,6 +358,10 @@
|
|||
#define CC_SYS_RB_BACKEND_DISABLE 0xe80
|
||||
#define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84
|
||||
|
||||
#define SRBM_READ_ERROR 0xE98
|
||||
#define SRBM_INT_CNTL 0xEA0
|
||||
#define SRBM_INT_ACK 0xEA8
|
||||
|
||||
#define SRBM_STATUS2 0x0EC4
|
||||
#define DMA_BUSY (1 << 5)
|
||||
#define DMA1_BUSY (1 << 6)
|
||||
|
|
|
@ -997,8 +997,10 @@ static void tegra_crtc_reset(struct drm_crtc *crtc)
|
|||
crtc->state = NULL;
|
||||
|
||||
state = kzalloc(sizeof(*state), GFP_KERNEL);
|
||||
if (state)
|
||||
if (state) {
|
||||
crtc->state = &state->base;
|
||||
crtc->state->crtc = crtc;
|
||||
}
|
||||
}
|
||||
|
||||
static struct drm_crtc_state *
|
||||
|
@ -1012,6 +1014,7 @@ tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
|
|||
return NULL;
|
||||
|
||||
copy->base.mode_changed = false;
|
||||
copy->base.active_changed = false;
|
||||
copy->base.planes_changed = false;
|
||||
copy->base.event = NULL;
|
||||
|
||||
|
@ -1227,9 +1230,6 @@ static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc)
|
|||
/* program display mode */
|
||||
tegra_dc_set_timings(dc, mode);
|
||||
|
||||
if (dc->soc->supports_border_color)
|
||||
tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
|
||||
|
||||
/* interlacing isn't supported yet, so disable it */
|
||||
if (dc->soc->supports_interlacing) {
|
||||
value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
|
||||
|
@ -1252,42 +1252,7 @@ static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc)
|
|||
|
||||
static void tegra_crtc_prepare(struct drm_crtc *crtc)
|
||||
{
|
||||
struct tegra_dc *dc = to_tegra_dc(crtc);
|
||||
unsigned int syncpt;
|
||||
unsigned long value;
|
||||
|
||||
drm_crtc_vblank_off(crtc);
|
||||
|
||||
if (dc->pipe)
|
||||
syncpt = SYNCPT_VBLANK1;
|
||||
else
|
||||
syncpt = SYNCPT_VBLANK0;
|
||||
|
||||
/* initialize display controller */
|
||||
tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
|
||||
tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
|
||||
|
||||
value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
|
||||
tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
|
||||
|
||||
value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
|
||||
WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
|
||||
tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
|
||||
|
||||
/* initialize timer */
|
||||
value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
|
||||
WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
|
||||
tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
|
||||
|
||||
value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
|
||||
WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
|
||||
tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
|
||||
|
||||
value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
|
||||
tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
|
||||
|
||||
value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
|
||||
tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
|
||||
}
|
||||
|
||||
static void tegra_crtc_commit(struct drm_crtc *crtc)
|
||||
|
@ -1664,6 +1629,8 @@ static int tegra_dc_init(struct host1x_client *client)
|
|||
struct tegra_drm *tegra = drm->dev_private;
|
||||
struct drm_plane *primary = NULL;
|
||||
struct drm_plane *cursor = NULL;
|
||||
unsigned int syncpt;
|
||||
u32 value;
|
||||
int err;
|
||||
|
||||
if (tegra->domain) {
|
||||
|
@ -1730,6 +1697,40 @@ static int tegra_dc_init(struct host1x_client *client)
|
|||
goto cleanup;
|
||||
}
|
||||
|
||||
/* initialize display controller */
|
||||
if (dc->pipe)
|
||||
syncpt = SYNCPT_VBLANK1;
|
||||
else
|
||||
syncpt = SYNCPT_VBLANK0;
|
||||
|
||||
tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
|
||||
tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
|
||||
|
||||
value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
|
||||
tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
|
||||
|
||||
value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
|
||||
WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
|
||||
tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
|
||||
|
||||
/* initialize timer */
|
||||
value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
|
||||
WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
|
||||
tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
|
||||
|
||||
value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
|
||||
WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
|
||||
tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
|
||||
|
||||
value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
|
||||
tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
|
||||
|
||||
value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
|
||||
tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
|
||||
|
||||
if (dc->soc->supports_border_color)
|
||||
tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
|
||||
|
||||
return 0;
|
||||
|
||||
cleanup:
|
||||
|
|
|
@ -851,6 +851,14 @@ static void tegra_hdmi_encoder_mode_set(struct drm_encoder *encoder,
|
|||
h_back_porch = mode->htotal - mode->hsync_end;
|
||||
h_front_porch = mode->hsync_start - mode->hdisplay;
|
||||
|
||||
err = clk_set_rate(hdmi->clk, pclk);
|
||||
if (err < 0) {
|
||||
dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n",
|
||||
err);
|
||||
}
|
||||
|
||||
DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk));
|
||||
|
||||
/* power up sequence */
|
||||
value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
|
||||
value &= ~SOR_PLL_PDBG;
|
||||
|
|
|
@ -1872,6 +1872,7 @@ static const struct hid_device_id hid_have_special_driver[] = {
|
|||
{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_SIDEWINDER_GV) },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_NE4K) },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_NE4K_JP) },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_NE7K) },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_LK6K) },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_PRESENTER_8K_USB) },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_DIGITAL_MEDIA_3K) },
|
||||
|
@ -1926,6 +1927,7 @@ static const struct hid_device_id hid_have_special_driver[] = {
|
|||
#endif
|
||||
#if IS_ENABLED(CONFIG_HID_SAITEK)
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_PS1000) },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_RAT7_OLD) },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_RAT7) },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_MMO7) },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_MADCATZ, USB_DEVICE_ID_MADCATZ_RAT9) },
|
||||
|
|
|
@ -654,6 +654,7 @@
|
|||
#define USB_DEVICE_ID_MS_LK6K 0x00f9
|
||||
#define USB_DEVICE_ID_MS_PRESENTER_8K_BT 0x0701
|
||||
#define USB_DEVICE_ID_MS_PRESENTER_8K_USB 0x0713
|
||||
#define USB_DEVICE_ID_MS_NE7K 0x071d
|
||||
#define USB_DEVICE_ID_MS_DIGITAL_MEDIA_3K 0x0730
|
||||
#define USB_DEVICE_ID_MS_COMFORT_MOUSE_4500 0x076c
|
||||
#define USB_DEVICE_ID_MS_SURFACE_PRO_2 0x0799
|
||||
|
@ -802,6 +803,7 @@
|
|||
#define USB_VENDOR_ID_SAITEK 0x06a3
|
||||
#define USB_DEVICE_ID_SAITEK_RUMBLEPAD 0xff17
|
||||
#define USB_DEVICE_ID_SAITEK_PS1000 0x0621
|
||||
#define USB_DEVICE_ID_SAITEK_RAT7_OLD 0x0ccb
|
||||
#define USB_DEVICE_ID_SAITEK_RAT7 0x0cd7
|
||||
#define USB_DEVICE_ID_SAITEK_MMO7 0x0cd0
|
||||
|
||||
|
|
|
@ -264,6 +264,8 @@ static const struct hid_device_id ms_devices[] = {
|
|||
.driver_data = MS_ERGONOMY },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_NE4K_JP),
|
||||
.driver_data = MS_ERGONOMY },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_NE7K),
|
||||
.driver_data = MS_ERGONOMY },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_LK6K),
|
||||
.driver_data = MS_ERGONOMY | MS_RDESC },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_PRESENTER_8K_USB),
|
||||
|
|
|
@ -177,6 +177,8 @@ static int saitek_event(struct hid_device *hdev, struct hid_field *field,
|
|||
static const struct hid_device_id saitek_devices[] = {
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_PS1000),
|
||||
.driver_data = SAITEK_FIX_PS1000 },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_RAT7_OLD),
|
||||
.driver_data = SAITEK_RELEASE_MODE_RAT7 },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_RAT7),
|
||||
.driver_data = SAITEK_RELEASE_MODE_RAT7 },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_MADCATZ, USB_DEVICE_ID_MADCATZ_RAT9),
|
||||
|
|
|
@ -135,8 +135,9 @@ static struct hid_sensor_hub_callbacks *sensor_hub_get_callback(
|
|||
{
|
||||
struct hid_sensor_hub_callbacks_list *callback;
|
||||
struct sensor_hub_data *pdata = hid_get_drvdata(hdev);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock(&pdata->dyn_callback_lock);
|
||||
spin_lock_irqsave(&pdata->dyn_callback_lock, flags);
|
||||
list_for_each_entry(callback, &pdata->dyn_callback_list, list)
|
||||
if (callback->usage_id == usage_id &&
|
||||
(collection_index >=
|
||||
|
@ -145,10 +146,11 @@ static struct hid_sensor_hub_callbacks *sensor_hub_get_callback(
|
|||
callback->hsdev->end_collection_index)) {
|
||||
*priv = callback->priv;
|
||||
*hsdev = callback->hsdev;
|
||||
spin_unlock(&pdata->dyn_callback_lock);
|
||||
spin_unlock_irqrestore(&pdata->dyn_callback_lock,
|
||||
flags);
|
||||
return callback->usage_callback;
|
||||
}
|
||||
spin_unlock(&pdata->dyn_callback_lock);
|
||||
spin_unlock_irqrestore(&pdata->dyn_callback_lock, flags);
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
|
|
@ -804,7 +804,7 @@ union sixaxis_output_report_01 {
|
|||
#define DS4_REPORT_0x81_SIZE 7
|
||||
#define SIXAXIS_REPORT_0xF2_SIZE 18
|
||||
|
||||
static spinlock_t sony_dev_list_lock;
|
||||
static DEFINE_SPINLOCK(sony_dev_list_lock);
|
||||
static LIST_HEAD(sony_device_list);
|
||||
static DEFINE_IDA(sony_device_id_allocator);
|
||||
|
||||
|
@ -1944,6 +1944,8 @@ static int sony_probe(struct hid_device *hdev, const struct hid_device_id *id)
|
|||
return -ENOMEM;
|
||||
}
|
||||
|
||||
spin_lock_init(&sc->lock);
|
||||
|
||||
sc->quirks = quirks;
|
||||
hid_set_drvdata(hdev, sc);
|
||||
sc->hdev = hdev;
|
||||
|
@ -2147,8 +2149,8 @@ static void __exit sony_exit(void)
|
|||
{
|
||||
dbg_hid("Sony:%s\n", __func__);
|
||||
|
||||
ida_destroy(&sony_device_id_allocator);
|
||||
hid_unregister_driver(&sony_driver);
|
||||
ida_destroy(&sony_device_id_allocator);
|
||||
}
|
||||
module_init(sony_init);
|
||||
module_exit(sony_exit);
|
||||
|
|
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