rdma/siw: main include file
Broken up commit to add the Soft iWarp RDMA driver. Signed-off-by: Bernard Metzler <bmt@zurich.ibm.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
This commit is contained in:
Bernard Metzler
Jason Gunthorpe
Родитель
0e935ae6af
Коммит
a531975279
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/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
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/* Authors: Bernard Metzler <bmt@zurich.ibm.com> */
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/* Copyright (c) 2008-2019, IBM Corporation */
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#ifndef _SIW_H
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#define _SIW_H
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#include <rdma/ib_verbs.h>
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#include <linux/socket.h>
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#include <linux/skbuff.h>
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#include <crypto/hash.h>
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#include <linux/crc32.h>
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#include <linux/crc32c.h>
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#include <rdma/siw-abi.h>
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#include "iwarp.h"
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#define SIW_VENDOR_ID 0x626d74 /* ascii 'bmt' for now */
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#define SIW_VENDORT_PART_ID 0
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#define SIW_MAX_QP (1024 * 100)
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#define SIW_MAX_QP_WR (1024 * 32)
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#define SIW_MAX_ORD_QP 128
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#define SIW_MAX_IRD_QP 128
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#define SIW_MAX_SGE_PBL 256 /* max num sge's for PBL */
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#define SIW_MAX_SGE_RD 1 /* iwarp limitation. we could relax */
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#define SIW_MAX_CQ (1024 * 100)
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#define SIW_MAX_CQE (SIW_MAX_QP_WR * 100)
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#define SIW_MAX_MR (SIW_MAX_QP * 10)
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#define SIW_MAX_PD SIW_MAX_QP
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#define SIW_MAX_MW 0 /* to be set if MW's are supported */
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#define SIW_MAX_FMR SIW_MAX_MR
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#define SIW_MAX_SRQ SIW_MAX_QP
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#define SIW_MAX_SRQ_WR (SIW_MAX_QP_WR * 10)
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#define SIW_MAX_CONTEXT SIW_MAX_PD
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/* Min number of bytes for using zero copy transmit */
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#define SENDPAGE_THRESH PAGE_SIZE
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/* Maximum number of frames which can be send in one SQ processing */
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#define SQ_USER_MAXBURST 100
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/* Maximum number of consecutive IRQ elements which get served
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* if SQ has pending work. Prevents starving local SQ processing
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* by serving peer Read Requests.
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*/
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#define SIW_IRQ_MAXBURST_SQ_ACTIVE 4
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struct siw_dev_cap {
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int max_qp;
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int max_qp_wr;
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int max_ord; /* max. outbound read queue depth */
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int max_ird; /* max. inbound read queue depth */
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int max_sge;
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int max_sge_rd;
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int max_cq;
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int max_cqe;
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int max_mr;
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int max_pd;
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int max_mw;
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int max_fmr;
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int max_srq;
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int max_srq_wr;
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int max_srq_sge;
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};
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struct siw_pd {
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struct ib_pd base_pd;
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};
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struct siw_device {
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struct ib_device base_dev;
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struct net_device *netdev;
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struct siw_dev_cap attrs;
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u32 vendor_part_id;
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int numa_node;
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/* physical port state (only one port per device) */
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enum ib_port_state state;
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spinlock_t lock;
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struct xarray qp_xa;
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struct xarray mem_xa;
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struct list_head cep_list;
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struct list_head qp_list;
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/* active objects statistics to enforce limits */
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atomic_t num_qp;
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atomic_t num_cq;
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atomic_t num_pd;
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atomic_t num_mr;
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atomic_t num_srq;
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atomic_t num_ctx;
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struct work_struct netdev_down;
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};
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struct siw_uobj {
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void *addr;
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u32 size;
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};
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struct siw_ucontext {
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struct ib_ucontext base_ucontext;
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struct siw_device *sdev;
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/* xarray of user mappable objects */
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struct xarray xa;
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u32 uobj_nextkey;
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};
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/*
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* The RDMA core does not define LOCAL_READ access, which is always
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* enabled implictely.
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*/
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#define IWARP_ACCESS_MASK \
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(IB_ACCESS_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE | \
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IB_ACCESS_REMOTE_READ)
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/*
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* siw presentation of user memory registered as source
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* or target of RDMA operations.
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*/
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struct siw_page_chunk {
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struct page **plist;
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};
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struct siw_umem {
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struct siw_page_chunk *page_chunk;
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int num_pages;
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bool writable;
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u64 fp_addr; /* First page base address */
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struct mm_struct *owning_mm;
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};
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struct siw_pble {
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u64 addr; /* Address of assigned user buffer */
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u64 size; /* Size of this entry */
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u64 pbl_off; /* Total offset from start of PBL */
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};
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struct siw_pbl {
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unsigned int num_buf;
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unsigned int max_buf;
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struct siw_pble pbe[1];
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};
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struct siw_mr;
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/*
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* Generic memory representation for registered siw memory.
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* Memory lookup always via higher 24 bit of STag (STag index).
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*/
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struct siw_mem {
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struct siw_device *sdev;
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struct kref ref;
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u64 va; /* VA of memory */
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u64 len; /* length of the memory buffer in bytes */
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u32 stag; /* iWarp memory access steering tag */
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u8 stag_valid; /* VALID or INVALID */
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u8 is_pbl; /* PBL or user space mem */
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u8 is_mw; /* Memory Region or Memory Window */
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enum ib_access_flags perms; /* local/remote READ & WRITE */
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union {
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struct siw_umem *umem;
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struct siw_pbl *pbl;
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void *mem_obj;
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};
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struct ib_pd *pd;
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};
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struct siw_mr {
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struct ib_mr base_mr;
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struct siw_mem *mem;
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struct rcu_head rcu;
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};
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/*
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* Error codes for local or remote
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* access to registered memory
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*/
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enum siw_access_state {
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E_ACCESS_OK,
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E_STAG_INVALID,
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E_BASE_BOUNDS,
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E_ACCESS_PERM,
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E_PD_MISMATCH
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};
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enum siw_wr_state {
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SIW_WR_IDLE,
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SIW_WR_QUEUED, /* processing has not started yet */
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SIW_WR_INPROGRESS /* initiated processing of the WR */
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};
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/* The WQE currently being processed (RX or TX) */
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struct siw_wqe {
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/* Copy of applications SQE or RQE */
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union {
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struct siw_sqe sqe;
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struct siw_rqe rqe;
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};
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struct siw_mem *mem[SIW_MAX_SGE]; /* per sge's resolved mem */
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enum siw_wr_state wr_status;
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enum siw_wc_status wc_status;
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u32 bytes; /* total bytes to process */
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u32 processed; /* bytes processed */
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};
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struct siw_cq {
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struct ib_cq base_cq;
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spinlock_t lock;
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u64 *notify;
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struct siw_cqe *queue;
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u32 cq_put;
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u32 cq_get;
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u32 num_cqe;
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bool kernel_verbs;
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u32 xa_cq_index; /* mmap information for CQE array */
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u32 id; /* For debugging only */
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};
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enum siw_qp_state {
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SIW_QP_STATE_IDLE,
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SIW_QP_STATE_RTR,
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SIW_QP_STATE_RTS,
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SIW_QP_STATE_CLOSING,
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SIW_QP_STATE_TERMINATE,
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SIW_QP_STATE_ERROR,
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SIW_QP_STATE_COUNT
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};
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enum siw_qp_flags {
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SIW_RDMA_BIND_ENABLED = (1 << 0),
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SIW_RDMA_WRITE_ENABLED = (1 << 1),
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SIW_RDMA_READ_ENABLED = (1 << 2),
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SIW_SIGNAL_ALL_WR = (1 << 3),
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SIW_MPA_CRC = (1 << 4),
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SIW_QP_IN_DESTROY = (1 << 5)
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};
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enum siw_qp_attr_mask {
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SIW_QP_ATTR_STATE = (1 << 0),
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SIW_QP_ATTR_ACCESS_FLAGS = (1 << 1),
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SIW_QP_ATTR_LLP_HANDLE = (1 << 2),
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SIW_QP_ATTR_ORD = (1 << 3),
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SIW_QP_ATTR_IRD = (1 << 4),
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SIW_QP_ATTR_SQ_SIZE = (1 << 5),
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SIW_QP_ATTR_RQ_SIZE = (1 << 6),
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SIW_QP_ATTR_MPA = (1 << 7)
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};
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struct siw_srq {
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struct ib_srq base_srq;
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spinlock_t lock;
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u32 max_sge;
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u32 limit; /* low watermark for async event */
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struct siw_rqe *recvq;
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u32 rq_put;
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u32 rq_get;
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u32 num_rqe; /* max # of wqe's allowed */
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u32 xa_srq_index; /* mmap information for SRQ array */
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char armed; /* inform user if limit hit */
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char kernel_verbs; /* '1' if kernel client */
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};
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struct siw_qp_attrs {
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enum siw_qp_state state;
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u32 sq_size;
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u32 rq_size;
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u32 orq_size;
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u32 irq_size;
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u32 sq_max_sges;
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u32 rq_max_sges;
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enum siw_qp_flags flags;
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struct socket *sk;
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};
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enum siw_tx_ctx {
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SIW_SEND_HDR, /* start or continue sending HDR */
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SIW_SEND_DATA, /* start or continue sending DDP payload */
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SIW_SEND_TRAILER, /* start or continue sending TRAILER */
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SIW_SEND_SHORT_FPDU/* send whole FPDU hdr|data|trailer at once */
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};
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enum siw_rx_state {
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SIW_GET_HDR, /* await new hdr or within hdr */
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SIW_GET_DATA_START, /* start of inbound DDP payload */
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SIW_GET_DATA_MORE, /* continuation of (misaligned) DDP payload */
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SIW_GET_TRAILER/* await new trailer or within trailer */
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};
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struct siw_rx_stream {
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struct sk_buff *skb;
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int skb_new; /* pending unread bytes in skb */
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int skb_offset; /* offset in skb */
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int skb_copied; /* processed bytes in skb */
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union iwarp_hdr hdr;
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struct mpa_trailer trailer;
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enum siw_rx_state state;
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/*
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* For each FPDU, main RX loop runs through 3 stages:
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* Receiving protocol headers, placing DDP payload and receiving
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* trailer information (CRC + possibly padding).
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* Next two variables keep state on receive status of the
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* current FPDU part (hdr, data, trailer).
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*/
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int fpdu_part_rcvd; /* bytes in pkt part copied */
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int fpdu_part_rem; /* bytes in pkt part not seen */
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/*
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* Next expected DDP MSN for each QN +
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* expected steering tag +
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* expected DDP tagget offset (all HBO)
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*/
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u32 ddp_msn[RDMAP_UNTAGGED_QN_COUNT];
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u32 ddp_stag;
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u64 ddp_to;
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u32 inval_stag; /* Stag to be invalidated */
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struct shash_desc *mpa_crc_hd;
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u8 rx_suspend : 1;
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u8 pad : 2; /* # of pad bytes expected */
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u8 rdmap_op : 4; /* opcode of current frame */
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};
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struct siw_rx_fpdu {
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/*
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* Local destination memory of inbound RDMA operation.
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* Valid, according to wqe->wr_status
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*/
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struct siw_wqe wqe_active;
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unsigned int pbl_idx; /* Index into current PBL */
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unsigned int sge_idx; /* current sge in rx */
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unsigned int sge_off; /* already rcvd in curr. sge */
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char first_ddp_seg; /* this is the first DDP seg */
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char more_ddp_segs; /* more DDP segs expected */
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u8 prev_rdmap_op : 4; /* opcode of prev frame */
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};
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/*
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* Shorthands for short packets w/o payload
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* to be transmitted more efficient.
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*/
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struct siw_send_pkt {
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struct iwarp_send send;
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__be32 crc;
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};
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struct siw_write_pkt {
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struct iwarp_rdma_write write;
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__be32 crc;
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};
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struct siw_rreq_pkt {
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struct iwarp_rdma_rreq rreq;
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__be32 crc;
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};
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struct siw_rresp_pkt {
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struct iwarp_rdma_rresp rresp;
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__be32 crc;
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};
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struct siw_iwarp_tx {
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union {
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union iwarp_hdr hdr;
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/* Generic part of FPDU header */
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struct iwarp_ctrl ctrl;
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struct iwarp_ctrl_untagged c_untagged;
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struct iwarp_ctrl_tagged c_tagged;
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/* FPDU headers */
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struct iwarp_rdma_write rwrite;
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struct iwarp_rdma_rreq rreq;
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struct iwarp_rdma_rresp rresp;
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struct iwarp_terminate terminate;
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struct iwarp_send send;
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struct iwarp_send_inv send_inv;
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/* complete short FPDUs */
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struct siw_send_pkt send_pkt;
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struct siw_write_pkt write_pkt;
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struct siw_rreq_pkt rreq_pkt;
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struct siw_rresp_pkt rresp_pkt;
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} pkt;
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struct mpa_trailer trailer;
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/* DDP MSN for untagged messages */
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u32 ddp_msn[RDMAP_UNTAGGED_QN_COUNT];
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enum siw_tx_ctx state;
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u16 ctrl_len; /* ddp+rdmap hdr */
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u16 ctrl_sent;
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int burst;
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int bytes_unsent; /* ddp payload bytes */
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struct shash_desc *mpa_crc_hd;
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u8 do_crc : 1; /* do crc for segment */
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u8 use_sendpage : 1; /* send w/o copy */
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u8 tx_suspend : 1; /* stop sending DDP segs. */
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u8 pad : 2; /* # pad in current fpdu */
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u8 orq_fence : 1; /* ORQ full or Send fenced */
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u8 in_syscall : 1; /* TX out of user context */
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u8 zcopy_tx : 1; /* Use TCP_SENDPAGE if possible */
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u8 gso_seg_limit; /* Maximum segments for GSO, 0 = unbound */
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u16 fpdu_len; /* len of FPDU to tx */
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unsigned int tcp_seglen; /* remaining tcp seg space */
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struct siw_wqe wqe_active;
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int pbl_idx; /* Index into current PBL */
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int sge_idx; /* current sge in tx */
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u32 sge_off; /* already sent in curr. sge */
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};
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struct siw_qp {
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struct siw_device *sdev;
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struct ib_qp *ib_qp;
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struct kref ref;
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u32 qp_num;
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struct list_head devq;
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int tx_cpu;
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bool kernel_verbs;
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struct siw_qp_attrs attrs;
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struct siw_cep *cep;
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struct rw_semaphore state_lock;
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struct ib_pd *pd;
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struct siw_cq *scq;
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struct siw_cq *rcq;
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struct siw_srq *srq;
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struct siw_iwarp_tx tx_ctx; /* Transmit context */
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spinlock_t sq_lock;
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struct siw_sqe *sendq; /* send queue element array */
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uint32_t sq_get; /* consumer index into sq array */
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uint32_t sq_put; /* kernel prod. index into sq array */
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struct llist_node tx_list;
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struct siw_sqe *orq; /* outbound read queue element array */
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spinlock_t orq_lock;
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uint32_t orq_get; /* consumer index into orq array */
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uint32_t orq_put; /* shared producer index for ORQ */
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struct siw_rx_stream rx_stream;
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struct siw_rx_fpdu *rx_fpdu;
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struct siw_rx_fpdu rx_tagged;
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struct siw_rx_fpdu rx_untagged;
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spinlock_t rq_lock;
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struct siw_rqe *recvq; /* recv queue element array */
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uint32_t rq_get; /* consumer index into rq array */
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uint32_t rq_put; /* kernel prod. index into rq array */
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struct siw_sqe *irq; /* inbound read queue element array */
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uint32_t irq_get; /* consumer index into irq array */
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uint32_t irq_put; /* producer index into irq array */
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int irq_burst;
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|
||||
struct { /* information to be carried in TERMINATE pkt, if valid */
|
||||
u8 valid;
|
||||
u8 in_tx;
|
||||
u8 layer : 4, etype : 4;
|
||||
u8 ecode;
|
||||
} term_info;
|
||||
u32 xa_sq_index; /* mmap information for SQE array */
|
||||
u32 xa_rq_index; /* mmap information for RQE array */
|
||||
struct rcu_head rcu;
|
||||
};
|
||||
|
||||
struct siw_base_qp {
|
||||
struct ib_qp base_qp;
|
||||
struct siw_qp *qp;
|
||||
};
|
||||
|
||||
/* helper macros */
|
||||
#define rx_qp(rx) container_of(rx, struct siw_qp, rx_stream)
|
||||
#define tx_qp(tx) container_of(tx, struct siw_qp, tx_ctx)
|
||||
#define tx_wqe(qp) (&(qp)->tx_ctx.wqe_active)
|
||||
#define rx_wqe(rctx) (&(rctx)->wqe_active)
|
||||
#define rx_mem(rctx) ((rctx)->wqe_active.mem[0])
|
||||
#define tx_type(wqe) ((wqe)->sqe.opcode)
|
||||
#define rx_type(wqe) ((wqe)->rqe.opcode)
|
||||
#define tx_flags(wqe) ((wqe)->sqe.flags)
|
||||
|
||||
struct iwarp_msg_info {
|
||||
int hdr_len;
|
||||
struct iwarp_ctrl ctrl;
|
||||
int (*rx_data)(struct siw_qp *qp);
|
||||
};
|
||||
|
||||
/* Global siw parameters. Currently set in siw_main.c */
|
||||
extern const bool zcopy_tx;
|
||||
extern const bool try_gso;
|
||||
extern const bool loopback_enabled;
|
||||
extern const bool mpa_crc_required;
|
||||
extern const bool mpa_crc_strict;
|
||||
extern const bool siw_tcp_nagle;
|
||||
extern u_char mpa_version;
|
||||
extern const bool peer_to_peer;
|
||||
extern struct task_struct *siw_tx_thread[];
|
||||
|
||||
extern struct crypto_shash *siw_crypto_shash;
|
||||
extern struct iwarp_msg_info iwarp_pktinfo[RDMAP_TERMINATE + 1];
|
||||
|
||||
/* QP general functions */
|
||||
int siw_qp_modify(struct siw_qp *qp, struct siw_qp_attrs *attr,
|
||||
enum siw_qp_attr_mask mask);
|
||||
int siw_qp_mpa_rts(struct siw_qp *qp, enum mpa_v2_ctrl ctrl);
|
||||
void siw_qp_llp_close(struct siw_qp *qp);
|
||||
void siw_qp_cm_drop(struct siw_qp *qp, int schedule);
|
||||
void siw_send_terminate(struct siw_qp *qp);
|
||||
|
||||
void siw_qp_get_ref(struct ib_qp *qp);
|
||||
void siw_qp_put_ref(struct ib_qp *qp);
|
||||
int siw_qp_add(struct siw_device *sdev, struct siw_qp *qp);
|
||||
void siw_free_qp(struct kref *ref);
|
||||
|
||||
void siw_init_terminate(struct siw_qp *qp, enum term_elayer layer,
|
||||
u8 etype, u8 ecode, int in_tx);
|
||||
enum ddp_ecode siw_tagged_error(enum siw_access_state state);
|
||||
enum rdmap_ecode siw_rdmap_error(enum siw_access_state state);
|
||||
|
||||
void siw_read_to_orq(struct siw_sqe *rreq, struct siw_sqe *sqe);
|
||||
int siw_sqe_complete(struct siw_qp *qp, struct siw_sqe *sqe, u32 bytes,
|
||||
enum siw_wc_status status);
|
||||
int siw_rqe_complete(struct siw_qp *qp, struct siw_rqe *rqe, u32 bytes,
|
||||
u32 inval_stag, enum siw_wc_status status);
|
||||
void siw_qp_llp_data_ready(struct sock *sk);
|
||||
void siw_qp_llp_write_space(struct sock *sk);
|
||||
|
||||
/* QP TX path functions */
|
||||
int siw_run_sq(void *arg);
|
||||
int siw_qp_sq_process(struct siw_qp *qp);
|
||||
int siw_sq_start(struct siw_qp *qp);
|
||||
int siw_activate_tx(struct siw_qp *qp);
|
||||
void siw_stop_tx_thread(int nr_cpu);
|
||||
int siw_get_tx_cpu(struct siw_device *sdev);
|
||||
void siw_put_tx_cpu(int cpu);
|
||||
|
||||
/* QP RX path functions */
|
||||
int siw_proc_send(struct siw_qp *qp);
|
||||
int siw_proc_rreq(struct siw_qp *qp);
|
||||
int siw_proc_rresp(struct siw_qp *qp);
|
||||
int siw_proc_write(struct siw_qp *qp);
|
||||
int siw_proc_terminate(struct siw_qp *qp);
|
||||
|
||||
int siw_tcp_rx_data(read_descriptor_t *rd_desc, struct sk_buff *skb,
|
||||
unsigned int off, size_t len);
|
||||
|
||||
static inline void set_rx_fpdu_context(struct siw_qp *qp, u8 opcode)
|
||||
{
|
||||
if (opcode == RDMAP_RDMA_WRITE || opcode == RDMAP_RDMA_READ_RESP)
|
||||
qp->rx_fpdu = &qp->rx_tagged;
|
||||
else
|
||||
qp->rx_fpdu = &qp->rx_untagged;
|
||||
|
||||
qp->rx_stream.rdmap_op = opcode;
|
||||
}
|
||||
|
||||
static inline struct siw_ucontext *to_siw_ctx(struct ib_ucontext *base_ctx)
|
||||
{
|
||||
return container_of(base_ctx, struct siw_ucontext, base_ucontext);
|
||||
}
|
||||
|
||||
static inline struct siw_base_qp *to_siw_base_qp(struct ib_qp *base_qp)
|
||||
{
|
||||
return container_of(base_qp, struct siw_base_qp, base_qp);
|
||||
}
|
||||
|
||||
static inline struct siw_qp *to_siw_qp(struct ib_qp *base_qp)
|
||||
{
|
||||
return to_siw_base_qp(base_qp)->qp;
|
||||
}
|
||||
|
||||
static inline struct siw_cq *to_siw_cq(struct ib_cq *base_cq)
|
||||
{
|
||||
return container_of(base_cq, struct siw_cq, base_cq);
|
||||
}
|
||||
|
||||
static inline struct siw_srq *to_siw_srq(struct ib_srq *base_srq)
|
||||
{
|
||||
return container_of(base_srq, struct siw_srq, base_srq);
|
||||
}
|
||||
|
||||
static inline struct siw_device *to_siw_dev(struct ib_device *base_dev)
|
||||
{
|
||||
return container_of(base_dev, struct siw_device, base_dev);
|
||||
}
|
||||
|
||||
static inline struct siw_mr *to_siw_mr(struct ib_mr *base_mr)
|
||||
{
|
||||
return container_of(base_mr, struct siw_mr, base_mr);
|
||||
}
|
||||
|
||||
static inline struct siw_qp *siw_qp_id2obj(struct siw_device *sdev, int id)
|
||||
{
|
||||
struct siw_qp *qp;
|
||||
|
||||
rcu_read_lock();
|
||||
qp = xa_load(&sdev->qp_xa, id);
|
||||
if (likely(qp && kref_get_unless_zero(&qp->ref))) {
|
||||
rcu_read_unlock();
|
||||
return qp;
|
||||
}
|
||||
rcu_read_unlock();
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline u32 qp_id(struct siw_qp *qp)
|
||||
{
|
||||
return qp->qp_num;
|
||||
}
|
||||
|
||||
static inline void siw_qp_get(struct siw_qp *qp)
|
||||
{
|
||||
kref_get(&qp->ref);
|
||||
}
|
||||
|
||||
static inline void siw_qp_put(struct siw_qp *qp)
|
||||
{
|
||||
kref_put(&qp->ref, siw_free_qp);
|
||||
}
|
||||
|
||||
static inline int siw_sq_empty(struct siw_qp *qp)
|
||||
{
|
||||
struct siw_sqe *sqe = &qp->sendq[qp->sq_get % qp->attrs.sq_size];
|
||||
|
||||
return READ_ONCE(sqe->flags) == 0;
|
||||
}
|
||||
|
||||
static inline struct siw_sqe *sq_get_next(struct siw_qp *qp)
|
||||
{
|
||||
struct siw_sqe *sqe = &qp->sendq[qp->sq_get % qp->attrs.sq_size];
|
||||
|
||||
if (READ_ONCE(sqe->flags) & SIW_WQE_VALID)
|
||||
return sqe;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline struct siw_sqe *orq_get_current(struct siw_qp *qp)
|
||||
{
|
||||
return &qp->orq[qp->orq_get % qp->attrs.orq_size];
|
||||
}
|
||||
|
||||
static inline struct siw_sqe *orq_get_tail(struct siw_qp *qp)
|
||||
{
|
||||
return &qp->orq[qp->orq_put % qp->attrs.orq_size];
|
||||
}
|
||||
|
||||
static inline struct siw_sqe *orq_get_free(struct siw_qp *qp)
|
||||
{
|
||||
struct siw_sqe *orq_e = orq_get_tail(qp);
|
||||
|
||||
if (orq_e && READ_ONCE(orq_e->flags) == 0)
|
||||
return orq_e;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline int siw_orq_empty(struct siw_qp *qp)
|
||||
{
|
||||
return qp->orq[qp->orq_get % qp->attrs.orq_size].flags == 0 ? 1 : 0;
|
||||
}
|
||||
|
||||
static inline struct siw_sqe *irq_alloc_free(struct siw_qp *qp)
|
||||
{
|
||||
struct siw_sqe *irq_e = &qp->irq[qp->irq_put % qp->attrs.irq_size];
|
||||
|
||||
if (READ_ONCE(irq_e->flags) == 0) {
|
||||
qp->irq_put++;
|
||||
return irq_e;
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline __wsum siw_csum_update(const void *buff, int len, __wsum sum)
|
||||
{
|
||||
return (__force __wsum)crc32c((__force __u32)sum, buff, len);
|
||||
}
|
||||
|
||||
static inline __wsum siw_csum_combine(__wsum csum, __wsum csum2, int offset,
|
||||
int len)
|
||||
{
|
||||
return (__force __wsum)__crc32c_le_combine((__force __u32)csum,
|
||||
(__force __u32)csum2, len);
|
||||
}
|
||||
|
||||
static inline void siw_crc_skb(struct siw_rx_stream *srx, unsigned int len)
|
||||
{
|
||||
const struct skb_checksum_ops siw_cs_ops = {
|
||||
.update = siw_csum_update,
|
||||
.combine = siw_csum_combine,
|
||||
};
|
||||
__wsum crc = *(u32 *)shash_desc_ctx(srx->mpa_crc_hd);
|
||||
|
||||
crc = __skb_checksum(srx->skb, srx->skb_offset, len, crc,
|
||||
&siw_cs_ops);
|
||||
*(u32 *)shash_desc_ctx(srx->mpa_crc_hd) = crc;
|
||||
}
|
||||
|
||||
#define siw_dbg(ibdev, fmt, ...) \
|
||||
ibdev_dbg(ibdev, "%s: " fmt, __func__, ##__VA_ARGS__)
|
||||
|
||||
#define siw_dbg_qp(qp, fmt, ...) \
|
||||
ibdev_dbg(&qp->sdev->base_dev, "QP[%u] %s: " fmt, qp_id(qp), __func__, \
|
||||
##__VA_ARGS__)
|
||||
|
||||
#define siw_dbg_cq(cq, fmt, ...) \
|
||||
ibdev_dbg(cq->base_cq.device, "CQ[%u] %s: " fmt, cq->id, __func__, \
|
||||
##__VA_ARGS__)
|
||||
|
||||
#define siw_dbg_pd(pd, fmt, ...) \
|
||||
ibdev_dbg(pd->device, "PD[%u] %s: " fmt, pd->res.id, __func__, \
|
||||
##__VA_ARGS__)
|
||||
|
||||
#define siw_dbg_mem(mem, fmt, ...) \
|
||||
ibdev_dbg(&mem->sdev->base_dev, \
|
||||
"MEM[0x%08x] %s: " fmt, mem->stag, __func__, ##__VA_ARGS__)
|
||||
|
||||
#define siw_dbg_cep(cep, fmt, ...) \
|
||||
ibdev_dbg(&cep->sdev->base_dev, "CEP[0x%p] %s: " fmt, \
|
||||
cep, __func__, ##__VA_ARGS__)
|
||||
|
||||
void siw_cq_flush(struct siw_cq *cq);
|
||||
void siw_sq_flush(struct siw_qp *qp);
|
||||
void siw_rq_flush(struct siw_qp *qp);
|
||||
int siw_reap_cqe(struct siw_cq *cq, struct ib_wc *wc);
|
||||
|
||||
#endif
|
||||
Загрузка…
Ссылка в новой задаче