wireless-drivers-next patches for 4.18
The first pull request for 4.18. As usual new features and bug fixes but nothing really special. I also merged wireless-drivers due to an iwlwifi patch dependency. Major changes: iwlwifi * implement Traffic Condition Monitor and use it for scan, BT coex and to detect when the AP doesn't support UAPSD properly * some more work for the 22000 family of devices; * introduce AMSDU rate control offload qtnfmac * DFS offload support rsi * roaming enhancements * increase max supported aggregation subframes * don't advertise 5 GHz support if the device doesn't support it brcmfmac * add support for BCM4366E chipset * add support for bcm43364 wireless chipset ath10k * enable temperature reads for QCA6174 and QCA9377 * add firmware memory dump support for QCA9984 * continue adding WCN3990 support via SNOC bus -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJa/TreAAoJEG4XJFUm622boV0IAI/tTu3obIdhdlnZJsjat/wH tmQX2rZl0g7kbthVU+WqPA1KgvK/HEX1SUIP0leARl6FDqxrBzE1G4P1fOY3JIaZ +T3UG9LgFM3hoXtJ1VRdvi8rTBVU67TTOrQCVD7AapGWfQwn6AXfy4ARUEqBjkrA SxDemdAwIks3miMU3EnsRlzLaI56R7l1mk0Xr30tM5Coq721AcWE6FBz6lqmFnTC 3vdDzpMRIiTt5zLICJZYgAB3akiaJEqHnIAv+y0sbXG1gHDhKcfEH674SM6FCB2N 3TP7EpzzxH/FYB0i+zOFg6wnAqUngLLnwkG/ciniVi75feb+gbaKqWHT8FNfx04= =rF/V -----END PGP SIGNATURE----- Merge tag 'wireless-drivers-next-for-davem-2018-05-17' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next Kalle Valo says: ==================== wireless-drivers-next patches for 4.18 The first pull request for 4.18. As usual new features and bug fixes but nothing really special. I also merged wireless-drivers due to an iwlwifi patch dependency. Major changes: iwlwifi * implement Traffic Condition Monitor and use it for scan, BT coex and to detect when the AP doesn't support UAPSD properly * some more work for the 22000 family of devices; * introduce AMSDU rate control offload qtnfmac * DFS offload support rsi * roaming enhancements * increase max supported aggregation subframes * don't advertise 5 GHz support if the device doesn't support it brcmfmac * add support for BCM4366E chipset * add support for bcm43364 wireless chipset ath10k * enable temperature reads for QCA6174 and QCA9377 * add firmware memory dump support for QCA9984 * continue adding WCN3990 support via SNOC bus ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Коммит
a564b659bb
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@ -4,6 +4,7 @@ Required properties:
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- compatible: Should be one of the following:
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* "qcom,ath10k"
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* "qcom,ipq4019-wifi"
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* "qcom,wcn3990-wifi"
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PCI based devices uses compatible string "qcom,ath10k" and takes calibration
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data along with board specific data via "qcom,ath10k-calibration-data".
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@ -18,8 +19,12 @@ In general, entry "qcom,ath10k-pre-calibration-data" and
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"qcom,ath10k-calibration-data" conflict with each other and only one
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can be provided per device.
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SNOC based devices (i.e. wcn3990) uses compatible string "qcom,wcn3990-wifi".
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Optional properties:
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- reg: Address and length of the register set for the device.
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- reg-names: Must include the list of following reg names,
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"membase"
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reseti.txt for details.
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- reset-names: Must include the list of following reset names,
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@ -49,6 +54,8 @@ Optional properties:
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hw versions.
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- qcom,ath10k-pre-calibration-data : pre calibration data as an array,
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the length can vary between hw versions.
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- <supply-name>-supply: handle to the regulator device tree node
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optional "supply-name" is "vdd-0.8-cx-mx".
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Example (to supply the calibration data alone):
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@ -119,3 +126,27 @@ wifi0: wifi@a000000 {
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qcom,msi_base = <0x40>;
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qcom,ath10k-pre-calibration-data = [ 01 02 03 ... ];
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};
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Example (to supply wcn3990 SoC wifi block details):
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wifi@18000000 {
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compatible = "qcom,wcn3990-wifi";
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reg = <0x18800000 0x800000>;
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reg-names = "membase";
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clocks = <&clock_gcc clk_aggre2_noc_clk>;
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clock-names = "smmu_aggre2_noc_clk"
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interrupts =
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<0 130 0 /* CE0 */ >,
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<0 131 0 /* CE1 */ >,
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<0 132 0 /* CE2 */ >,
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<0 133 0 /* CE3 */ >,
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<0 134 0 /* CE4 */ >,
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<0 135 0 /* CE5 */ >,
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<0 136 0 /* CE6 */ >,
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<0 137 0 /* CE7 */ >,
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<0 138 0 /* CE8 */ >,
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<0 139 0 /* CE9 */ >,
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<0 140 0 /* CE10 */ >,
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<0 141 0 /* CE11 */ >;
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vdd-0.8-cx-mx-supply = <&pm8998_l5>;
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};
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@ -4,12 +4,16 @@ config ATH10K
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select ATH_COMMON
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select CRC32
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select WANT_DEV_COREDUMP
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select ATH10K_CE
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---help---
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This module adds support for wireless adapters based on
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Atheros IEEE 802.11ac family of chipsets.
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If you choose to build a module, it'll be called ath10k.
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config ATH10K_CE
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bool
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config ATH10K_PCI
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tristate "Atheros ath10k PCI support"
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depends on ATH10K && PCI
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@ -36,6 +40,14 @@ config ATH10K_USB
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This module adds experimental support for USB bus. Currently
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work in progress and will not fully work.
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config ATH10K_SNOC
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tristate "Qualcomm ath10k SNOC support (EXPERIMENTAL)"
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depends on ATH10K && ARCH_QCOM
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---help---
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This module adds support for integrated WCN3990 chip connected
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to system NOC(SNOC). Currently work in progress and will not
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fully work.
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config ATH10K_DEBUG
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bool "Atheros ath10k debugging"
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depends on ATH10K
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|
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@ -22,10 +22,10 @@ ath10k_core-$(CONFIG_THERMAL) += thermal.o
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ath10k_core-$(CONFIG_MAC80211_DEBUGFS) += debugfs_sta.o
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ath10k_core-$(CONFIG_PM) += wow.o
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ath10k_core-$(CONFIG_DEV_COREDUMP) += coredump.o
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ath10k_core-$(CONFIG_ATH10K_CE) += ce.o
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obj-$(CONFIG_ATH10K_PCI) += ath10k_pci.o
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ath10k_pci-y += pci.o \
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ce.o
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ath10k_pci-y += pci.o
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ath10k_pci-$(CONFIG_ATH10K_AHB) += ahb.o
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|
@ -35,5 +35,8 @@ ath10k_sdio-y += sdio.o
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obj-$(CONFIG_ATH10K_USB) += ath10k_usb.o
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ath10k_usb-y += usb.o
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obj-$(CONFIG_ATH10K_SNOC) += ath10k_snoc.o
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ath10k_snoc-y += snoc.o
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# for tracing framework to find trace.h
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CFLAGS_trace.o := -I$(src)
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|
|
@ -1,6 +1,7 @@
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/*
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* Copyright (c) 2005-2011 Atheros Communications Inc.
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* Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
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* Copyright (c) 2018 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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|
@ -58,6 +59,74 @@
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* the buffer is sent/received.
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*/
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static inline u32 shadow_sr_wr_ind_addr(struct ath10k *ar,
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struct ath10k_ce_pipe *ce_state)
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{
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u32 ce_id = ce_state->id;
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u32 addr = 0;
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switch (ce_id) {
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case 0:
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addr = 0x00032000;
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break;
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case 3:
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addr = 0x0003200C;
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break;
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case 4:
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addr = 0x00032010;
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break;
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case 5:
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addr = 0x00032014;
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break;
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case 7:
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addr = 0x0003201C;
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break;
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default:
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ath10k_warn(ar, "invalid CE id: %d", ce_id);
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break;
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}
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return addr;
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}
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static inline u32 shadow_dst_wr_ind_addr(struct ath10k *ar,
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struct ath10k_ce_pipe *ce_state)
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{
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u32 ce_id = ce_state->id;
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u32 addr = 0;
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switch (ce_id) {
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case 1:
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addr = 0x00032034;
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break;
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case 2:
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addr = 0x00032038;
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break;
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case 5:
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addr = 0x00032044;
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break;
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case 7:
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addr = 0x0003204C;
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break;
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case 8:
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addr = 0x00032050;
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break;
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case 9:
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addr = 0x00032054;
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break;
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case 10:
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addr = 0x00032058;
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break;
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case 11:
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addr = 0x0003205C;
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break;
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default:
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ath10k_warn(ar, "invalid CE id: %d", ce_id);
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break;
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}
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return addr;
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}
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static inline unsigned int
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ath10k_set_ring_byte(unsigned int offset,
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struct ath10k_hw_ce_regs_addr_map *addr_map)
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@ -116,11 +185,46 @@ static inline u32 ath10k_ce_src_ring_write_index_get(struct ath10k *ar,
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ar->hw_ce_regs->sr_wr_index_addr);
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}
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static inline u32 ath10k_ce_src_ring_read_index_from_ddr(struct ath10k *ar,
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u32 ce_id)
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{
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struct ath10k_ce *ce = ath10k_ce_priv(ar);
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return ce->vaddr_rri[ce_id] & CE_DDR_RRI_MASK;
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}
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static inline u32 ath10k_ce_src_ring_read_index_get(struct ath10k *ar,
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u32 ce_ctrl_addr)
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{
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return ath10k_ce_read32(ar, ce_ctrl_addr +
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ar->hw_ce_regs->current_srri_addr);
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struct ath10k_ce *ce = ath10k_ce_priv(ar);
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u32 ce_id = COPY_ENGINE_ID(ce_ctrl_addr);
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struct ath10k_ce_pipe *ce_state = &ce->ce_states[ce_id];
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u32 index;
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if (ar->hw_params.rri_on_ddr &&
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(ce_state->attr_flags & CE_ATTR_DIS_INTR))
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index = ath10k_ce_src_ring_read_index_from_ddr(ar, ce_id);
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else
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index = ath10k_ce_read32(ar, ce_ctrl_addr +
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ar->hw_ce_regs->current_srri_addr);
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return index;
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}
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static inline void
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ath10k_ce_shadow_src_ring_write_index_set(struct ath10k *ar,
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struct ath10k_ce_pipe *ce_state,
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unsigned int value)
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{
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ath10k_ce_write32(ar, shadow_sr_wr_ind_addr(ar, ce_state), value);
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}
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static inline void
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ath10k_ce_shadow_dest_ring_write_index_set(struct ath10k *ar,
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struct ath10k_ce_pipe *ce_state,
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unsigned int value)
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{
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ath10k_ce_write32(ar, shadow_dst_wr_ind_addr(ar, ce_state), value);
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}
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static inline void ath10k_ce_src_ring_base_addr_set(struct ath10k *ar,
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@ -181,11 +285,31 @@ static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar,
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ath10k_set_ring_byte(n, ctrl_regs->dst_ring));
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}
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static inline
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u32 ath10k_ce_dest_ring_read_index_from_ddr(struct ath10k *ar, u32 ce_id)
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{
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struct ath10k_ce *ce = ath10k_ce_priv(ar);
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return (ce->vaddr_rri[ce_id] >> CE_DDR_DRRI_SHIFT) &
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CE_DDR_RRI_MASK;
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}
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static inline u32 ath10k_ce_dest_ring_read_index_get(struct ath10k *ar,
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u32 ce_ctrl_addr)
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{
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return ath10k_ce_read32(ar, ce_ctrl_addr +
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ar->hw_ce_regs->current_drri_addr);
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struct ath10k_ce *ce = ath10k_ce_priv(ar);
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u32 ce_id = COPY_ENGINE_ID(ce_ctrl_addr);
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struct ath10k_ce_pipe *ce_state = &ce->ce_states[ce_id];
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u32 index;
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if (ar->hw_params.rri_on_ddr &&
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(ce_state->attr_flags & CE_ATTR_DIS_INTR))
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index = ath10k_ce_dest_ring_read_index_from_ddr(ar, ce_id);
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else
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index = ath10k_ce_read32(ar, ce_ctrl_addr +
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ar->hw_ce_regs->current_drri_addr);
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return index;
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}
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static inline void ath10k_ce_dest_ring_base_addr_set(struct ath10k *ar,
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|
@ -376,8 +500,14 @@ static int _ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
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write_index = CE_RING_IDX_INCR(nentries_mask, write_index);
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|
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/* WORKAROUND */
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if (!(flags & CE_SEND_FLAG_GATHER))
|
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ath10k_ce_src_ring_write_index_set(ar, ctrl_addr, write_index);
|
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if (!(flags & CE_SEND_FLAG_GATHER)) {
|
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if (ar->hw_params.shadow_reg_support)
|
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ath10k_ce_shadow_src_ring_write_index_set(ar, ce_state,
|
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write_index);
|
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else
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ath10k_ce_src_ring_write_index_set(ar, ctrl_addr,
|
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write_index);
|
||||
}
|
||||
|
||||
src_ring->write_index = write_index;
|
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exit:
|
||||
|
@ -395,7 +525,7 @@ static int _ath10k_ce_send_nolock_64(struct ath10k_ce_pipe *ce_state,
|
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struct ath10k_ce_ring *src_ring = ce_state->src_ring;
|
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struct ce_desc_64 *desc, sdesc;
|
||||
unsigned int nentries_mask = src_ring->nentries_mask;
|
||||
unsigned int sw_index = src_ring->sw_index;
|
||||
unsigned int sw_index;
|
||||
unsigned int write_index = src_ring->write_index;
|
||||
u32 ctrl_addr = ce_state->ctrl_addr;
|
||||
__le32 *addr;
|
||||
|
@ -409,6 +539,11 @@ static int _ath10k_ce_send_nolock_64(struct ath10k_ce_pipe *ce_state,
|
|||
ath10k_warn(ar, "%s: send more we can (nbytes: %d, max: %d)\n",
|
||||
__func__, nbytes, ce_state->src_sz_max);
|
||||
|
||||
if (ar->hw_params.rri_on_ddr)
|
||||
sw_index = ath10k_ce_src_ring_read_index_from_ddr(ar, ce_state->id);
|
||||
else
|
||||
sw_index = src_ring->sw_index;
|
||||
|
||||
if (unlikely(CE_RING_DELTA(nentries_mask,
|
||||
write_index, sw_index - 1) <= 0)) {
|
||||
ret = -ENOSR;
|
||||
|
@ -464,6 +599,7 @@ int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
|
|||
return ce_state->ops->ce_send_nolock(ce_state, per_transfer_context,
|
||||
buffer, nbytes, transfer_id, flags);
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_ce_send_nolock);
|
||||
|
||||
void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe)
|
||||
{
|
||||
|
@ -491,6 +627,7 @@ void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe)
|
|||
|
||||
src_ring->per_transfer_context[src_ring->write_index] = NULL;
|
||||
}
|
||||
EXPORT_SYMBOL(__ath10k_ce_send_revert);
|
||||
|
||||
int ath10k_ce_send(struct ath10k_ce_pipe *ce_state,
|
||||
void *per_transfer_context,
|
||||
|
@ -510,6 +647,7 @@ int ath10k_ce_send(struct ath10k_ce_pipe *ce_state,
|
|||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_ce_send);
|
||||
|
||||
int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe)
|
||||
{
|
||||
|
@ -525,6 +663,7 @@ int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe)
|
|||
|
||||
return delta;
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_ce_num_free_src_entries);
|
||||
|
||||
int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe)
|
||||
{
|
||||
|
@ -539,6 +678,7 @@ int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe)
|
|||
|
||||
return CE_RING_DELTA(nentries_mask, write_index, sw_index - 1);
|
||||
}
|
||||
EXPORT_SYMBOL(__ath10k_ce_rx_num_free_bufs);
|
||||
|
||||
static int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx,
|
||||
dma_addr_t paddr)
|
||||
|
@ -615,13 +755,14 @@ void ath10k_ce_rx_update_write_idx(struct ath10k_ce_pipe *pipe, u32 nentries)
|
|||
/* Prevent CE ring stuck issue that will occur when ring is full.
|
||||
* Make sure that write index is 1 less than read index.
|
||||
*/
|
||||
if ((cur_write_idx + nentries) == dest_ring->sw_index)
|
||||
if (((cur_write_idx + nentries) & nentries_mask) == dest_ring->sw_index)
|
||||
nentries -= 1;
|
||||
|
||||
write_index = CE_RING_IDX_ADD(nentries_mask, write_index, nentries);
|
||||
ath10k_ce_dest_ring_write_index_set(ar, ctrl_addr, write_index);
|
||||
dest_ring->write_index = write_index;
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_ce_rx_update_write_idx);
|
||||
|
||||
int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx,
|
||||
dma_addr_t paddr)
|
||||
|
@ -636,6 +777,7 @@ int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx,
|
|||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_ce_rx_post_buf);
|
||||
|
||||
/*
|
||||
* Guts of ath10k_ce_completed_recv_next.
|
||||
|
@ -748,6 +890,7 @@ int ath10k_ce_completed_recv_next_nolock(struct ath10k_ce_pipe *ce_state,
|
|||
per_transfer_ctx,
|
||||
nbytesp);
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_ce_completed_recv_next_nolock);
|
||||
|
||||
int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state,
|
||||
void **per_transfer_contextp,
|
||||
|
@ -766,6 +909,7 @@ int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state,
|
|||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_ce_completed_recv_next);
|
||||
|
||||
static int _ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state,
|
||||
void **per_transfer_contextp,
|
||||
|
@ -882,6 +1026,7 @@ int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state,
|
|||
per_transfer_contextp,
|
||||
bufferp);
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_ce_revoke_recv_next);
|
||||
|
||||
/*
|
||||
* Guts of ath10k_ce_completed_send_next.
|
||||
|
@ -915,7 +1060,10 @@ int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state,
|
|||
src_ring->hw_index = read_index;
|
||||
}
|
||||
|
||||
read_index = src_ring->hw_index;
|
||||
if (ar->hw_params.rri_on_ddr)
|
||||
read_index = ath10k_ce_src_ring_read_index_get(ar, ctrl_addr);
|
||||
else
|
||||
read_index = src_ring->hw_index;
|
||||
|
||||
if (read_index == sw_index)
|
||||
return -EIO;
|
||||
|
@ -936,6 +1084,7 @@ int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state,
|
|||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_ce_completed_send_next_nolock);
|
||||
|
||||
static void ath10k_ce_extract_desc_data(struct ath10k *ar,
|
||||
struct ath10k_ce_ring *src_ring,
|
||||
|
@ -1025,6 +1174,7 @@ int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state,
|
|||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_ce_cancel_send_next);
|
||||
|
||||
int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state,
|
||||
void **per_transfer_contextp)
|
||||
|
@ -1040,6 +1190,7 @@ int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state,
|
|||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_ce_completed_send_next);
|
||||
|
||||
/*
|
||||
* Guts of interrupt handler for per-engine interrupts on a particular CE.
|
||||
|
@ -1078,6 +1229,7 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
|
|||
|
||||
spin_unlock_bh(&ce->ce_lock);
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_ce_per_engine_service);
|
||||
|
||||
/*
|
||||
* Handler for per-engine interrupts on ALL active CEs.
|
||||
|
@ -1102,6 +1254,7 @@ void ath10k_ce_per_engine_service_any(struct ath10k *ar)
|
|||
ath10k_ce_per_engine_service(ar, ce_id);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_ce_per_engine_service_any);
|
||||
|
||||
/*
|
||||
* Adjust interrupts for the copy complete handler.
|
||||
|
@ -1139,6 +1292,7 @@ int ath10k_ce_disable_interrupts(struct ath10k *ar)
|
|||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_ce_disable_interrupts);
|
||||
|
||||
void ath10k_ce_enable_interrupts(struct ath10k *ar)
|
||||
{
|
||||
|
@ -1154,6 +1308,7 @@ void ath10k_ce_enable_interrupts(struct ath10k *ar)
|
|||
ath10k_ce_per_engine_handler_adjust(ce_state);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_ce_enable_interrupts);
|
||||
|
||||
static int ath10k_ce_init_src_ring(struct ath10k *ar,
|
||||
unsigned int ce_id,
|
||||
|
@ -1234,6 +1389,22 @@ static int ath10k_ce_init_dest_ring(struct ath10k *ar,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int ath10k_ce_alloc_shadow_base(struct ath10k *ar,
|
||||
struct ath10k_ce_ring *src_ring,
|
||||
u32 nentries)
|
||||
{
|
||||
src_ring->shadow_base_unaligned = kcalloc(nentries,
|
||||
sizeof(struct ce_desc),
|
||||
GFP_KERNEL);
|
||||
if (!src_ring->shadow_base_unaligned)
|
||||
return -ENOMEM;
|
||||
|
||||
src_ring->shadow_base = (struct ce_desc *)
|
||||
PTR_ALIGN(src_ring->shadow_base_unaligned,
|
||||
CE_DESC_RING_ALIGN);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct ath10k_ce_ring *
|
||||
ath10k_ce_alloc_src_ring(struct ath10k *ar, unsigned int ce_id,
|
||||
const struct ce_attr *attr)
|
||||
|
@ -1241,6 +1412,7 @@ ath10k_ce_alloc_src_ring(struct ath10k *ar, unsigned int ce_id,
|
|||
struct ath10k_ce_ring *src_ring;
|
||||
u32 nentries = attr->src_nentries;
|
||||
dma_addr_t base_addr;
|
||||
int ret;
|
||||
|
||||
nentries = roundup_pow_of_two(nentries);
|
||||
|
||||
|
@ -1277,6 +1449,19 @@ ath10k_ce_alloc_src_ring(struct ath10k *ar, unsigned int ce_id,
|
|||
ALIGN(src_ring->base_addr_ce_space_unaligned,
|
||||
CE_DESC_RING_ALIGN);
|
||||
|
||||
if (ar->hw_params.shadow_reg_support) {
|
||||
ret = ath10k_ce_alloc_shadow_base(ar, src_ring, nentries);
|
||||
if (ret) {
|
||||
dma_free_coherent(ar->dev,
|
||||
(nentries * sizeof(struct ce_desc) +
|
||||
CE_DESC_RING_ALIGN),
|
||||
src_ring->base_addr_owner_space_unaligned,
|
||||
base_addr);
|
||||
kfree(src_ring);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
}
|
||||
|
||||
return src_ring;
|
||||
}
|
||||
|
||||
|
@ -1287,6 +1472,7 @@ ath10k_ce_alloc_src_ring_64(struct ath10k *ar, unsigned int ce_id,
|
|||
struct ath10k_ce_ring *src_ring;
|
||||
u32 nentries = attr->src_nentries;
|
||||
dma_addr_t base_addr;
|
||||
int ret;
|
||||
|
||||
nentries = roundup_pow_of_two(nentries);
|
||||
|
||||
|
@ -1322,6 +1508,19 @@ ath10k_ce_alloc_src_ring_64(struct ath10k *ar, unsigned int ce_id,
|
|||
ALIGN(src_ring->base_addr_ce_space_unaligned,
|
||||
CE_DESC_RING_ALIGN);
|
||||
|
||||
if (ar->hw_params.shadow_reg_support) {
|
||||
ret = ath10k_ce_alloc_shadow_base(ar, src_ring, nentries);
|
||||
if (ret) {
|
||||
dma_free_coherent(ar->dev,
|
||||
(nentries * sizeof(struct ce_desc) +
|
||||
CE_DESC_RING_ALIGN),
|
||||
src_ring->base_addr_owner_space_unaligned,
|
||||
base_addr);
|
||||
kfree(src_ring);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
}
|
||||
|
||||
return src_ring;
|
||||
}
|
||||
|
||||
|
@ -1454,6 +1653,7 @@ int ath10k_ce_init_pipe(struct ath10k *ar, unsigned int ce_id,
|
|||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_ce_init_pipe);
|
||||
|
||||
static void ath10k_ce_deinit_src_ring(struct ath10k *ar, unsigned int ce_id)
|
||||
{
|
||||
|
@ -1479,6 +1679,7 @@ void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id)
|
|||
ath10k_ce_deinit_src_ring(ar, ce_id);
|
||||
ath10k_ce_deinit_dest_ring(ar, ce_id);
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_ce_deinit_pipe);
|
||||
|
||||
static void _ath10k_ce_free_pipe(struct ath10k *ar, int ce_id)
|
||||
{
|
||||
|
@ -1486,6 +1687,8 @@ static void _ath10k_ce_free_pipe(struct ath10k *ar, int ce_id)
|
|||
struct ath10k_ce_pipe *ce_state = &ce->ce_states[ce_id];
|
||||
|
||||
if (ce_state->src_ring) {
|
||||
if (ar->hw_params.shadow_reg_support)
|
||||
kfree(ce_state->src_ring->shadow_base_unaligned);
|
||||
dma_free_coherent(ar->dev,
|
||||
(ce_state->src_ring->nentries *
|
||||
sizeof(struct ce_desc) +
|
||||
|
@ -1515,6 +1718,8 @@ static void _ath10k_ce_free_pipe_64(struct ath10k *ar, int ce_id)
|
|||
struct ath10k_ce_pipe *ce_state = &ce->ce_states[ce_id];
|
||||
|
||||
if (ce_state->src_ring) {
|
||||
if (ar->hw_params.shadow_reg_support)
|
||||
kfree(ce_state->src_ring->shadow_base_unaligned);
|
||||
dma_free_coherent(ar->dev,
|
||||
(ce_state->src_ring->nentries *
|
||||
sizeof(struct ce_desc_64) +
|
||||
|
@ -1545,6 +1750,7 @@ void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id)
|
|||
|
||||
ce_state->ops->ce_free_pipe(ar, ce_id);
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_ce_free_pipe);
|
||||
|
||||
void ath10k_ce_dump_registers(struct ath10k *ar,
|
||||
struct ath10k_fw_crash_data *crash_data)
|
||||
|
@ -1584,6 +1790,7 @@ void ath10k_ce_dump_registers(struct ath10k *ar,
|
|||
|
||||
spin_unlock_bh(&ce->ce_lock);
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_ce_dump_registers);
|
||||
|
||||
static const struct ath10k_ce_ops ce_ops = {
|
||||
.ce_alloc_src_ring = ath10k_ce_alloc_src_ring,
|
||||
|
@ -1680,3 +1887,47 @@ int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id,
|
|||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_ce_alloc_pipe);
|
||||
|
||||
void ath10k_ce_alloc_rri(struct ath10k *ar)
|
||||
{
|
||||
int i;
|
||||
u32 value;
|
||||
u32 ctrl1_regs;
|
||||
u32 ce_base_addr;
|
||||
struct ath10k_ce *ce = ath10k_ce_priv(ar);
|
||||
|
||||
ce->vaddr_rri = dma_alloc_coherent(ar->dev,
|
||||
(CE_COUNT * sizeof(u32)),
|
||||
&ce->paddr_rri, GFP_KERNEL);
|
||||
|
||||
if (!ce->vaddr_rri)
|
||||
return;
|
||||
|
||||
ath10k_ce_write32(ar, ar->hw_ce_regs->ce_rri_low,
|
||||
lower_32_bits(ce->paddr_rri));
|
||||
ath10k_ce_write32(ar, ar->hw_ce_regs->ce_rri_high,
|
||||
(upper_32_bits(ce->paddr_rri) &
|
||||
CE_DESC_FLAGS_GET_MASK));
|
||||
|
||||
for (i = 0; i < CE_COUNT; i++) {
|
||||
ctrl1_regs = ar->hw_ce_regs->ctrl1_regs->addr;
|
||||
ce_base_addr = ath10k_ce_base_address(ar, i);
|
||||
value = ath10k_ce_read32(ar, ce_base_addr + ctrl1_regs);
|
||||
value |= ar->hw_ce_regs->upd->mask;
|
||||
ath10k_ce_write32(ar, ce_base_addr + ctrl1_regs, value);
|
||||
}
|
||||
|
||||
memset(ce->vaddr_rri, 0, CE_COUNT * sizeof(u32));
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_ce_alloc_rri);
|
||||
|
||||
void ath10k_ce_free_rri(struct ath10k *ar)
|
||||
{
|
||||
struct ath10k_ce *ce = ath10k_ce_priv(ar);
|
||||
|
||||
dma_free_coherent(ar->dev, (CE_COUNT * sizeof(u32)),
|
||||
ce->vaddr_rri,
|
||||
ce->paddr_rri);
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_ce_free_rri);
|
||||
|
|
|
@ -1,6 +1,7 @@
|
|||
/*
|
||||
* Copyright (c) 2005-2011 Atheros Communications Inc.
|
||||
* Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
|
||||
* Copyright (c) 2018 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
|
@ -48,6 +49,9 @@ struct ath10k_ce_pipe;
|
|||
#define CE_DESC_FLAGS_META_DATA_MASK ar->hw_values->ce_desc_meta_data_mask
|
||||
#define CE_DESC_FLAGS_META_DATA_LSB ar->hw_values->ce_desc_meta_data_lsb
|
||||
|
||||
#define CE_DDR_RRI_MASK GENMASK(15, 0)
|
||||
#define CE_DDR_DRRI_SHIFT 16
|
||||
|
||||
struct ce_desc {
|
||||
__le32 addr;
|
||||
__le16 nbytes;
|
||||
|
@ -113,6 +117,9 @@ struct ath10k_ce_ring {
|
|||
/* CE address space */
|
||||
u32 base_addr_ce_space;
|
||||
|
||||
char *shadow_base_unaligned;
|
||||
struct ce_desc *shadow_base;
|
||||
|
||||
/* keep last */
|
||||
void *per_transfer_context[0];
|
||||
};
|
||||
|
@ -153,6 +160,8 @@ struct ath10k_ce {
|
|||
spinlock_t ce_lock;
|
||||
const struct ath10k_bus_ops *bus_ops;
|
||||
struct ath10k_ce_pipe ce_states[CE_COUNT_MAX];
|
||||
u32 *vaddr_rri;
|
||||
dma_addr_t paddr_rri;
|
||||
};
|
||||
|
||||
/*==================Send====================*/
|
||||
|
@ -261,6 +270,8 @@ int ath10k_ce_disable_interrupts(struct ath10k *ar);
|
|||
void ath10k_ce_enable_interrupts(struct ath10k *ar);
|
||||
void ath10k_ce_dump_registers(struct ath10k *ar,
|
||||
struct ath10k_fw_crash_data *crash_data);
|
||||
void ath10k_ce_alloc_rri(struct ath10k *ar);
|
||||
void ath10k_ce_free_rri(struct ath10k *ar);
|
||||
|
||||
/* ce_attr.flags values */
|
||||
/* Use NonSnooping PCIe accesses? */
|
||||
|
@ -327,6 +338,9 @@ static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id)
|
|||
return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id;
|
||||
}
|
||||
|
||||
#define COPY_ENGINE_ID(COPY_ENGINE_BASE_ADDRESS) (((COPY_ENGINE_BASE_ADDRESS) \
|
||||
- CE0_BASE_ADDRESS) / (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS))
|
||||
|
||||
#define CE_SRC_RING_TO_DESC(baddr, idx) \
|
||||
(&(((struct ce_desc *)baddr)[idx]))
|
||||
|
||||
|
@ -355,14 +369,18 @@ static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id)
|
|||
(((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \
|
||||
CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
|
||||
#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000
|
||||
#define CE_INTERRUPT_SUMMARY (GENMASK(CE_COUNT_MAX - 1, 0))
|
||||
|
||||
static inline u32 ath10k_ce_interrupt_summary(struct ath10k *ar)
|
||||
{
|
||||
struct ath10k_ce *ce = ath10k_ce_priv(ar);
|
||||
|
||||
return CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(
|
||||
ce->bus_ops->read32((ar), CE_WRAPPER_BASE_ADDRESS +
|
||||
CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS));
|
||||
if (!ar->hw_params.per_ce_irq)
|
||||
return CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(
|
||||
ce->bus_ops->read32((ar), CE_WRAPPER_BASE_ADDRESS +
|
||||
CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS));
|
||||
else
|
||||
return CE_INTERRUPT_SUMMARY;
|
||||
}
|
||||
|
||||
#endif /* _CE_H_ */
|
||||
|
|
|
@ -90,6 +90,8 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
|
|||
.num_wds_entries = 0x20,
|
||||
.target_64bit = false,
|
||||
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
|
||||
.shadow_reg_support = false,
|
||||
.rri_on_ddr = false,
|
||||
},
|
||||
{
|
||||
.id = QCA988X_HW_2_0_VERSION,
|
||||
|
@ -119,6 +121,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
|
|||
.num_wds_entries = 0x20,
|
||||
.target_64bit = false,
|
||||
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
|
||||
.per_ce_irq = false,
|
||||
.shadow_reg_support = false,
|
||||
.rri_on_ddr = false,
|
||||
},
|
||||
{
|
||||
.id = QCA9887_HW_1_0_VERSION,
|
||||
|
@ -148,6 +153,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
|
|||
.num_wds_entries = 0x20,
|
||||
.target_64bit = false,
|
||||
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
|
||||
.per_ce_irq = false,
|
||||
.shadow_reg_support = false,
|
||||
.rri_on_ddr = false,
|
||||
},
|
||||
{
|
||||
.id = QCA6174_HW_2_1_VERSION,
|
||||
|
@ -176,6 +184,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
|
|||
.num_wds_entries = 0x20,
|
||||
.target_64bit = false,
|
||||
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
|
||||
.per_ce_irq = false,
|
||||
.shadow_reg_support = false,
|
||||
.rri_on_ddr = false,
|
||||
},
|
||||
{
|
||||
.id = QCA6174_HW_2_1_VERSION,
|
||||
|
@ -204,6 +215,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
|
|||
.num_wds_entries = 0x20,
|
||||
.target_64bit = false,
|
||||
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
|
||||
.per_ce_irq = false,
|
||||
.shadow_reg_support = false,
|
||||
.rri_on_ddr = false,
|
||||
},
|
||||
{
|
||||
.id = QCA6174_HW_3_0_VERSION,
|
||||
|
@ -232,6 +246,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
|
|||
.num_wds_entries = 0x20,
|
||||
.target_64bit = false,
|
||||
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
|
||||
.per_ce_irq = false,
|
||||
.shadow_reg_support = false,
|
||||
.rri_on_ddr = false,
|
||||
},
|
||||
{
|
||||
.id = QCA6174_HW_3_2_VERSION,
|
||||
|
@ -263,6 +280,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
|
|||
.num_wds_entries = 0x20,
|
||||
.target_64bit = false,
|
||||
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
|
||||
.per_ce_irq = false,
|
||||
.shadow_reg_support = false,
|
||||
.rri_on_ddr = false,
|
||||
},
|
||||
{
|
||||
.id = QCA99X0_HW_2_0_DEV_VERSION,
|
||||
|
@ -297,6 +317,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
|
|||
.num_wds_entries = 0x20,
|
||||
.target_64bit = false,
|
||||
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
|
||||
.per_ce_irq = false,
|
||||
.shadow_reg_support = false,
|
||||
.rri_on_ddr = false,
|
||||
},
|
||||
{
|
||||
.id = QCA9984_HW_1_0_DEV_VERSION,
|
||||
|
@ -336,6 +359,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
|
|||
.num_wds_entries = 0x20,
|
||||
.target_64bit = false,
|
||||
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
|
||||
.per_ce_irq = false,
|
||||
.shadow_reg_support = false,
|
||||
.rri_on_ddr = false,
|
||||
},
|
||||
{
|
||||
.id = QCA9888_HW_2_0_DEV_VERSION,
|
||||
|
@ -374,6 +400,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
|
|||
.num_wds_entries = 0x20,
|
||||
.target_64bit = false,
|
||||
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
|
||||
.per_ce_irq = false,
|
||||
.shadow_reg_support = false,
|
||||
.rri_on_ddr = false,
|
||||
},
|
||||
{
|
||||
.id = QCA9377_HW_1_0_DEV_VERSION,
|
||||
|
@ -402,6 +431,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
|
|||
.num_wds_entries = 0x20,
|
||||
.target_64bit = false,
|
||||
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
|
||||
.per_ce_irq = false,
|
||||
.shadow_reg_support = false,
|
||||
.rri_on_ddr = false,
|
||||
},
|
||||
{
|
||||
.id = QCA9377_HW_1_1_DEV_VERSION,
|
||||
|
@ -432,6 +464,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
|
|||
.num_wds_entries = 0x20,
|
||||
.target_64bit = false,
|
||||
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
|
||||
.per_ce_irq = false,
|
||||
.shadow_reg_support = false,
|
||||
.rri_on_ddr = false,
|
||||
},
|
||||
{
|
||||
.id = QCA4019_HW_1_0_DEV_VERSION,
|
||||
|
@ -467,6 +502,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
|
|||
.num_wds_entries = 0x20,
|
||||
.target_64bit = false,
|
||||
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
|
||||
.per_ce_irq = false,
|
||||
.shadow_reg_support = false,
|
||||
.rri_on_ddr = false,
|
||||
},
|
||||
{
|
||||
.id = WCN3990_HW_1_0_DEV_VERSION,
|
||||
|
@ -487,6 +525,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
|
|||
.num_wds_entries = TARGET_HL_10_TLV_NUM_WDS_ENTRIES,
|
||||
.target_64bit = true,
|
||||
.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC,
|
||||
.per_ce_irq = true,
|
||||
.shadow_reg_support = true,
|
||||
.rri_on_ddr = true,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -1253,14 +1294,61 @@ out:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int ath10k_core_search_bd(struct ath10k *ar,
|
||||
const char *boardname,
|
||||
const u8 *data,
|
||||
size_t len)
|
||||
{
|
||||
size_t ie_len;
|
||||
struct ath10k_fw_ie *hdr;
|
||||
int ret = -ENOENT, ie_id;
|
||||
|
||||
while (len > sizeof(struct ath10k_fw_ie)) {
|
||||
hdr = (struct ath10k_fw_ie *)data;
|
||||
ie_id = le32_to_cpu(hdr->id);
|
||||
ie_len = le32_to_cpu(hdr->len);
|
||||
|
||||
len -= sizeof(*hdr);
|
||||
data = hdr->data;
|
||||
|
||||
if (len < ALIGN(ie_len, 4)) {
|
||||
ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n",
|
||||
ie_id, ie_len, len);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (ie_id) {
|
||||
case ATH10K_BD_IE_BOARD:
|
||||
ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len,
|
||||
boardname);
|
||||
if (ret == -ENOENT)
|
||||
/* no match found, continue */
|
||||
break;
|
||||
|
||||
/* either found or error, so stop searching */
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* jump over the padding */
|
||||
ie_len = ALIGN(ie_len, 4);
|
||||
|
||||
len -= ie_len;
|
||||
data += ie_len;
|
||||
}
|
||||
|
||||
out:
|
||||
/* return result of parse_bd_ie_board() or -ENOENT */
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar,
|
||||
const char *boardname,
|
||||
const char *fallback_boardname,
|
||||
const char *filename)
|
||||
{
|
||||
size_t len, magic_len, ie_len;
|
||||
struct ath10k_fw_ie *hdr;
|
||||
size_t len, magic_len;
|
||||
const u8 *data;
|
||||
int ret, ie_id;
|
||||
int ret;
|
||||
|
||||
ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
|
||||
ar->hw_params.fw.dir,
|
||||
|
@ -1298,69 +1386,23 @@ static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar,
|
|||
data += magic_len;
|
||||
len -= magic_len;
|
||||
|
||||
while (len > sizeof(struct ath10k_fw_ie)) {
|
||||
hdr = (struct ath10k_fw_ie *)data;
|
||||
ie_id = le32_to_cpu(hdr->id);
|
||||
ie_len = le32_to_cpu(hdr->len);
|
||||
/* attempt to find boardname in the IE list */
|
||||
ret = ath10k_core_search_bd(ar, boardname, data, len);
|
||||
|
||||
len -= sizeof(*hdr);
|
||||
data = hdr->data;
|
||||
/* if we didn't find it and have a fallback name, try that */
|
||||
if (ret == -ENOENT && fallback_boardname)
|
||||
ret = ath10k_core_search_bd(ar, fallback_boardname, data, len);
|
||||
|
||||
if (len < ALIGN(ie_len, 4)) {
|
||||
ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n",
|
||||
ie_id, ie_len, len);
|
||||
ret = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
switch (ie_id) {
|
||||
case ATH10K_BD_IE_BOARD:
|
||||
ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len,
|
||||
boardname);
|
||||
if (ret == -ENOENT && ar->id.bdf_ext[0] != '\0') {
|
||||
/* try default bdf if variant was not found */
|
||||
char *s, *v = ",variant=";
|
||||
char boardname2[100];
|
||||
|
||||
strlcpy(boardname2, boardname,
|
||||
sizeof(boardname2));
|
||||
|
||||
s = strstr(boardname2, v);
|
||||
if (s)
|
||||
*s = '\0'; /* strip ",variant=%s" */
|
||||
|
||||
ret = ath10k_core_parse_bd_ie_board(ar, data,
|
||||
ie_len,
|
||||
boardname2);
|
||||
}
|
||||
|
||||
if (ret == -ENOENT)
|
||||
/* no match found, continue */
|
||||
break;
|
||||
else if (ret)
|
||||
/* there was an error, bail out */
|
||||
goto err;
|
||||
|
||||
/* board data found */
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* jump over the padding */
|
||||
ie_len = ALIGN(ie_len, 4);
|
||||
|
||||
len -= ie_len;
|
||||
data += ie_len;
|
||||
}
|
||||
|
||||
out:
|
||||
if (!ar->normal_mode_fw.board_data || !ar->normal_mode_fw.board_len) {
|
||||
if (ret == -ENOENT) {
|
||||
ath10k_err(ar,
|
||||
"failed to fetch board data for %s from %s/%s\n",
|
||||
boardname, ar->hw_params.fw.dir, filename);
|
||||
ret = -ENODATA;
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
|
@ -1369,12 +1411,12 @@ err:
|
|||
}
|
||||
|
||||
static int ath10k_core_create_board_name(struct ath10k *ar, char *name,
|
||||
size_t name_len)
|
||||
size_t name_len, bool with_variant)
|
||||
{
|
||||
/* strlen(',variant=') + strlen(ar->id.bdf_ext) */
|
||||
char variant[9 + ATH10K_SMBIOS_BDF_EXT_STR_LENGTH] = { 0 };
|
||||
|
||||
if (ar->id.bdf_ext[0] != '\0')
|
||||
if (with_variant && ar->id.bdf_ext[0] != '\0')
|
||||
scnprintf(variant, sizeof(variant), ",variant=%s",
|
||||
ar->id.bdf_ext);
|
||||
|
||||
|
@ -1400,17 +1442,26 @@ out:
|
|||
|
||||
static int ath10k_core_fetch_board_file(struct ath10k *ar)
|
||||
{
|
||||
char boardname[100];
|
||||
char boardname[100], fallback_boardname[100];
|
||||
int ret;
|
||||
|
||||
ret = ath10k_core_create_board_name(ar, boardname, sizeof(boardname));
|
||||
ret = ath10k_core_create_board_name(ar, boardname,
|
||||
sizeof(boardname), true);
|
||||
if (ret) {
|
||||
ath10k_err(ar, "failed to create board name: %d", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = ath10k_core_create_board_name(ar, fallback_boardname,
|
||||
sizeof(boardname), false);
|
||||
if (ret) {
|
||||
ath10k_err(ar, "failed to create fallback board name: %d", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ar->bd_api = 2;
|
||||
ret = ath10k_core_fetch_board_data_api_n(ar, boardname,
|
||||
fallback_boardname,
|
||||
ATH10K_BOARD_API2_FILE);
|
||||
if (!ret)
|
||||
goto success;
|
||||
|
@ -2472,6 +2523,14 @@ static int ath10k_core_probe_fw(struct ath10k *ar)
|
|||
ar->hw->wiphy->hw_version = target_info.version;
|
||||
break;
|
||||
case ATH10K_BUS_SNOC:
|
||||
memset(&target_info, 0, sizeof(target_info));
|
||||
ret = ath10k_hif_get_target_info(ar, &target_info);
|
||||
if (ret) {
|
||||
ath10k_err(ar, "could not get target info (%d)\n", ret);
|
||||
goto err_power_down;
|
||||
}
|
||||
ar->target_version = target_info.version;
|
||||
ar->hw->wiphy->hw_version = target_info.version;
|
||||
break;
|
||||
default:
|
||||
ath10k_err(ar, "incorrect hif bus type: %d\n", ar->hif.bus);
|
||||
|
|
|
@ -52,6 +52,8 @@
|
|||
/* Antenna noise floor */
|
||||
#define ATH10K_DEFAULT_NOISE_FLOOR -95
|
||||
|
||||
#define ATH10K_INVALID_RSSI 128
|
||||
|
||||
#define ATH10K_MAX_NUM_MGMT_PENDING 128
|
||||
|
||||
/* number of failed packets (20 packets with 16 sw reties each) */
|
||||
|
|
|
@ -20,13 +20,14 @@
|
|||
|
||||
#include <linux/kernel.h>
|
||||
#include "core.h"
|
||||
#include "bmi.h"
|
||||
#include "debug.h"
|
||||
|
||||
struct ath10k_hif_sg_item {
|
||||
u16 transfer_id;
|
||||
void *transfer_context; /* NULL = tx completion callback not called */
|
||||
void *vaddr; /* for debugging mostly */
|
||||
u32 paddr;
|
||||
dma_addr_t paddr;
|
||||
u16 len;
|
||||
};
|
||||
|
||||
|
@ -93,6 +94,9 @@ struct ath10k_hif_ops {
|
|||
/* fetch calibration data from target eeprom */
|
||||
int (*fetch_cal_eeprom)(struct ath10k *ar, void **data,
|
||||
size_t *data_len);
|
||||
|
||||
int (*get_target_info)(struct ath10k *ar,
|
||||
struct bmi_target_info *target_info);
|
||||
};
|
||||
|
||||
static inline int ath10k_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
|
||||
|
@ -218,4 +222,13 @@ static inline int ath10k_hif_fetch_cal_eeprom(struct ath10k *ar,
|
|||
return ar->hif.ops->fetch_cal_eeprom(ar, data, data_len);
|
||||
}
|
||||
|
||||
static inline int ath10k_hif_get_target_info(struct ath10k *ar,
|
||||
struct bmi_target_info *tgt_info)
|
||||
{
|
||||
if (!ar->hif.ops->get_target_info)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
return ar->hif.ops->get_target_info(ar, tgt_info);
|
||||
}
|
||||
|
||||
#endif /* _HIF_H_ */
|
||||
|
|
|
@ -542,8 +542,14 @@ static const char *htc_service_name(enum ath10k_htc_svc_id id)
|
|||
return "NMI Data";
|
||||
case ATH10K_HTC_SVC_ID_HTT_DATA_MSG:
|
||||
return "HTT Data";
|
||||
case ATH10K_HTC_SVC_ID_HTT_DATA2_MSG:
|
||||
return "HTT Data";
|
||||
case ATH10K_HTC_SVC_ID_HTT_DATA3_MSG:
|
||||
return "HTT Data";
|
||||
case ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS:
|
||||
return "RAW";
|
||||
case ATH10K_HTC_SVC_ID_HTT_LOG_MSG:
|
||||
return "PKTLOG";
|
||||
}
|
||||
|
||||
return "Unknown";
|
||||
|
|
|
@ -248,6 +248,7 @@ enum ath10k_htc_svc_gid {
|
|||
ATH10K_HTC_SVC_GRP_WMI = 1,
|
||||
ATH10K_HTC_SVC_GRP_NMI = 2,
|
||||
ATH10K_HTC_SVC_GRP_HTT = 3,
|
||||
ATH10K_LOG_SERVICE_GROUP = 6,
|
||||
|
||||
ATH10K_HTC_SVC_GRP_TEST = 254,
|
||||
ATH10K_HTC_SVC_GRP_LAST = 255,
|
||||
|
@ -273,6 +274,9 @@ enum ath10k_htc_svc_id {
|
|||
|
||||
ATH10K_HTC_SVC_ID_HTT_DATA_MSG = SVC(ATH10K_HTC_SVC_GRP_HTT, 0),
|
||||
|
||||
ATH10K_HTC_SVC_ID_HTT_DATA2_MSG = SVC(ATH10K_HTC_SVC_GRP_HTT, 1),
|
||||
ATH10K_HTC_SVC_ID_HTT_DATA3_MSG = SVC(ATH10K_HTC_SVC_GRP_HTT, 2),
|
||||
ATH10K_HTC_SVC_ID_HTT_LOG_MSG = SVC(ATH10K_LOG_SERVICE_GROUP, 0),
|
||||
/* raw stream service (i.e. flash, tcmd, calibration apps) */
|
||||
ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS = SVC(ATH10K_HTC_SVC_GRP_TEST, 0),
|
||||
};
|
||||
|
|
|
@ -257,11 +257,11 @@ int ath10k_htt_setup(struct ath10k_htt *htt)
|
|||
return status;
|
||||
}
|
||||
|
||||
status = htt->tx_ops->htt_send_frag_desc_bank_cfg(htt);
|
||||
status = ath10k_htt_send_frag_desc_bank_cfg(htt);
|
||||
if (status)
|
||||
return status;
|
||||
|
||||
status = htt->tx_ops->htt_send_rx_ring_cfg(htt);
|
||||
status = ath10k_htt_send_rx_ring_cfg(htt);
|
||||
if (status) {
|
||||
ath10k_warn(ar, "failed to setup rx ring: %d\n",
|
||||
status);
|
||||
|
|
|
@ -1,6 +1,7 @@
|
|||
/*
|
||||
* Copyright (c) 2005-2011 Atheros Communications Inc.
|
||||
* Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
|
||||
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
|
@ -127,6 +128,19 @@ struct htt_msdu_ext_desc_64 {
|
|||
| HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE \
|
||||
| HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE)
|
||||
|
||||
#define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 BIT(16)
|
||||
#define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 BIT(17)
|
||||
#define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 BIT(18)
|
||||
#define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 BIT(19)
|
||||
#define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64 BIT(20)
|
||||
#define HTT_MSDU_EXT_DESC_FLAG_PARTIAL_CSUM_ENABLE_64 BIT(21)
|
||||
|
||||
#define HTT_MSDU_CHECKSUM_ENABLE_64 (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 \
|
||||
| HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 \
|
||||
| HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 \
|
||||
| HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 \
|
||||
| HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64)
|
||||
|
||||
enum htt_data_tx_desc_flags0 {
|
||||
HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0,
|
||||
HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1,
|
||||
|
@ -533,12 +547,18 @@ struct htt_ver_resp {
|
|||
u8 rsvd0;
|
||||
} __packed;
|
||||
|
||||
#define HTT_MGMT_TX_CMPL_FLAG_ACK_RSSI BIT(0)
|
||||
|
||||
#define HTT_MGMT_TX_CMPL_INFO_ACK_RSSI_MASK GENMASK(7, 0)
|
||||
|
||||
struct htt_mgmt_tx_completion {
|
||||
u8 rsvd0;
|
||||
u8 rsvd1;
|
||||
u8 rsvd2;
|
||||
u8 flags;
|
||||
__le32 desc_id;
|
||||
__le32 status;
|
||||
__le32 ppdu_id;
|
||||
__le32 info;
|
||||
} __packed;
|
||||
|
||||
#define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x1F)
|
||||
|
@ -1648,6 +1668,7 @@ struct htt_resp {
|
|||
struct htt_tx_done {
|
||||
u16 msdu_id;
|
||||
u16 status;
|
||||
u8 ack_rssi;
|
||||
};
|
||||
|
||||
enum htt_tx_compl_state {
|
||||
|
@ -1848,6 +1869,57 @@ struct ath10k_htt_tx_ops {
|
|||
void (*htt_free_txbuff)(struct ath10k_htt *htt);
|
||||
};
|
||||
|
||||
static inline int ath10k_htt_send_rx_ring_cfg(struct ath10k_htt *htt)
|
||||
{
|
||||
if (!htt->tx_ops->htt_send_rx_ring_cfg)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
return htt->tx_ops->htt_send_rx_ring_cfg(htt);
|
||||
}
|
||||
|
||||
static inline int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt)
|
||||
{
|
||||
if (!htt->tx_ops->htt_send_frag_desc_bank_cfg)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
return htt->tx_ops->htt_send_frag_desc_bank_cfg(htt);
|
||||
}
|
||||
|
||||
static inline int ath10k_htt_alloc_frag_desc(struct ath10k_htt *htt)
|
||||
{
|
||||
if (!htt->tx_ops->htt_alloc_frag_desc)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
return htt->tx_ops->htt_alloc_frag_desc(htt);
|
||||
}
|
||||
|
||||
static inline void ath10k_htt_free_frag_desc(struct ath10k_htt *htt)
|
||||
{
|
||||
if (htt->tx_ops->htt_free_frag_desc)
|
||||
htt->tx_ops->htt_free_frag_desc(htt);
|
||||
}
|
||||
|
||||
static inline int ath10k_htt_tx(struct ath10k_htt *htt,
|
||||
enum ath10k_hw_txrx_mode txmode,
|
||||
struct sk_buff *msdu)
|
||||
{
|
||||
return htt->tx_ops->htt_tx(htt, txmode, msdu);
|
||||
}
|
||||
|
||||
static inline int ath10k_htt_alloc_txbuff(struct ath10k_htt *htt)
|
||||
{
|
||||
if (!htt->tx_ops->htt_alloc_txbuff)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
return htt->tx_ops->htt_alloc_txbuff(htt);
|
||||
}
|
||||
|
||||
static inline void ath10k_htt_free_txbuff(struct ath10k_htt *htt)
|
||||
{
|
||||
if (htt->tx_ops->htt_free_txbuff)
|
||||
htt->tx_ops->htt_free_txbuff(htt);
|
||||
}
|
||||
|
||||
struct ath10k_htt_rx_ops {
|
||||
size_t (*htt_get_rx_ring_size)(struct ath10k_htt *htt);
|
||||
void (*htt_config_paddrs_ring)(struct ath10k_htt *htt, void *vaddr);
|
||||
|
@ -1857,6 +1929,43 @@ struct ath10k_htt_rx_ops {
|
|||
void (*htt_reset_paddrs_ring)(struct ath10k_htt *htt, int idx);
|
||||
};
|
||||
|
||||
static inline size_t ath10k_htt_get_rx_ring_size(struct ath10k_htt *htt)
|
||||
{
|
||||
if (!htt->rx_ops->htt_get_rx_ring_size)
|
||||
return 0;
|
||||
|
||||
return htt->rx_ops->htt_get_rx_ring_size(htt);
|
||||
}
|
||||
|
||||
static inline void ath10k_htt_config_paddrs_ring(struct ath10k_htt *htt,
|
||||
void *vaddr)
|
||||
{
|
||||
if (htt->rx_ops->htt_config_paddrs_ring)
|
||||
htt->rx_ops->htt_config_paddrs_ring(htt, vaddr);
|
||||
}
|
||||
|
||||
static inline void ath10k_htt_set_paddrs_ring(struct ath10k_htt *htt,
|
||||
dma_addr_t paddr,
|
||||
int idx)
|
||||
{
|
||||
if (htt->rx_ops->htt_set_paddrs_ring)
|
||||
htt->rx_ops->htt_set_paddrs_ring(htt, paddr, idx);
|
||||
}
|
||||
|
||||
static inline void *ath10k_htt_get_vaddr_ring(struct ath10k_htt *htt)
|
||||
{
|
||||
if (!htt->rx_ops->htt_get_vaddr_ring)
|
||||
return NULL;
|
||||
|
||||
return htt->rx_ops->htt_get_vaddr_ring(htt);
|
||||
}
|
||||
|
||||
static inline void ath10k_htt_reset_paddrs_ring(struct ath10k_htt *htt, int idx)
|
||||
{
|
||||
if (htt->rx_ops->htt_reset_paddrs_ring)
|
||||
htt->rx_ops->htt_reset_paddrs_ring(htt, idx);
|
||||
}
|
||||
|
||||
#define RX_HTT_HDR_STATUS_LEN 64
|
||||
|
||||
/* This structure layout is programmed via rx ring setup
|
||||
|
|
|
@ -25,6 +25,7 @@
|
|||
#include "mac.h"
|
||||
|
||||
#include <linux/log2.h>
|
||||
#include <linux/bitfield.h>
|
||||
|
||||
/* when under memory pressure rx ring refill may fail and needs a retry */
|
||||
#define HTT_RX_RING_REFILL_RETRY_MS 50
|
||||
|
@ -181,7 +182,7 @@ static int __ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num)
|
|||
rxcb = ATH10K_SKB_RXCB(skb);
|
||||
rxcb->paddr = paddr;
|
||||
htt->rx_ring.netbufs_ring[idx] = skb;
|
||||
htt->rx_ops->htt_set_paddrs_ring(htt, paddr, idx);
|
||||
ath10k_htt_set_paddrs_ring(htt, paddr, idx);
|
||||
htt->rx_ring.fill_cnt++;
|
||||
|
||||
if (htt->rx_ring.in_ord_rx) {
|
||||
|
@ -286,8 +287,8 @@ void ath10k_htt_rx_free(struct ath10k_htt *htt)
|
|||
ath10k_htt_rx_ring_free(htt);
|
||||
|
||||
dma_free_coherent(htt->ar->dev,
|
||||
htt->rx_ops->htt_get_rx_ring_size(htt),
|
||||
htt->rx_ops->htt_get_vaddr_ring(htt),
|
||||
ath10k_htt_get_rx_ring_size(htt),
|
||||
ath10k_htt_get_vaddr_ring(htt),
|
||||
htt->rx_ring.base_paddr);
|
||||
|
||||
dma_free_coherent(htt->ar->dev,
|
||||
|
@ -314,7 +315,7 @@ static inline struct sk_buff *ath10k_htt_rx_netbuf_pop(struct ath10k_htt *htt)
|
|||
idx = htt->rx_ring.sw_rd_idx.msdu_payld;
|
||||
msdu = htt->rx_ring.netbufs_ring[idx];
|
||||
htt->rx_ring.netbufs_ring[idx] = NULL;
|
||||
htt->rx_ops->htt_reset_paddrs_ring(htt, idx);
|
||||
ath10k_htt_reset_paddrs_ring(htt, idx);
|
||||
|
||||
idx++;
|
||||
idx &= htt->rx_ring.size_mask;
|
||||
|
@ -586,13 +587,13 @@ int ath10k_htt_rx_alloc(struct ath10k_htt *htt)
|
|||
if (!htt->rx_ring.netbufs_ring)
|
||||
goto err_netbuf;
|
||||
|
||||
size = htt->rx_ops->htt_get_rx_ring_size(htt);
|
||||
size = ath10k_htt_get_rx_ring_size(htt);
|
||||
|
||||
vaddr_ring = dma_alloc_coherent(htt->ar->dev, size, &paddr, GFP_KERNEL);
|
||||
if (!vaddr_ring)
|
||||
goto err_dma_ring;
|
||||
|
||||
htt->rx_ops->htt_config_paddrs_ring(htt, vaddr_ring);
|
||||
ath10k_htt_config_paddrs_ring(htt, vaddr_ring);
|
||||
htt->rx_ring.base_paddr = paddr;
|
||||
|
||||
vaddr = dma_alloc_coherent(htt->ar->dev,
|
||||
|
@ -626,7 +627,7 @@ int ath10k_htt_rx_alloc(struct ath10k_htt *htt)
|
|||
|
||||
err_dma_idx:
|
||||
dma_free_coherent(htt->ar->dev,
|
||||
htt->rx_ops->htt_get_rx_ring_size(htt),
|
||||
ath10k_htt_get_rx_ring_size(htt),
|
||||
vaddr_ring,
|
||||
htt->rx_ring.base_paddr);
|
||||
err_dma_ring:
|
||||
|
@ -2719,12 +2720,21 @@ bool ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb)
|
|||
case HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION: {
|
||||
struct htt_tx_done tx_done = {};
|
||||
int status = __le32_to_cpu(resp->mgmt_tx_completion.status);
|
||||
int info = __le32_to_cpu(resp->mgmt_tx_completion.info);
|
||||
|
||||
tx_done.msdu_id = __le32_to_cpu(resp->mgmt_tx_completion.desc_id);
|
||||
|
||||
switch (status) {
|
||||
case HTT_MGMT_TX_STATUS_OK:
|
||||
tx_done.status = HTT_TX_COMPL_STATE_ACK;
|
||||
if (test_bit(WMI_SERVICE_HTT_MGMT_TX_COMP_VALID_FLAGS,
|
||||
ar->wmi.svc_map) &&
|
||||
(resp->mgmt_tx_completion.flags &
|
||||
HTT_MGMT_TX_CMPL_FLAG_ACK_RSSI)) {
|
||||
tx_done.ack_rssi =
|
||||
FIELD_GET(HTT_MGMT_TX_CMPL_INFO_ACK_RSSI_MASK,
|
||||
info);
|
||||
}
|
||||
break;
|
||||
case HTT_MGMT_TX_STATUS_RETRY:
|
||||
tx_done.status = HTT_TX_COMPL_STATE_NOACK;
|
||||
|
|
|
@ -443,13 +443,13 @@ static int ath10k_htt_tx_alloc_buf(struct ath10k_htt *htt)
|
|||
struct ath10k *ar = htt->ar;
|
||||
int ret;
|
||||
|
||||
ret = htt->tx_ops->htt_alloc_txbuff(htt);
|
||||
ret = ath10k_htt_alloc_txbuff(htt);
|
||||
if (ret) {
|
||||
ath10k_err(ar, "failed to alloc cont tx buffer: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = htt->tx_ops->htt_alloc_frag_desc(htt);
|
||||
ret = ath10k_htt_alloc_frag_desc(htt);
|
||||
if (ret) {
|
||||
ath10k_err(ar, "failed to alloc cont frag desc: %d\n", ret);
|
||||
goto free_txbuf;
|
||||
|
@ -473,10 +473,10 @@ free_txq:
|
|||
ath10k_htt_tx_free_txq(htt);
|
||||
|
||||
free_frag_desc:
|
||||
htt->tx_ops->htt_free_frag_desc(htt);
|
||||
ath10k_htt_free_frag_desc(htt);
|
||||
|
||||
free_txbuf:
|
||||
htt->tx_ops->htt_free_txbuff(htt);
|
||||
ath10k_htt_free_txbuff(htt);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
@ -530,9 +530,9 @@ void ath10k_htt_tx_destroy(struct ath10k_htt *htt)
|
|||
if (!htt->tx_mem_allocated)
|
||||
return;
|
||||
|
||||
htt->tx_ops->htt_free_txbuff(htt);
|
||||
ath10k_htt_free_txbuff(htt);
|
||||
ath10k_htt_tx_free_txq(htt);
|
||||
htt->tx_ops->htt_free_frag_desc(htt);
|
||||
ath10k_htt_free_frag_desc(htt);
|
||||
ath10k_htt_tx_free_txdone_fifo(htt);
|
||||
htt->tx_mem_allocated = false;
|
||||
}
|
||||
|
@ -1475,8 +1475,11 @@ static int ath10k_htt_tx_64(struct ath10k_htt *htt,
|
|||
!test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
|
||||
flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD;
|
||||
flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD;
|
||||
if (ar->hw_params.continuous_frag_desc)
|
||||
ext_desc->flags |= HTT_MSDU_CHECKSUM_ENABLE;
|
||||
if (ar->hw_params.continuous_frag_desc) {
|
||||
memset(ext_desc->tso_flag, 0, sizeof(ext_desc->tso_flag));
|
||||
ext_desc->tso_flag[3] |=
|
||||
__cpu_to_le32(HTT_MSDU_CHECKSUM_ENABLE_64);
|
||||
}
|
||||
}
|
||||
|
||||
/* Prevent firmware from sending up tx inspection requests. There's
|
||||
|
|
|
@ -310,6 +310,12 @@ static struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_dst_ring = {
|
|||
.wm_high = &wcn3990_dst_wm_high,
|
||||
};
|
||||
|
||||
static struct ath10k_hw_ce_ctrl1_upd wcn3990_ctrl1_upd = {
|
||||
.shift = 19,
|
||||
.mask = 0x00080000,
|
||||
.enable = 0x00000000,
|
||||
};
|
||||
|
||||
const struct ath10k_hw_ce_regs wcn3990_ce_regs = {
|
||||
.sr_base_addr = 0x00000000,
|
||||
.sr_size_addr = 0x00000008,
|
||||
|
@ -320,8 +326,6 @@ const struct ath10k_hw_ce_regs wcn3990_ce_regs = {
|
|||
.dst_wr_index_addr = 0x00000040,
|
||||
.current_srri_addr = 0x00000044,
|
||||
.current_drri_addr = 0x00000048,
|
||||
.ddr_addr_for_rri_low = 0x00000004,
|
||||
.ddr_addr_for_rri_high = 0x00000008,
|
||||
.ce_rri_low = 0x0024C004,
|
||||
.ce_rri_high = 0x0024C008,
|
||||
.host_ie_addr = 0x0000002c,
|
||||
|
@ -331,6 +335,7 @@ const struct ath10k_hw_ce_regs wcn3990_ce_regs = {
|
|||
.misc_regs = &wcn3990_misc_reg,
|
||||
.wm_srcr = &wcn3990_wm_src_ring,
|
||||
.wm_dstr = &wcn3990_wm_dst_ring,
|
||||
.upd = &wcn3990_ctrl1_upd,
|
||||
};
|
||||
|
||||
const struct ath10k_hw_values wcn3990_values = {
|
||||
|
|
|
@ -1,6 +1,7 @@
|
|||
/*
|
||||
* Copyright (c) 2005-2011 Atheros Communications Inc.
|
||||
* Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
|
||||
* Copyright (c) 2018 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
|
@ -131,7 +132,7 @@ enum qca9377_chip_id_rev {
|
|||
|
||||
/* WCN3990 1.0 definitions */
|
||||
#define WCN3990_HW_1_0_DEV_VERSION ATH10K_HW_WCN3990
|
||||
#define WCN3990_HW_1_0_FW_DIR ATH10K_FW_DIR "/WCN3990/hw3.0"
|
||||
#define WCN3990_HW_1_0_FW_DIR ATH10K_FW_DIR "/WCN3990/hw1.0"
|
||||
|
||||
#define ATH10K_FW_FILE_BASE "firmware"
|
||||
#define ATH10K_FW_API_MAX 6
|
||||
|
@ -335,6 +336,12 @@ struct ath10k_hw_ce_dst_src_wm_regs {
|
|||
struct ath10k_hw_ce_regs_addr_map *wm_low;
|
||||
struct ath10k_hw_ce_regs_addr_map *wm_high; };
|
||||
|
||||
struct ath10k_hw_ce_ctrl1_upd {
|
||||
u32 shift;
|
||||
u32 mask;
|
||||
u32 enable;
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_regs {
|
||||
u32 sr_base_addr;
|
||||
u32 sr_size_addr;
|
||||
|
@ -357,7 +364,9 @@ struct ath10k_hw_ce_regs {
|
|||
struct ath10k_hw_ce_cmd_halt *cmd_halt;
|
||||
struct ath10k_hw_ce_host_ie *host_ie;
|
||||
struct ath10k_hw_ce_dst_src_wm_regs *wm_srcr;
|
||||
struct ath10k_hw_ce_dst_src_wm_regs *wm_dstr; };
|
||||
struct ath10k_hw_ce_dst_src_wm_regs *wm_dstr;
|
||||
struct ath10k_hw_ce_ctrl1_upd *upd;
|
||||
};
|
||||
|
||||
struct ath10k_hw_values {
|
||||
u32 rtc_state_val_on;
|
||||
|
@ -568,6 +577,15 @@ struct ath10k_hw_params {
|
|||
|
||||
/* Target rx ring fill level */
|
||||
u32 rx_ring_fill_level;
|
||||
|
||||
/* target supporting per ce IRQ */
|
||||
bool per_ce_irq;
|
||||
|
||||
/* target supporting shadow register for ce write */
|
||||
bool shadow_reg_support;
|
||||
|
||||
/* target supporting retention restore on ddr */
|
||||
bool rri_on_ddr;
|
||||
};
|
||||
|
||||
struct htt_rx_desc;
|
||||
|
|
|
@ -3598,7 +3598,7 @@ static int ath10k_mac_tx_submit(struct ath10k *ar,
|
|||
|
||||
switch (txpath) {
|
||||
case ATH10K_MAC_TX_HTT:
|
||||
ret = htt->tx_ops->htt_tx(htt, txmode, skb);
|
||||
ret = ath10k_htt_tx(htt, txmode, skb);
|
||||
break;
|
||||
case ATH10K_MAC_TX_HTT_MGMT:
|
||||
ret = ath10k_htt_mgmt_tx(htt, skb);
|
||||
|
@ -4679,6 +4679,13 @@ static int ath10k_start(struct ieee80211_hw *hw)
|
|||
}
|
||||
}
|
||||
|
||||
param = ar->wmi.pdev_param->idle_ps_config;
|
||||
ret = ath10k_wmi_pdev_set_param(ar, param, 1);
|
||||
if (ret && ret != -EOPNOTSUPP) {
|
||||
ath10k_warn(ar, "failed to enable idle_ps_config: %d\n", ret);
|
||||
goto err_core_stop;
|
||||
}
|
||||
|
||||
__ath10k_set_antenna(ar, ar->cfg_tx_chainmask, ar->cfg_rx_chainmask);
|
||||
|
||||
/*
|
||||
|
@ -5717,6 +5724,12 @@ static int ath10k_hw_scan(struct ieee80211_hw *hw,
|
|||
arg.scan_ctrl_flags |= WMI_SCAN_FLAG_PASSIVE;
|
||||
}
|
||||
|
||||
if (req->flags & NL80211_SCAN_FLAG_RANDOM_ADDR) {
|
||||
arg.scan_ctrl_flags |= WMI_SCAN_ADD_SPOOFED_MAC_IN_PROBE_REQ;
|
||||
ether_addr_copy(arg.mac_addr.addr, req->mac_addr);
|
||||
ether_addr_copy(arg.mac_mask.addr, req->mac_addr_mask);
|
||||
}
|
||||
|
||||
if (req->n_channels) {
|
||||
arg.n_channels = req->n_channels;
|
||||
for (i = 0; i < arg.n_channels; i++)
|
||||
|
@ -8433,6 +8446,17 @@ int ath10k_mac_register(struct ath10k *ar)
|
|||
goto err_dfs_detector_exit;
|
||||
}
|
||||
|
||||
if (test_bit(WMI_SERVICE_SPOOF_MAC_SUPPORT, ar->wmi.svc_map)) {
|
||||
ret = ath10k_wmi_scan_prob_req_oui(ar, ar->mac_addr);
|
||||
if (ret) {
|
||||
ath10k_err(ar, "failed to set prob req oui: %i\n", ret);
|
||||
goto err_dfs_detector_exit;
|
||||
}
|
||||
|
||||
ar->hw->wiphy->features |=
|
||||
NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
|
||||
}
|
||||
|
||||
ar->hw->wiphy->cipher_suites = cipher_suites;
|
||||
|
||||
/* QCA988x and QCA6174 family chips do not support CCMP-256, GCMP-128
|
||||
|
|
|
@ -1383,8 +1383,8 @@ int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
|
|||
|
||||
for (i = 0; i < n_items - 1; i++) {
|
||||
ath10k_dbg(ar, ATH10K_DBG_PCI,
|
||||
"pci tx item %d paddr 0x%08x len %d n_items %d\n",
|
||||
i, items[i].paddr, items[i].len, n_items);
|
||||
"pci tx item %d paddr %pad len %d n_items %d\n",
|
||||
i, &items[i].paddr, items[i].len, n_items);
|
||||
ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
|
||||
items[i].vaddr, items[i].len);
|
||||
|
||||
|
@ -1401,8 +1401,8 @@ int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
|
|||
/* `i` is equal to `n_items -1` after for() */
|
||||
|
||||
ath10k_dbg(ar, ATH10K_DBG_PCI,
|
||||
"pci tx item %d paddr 0x%08x len %d n_items %d\n",
|
||||
i, items[i].paddr, items[i].len, n_items);
|
||||
"pci tx item %d paddr %pad len %d n_items %d\n",
|
||||
i, &items[i].paddr, items[i].len, n_items);
|
||||
ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
|
||||
items[i].vaddr, items[i].len);
|
||||
|
||||
|
|
|
@ -1957,25 +1957,25 @@ static int ath10k_sdio_probe(struct sdio_func *func,
|
|||
ar_sdio = ath10k_sdio_priv(ar);
|
||||
|
||||
ar_sdio->irq_data.irq_proc_reg =
|
||||
kzalloc(sizeof(struct ath10k_sdio_irq_proc_regs),
|
||||
GFP_KERNEL);
|
||||
devm_kzalloc(ar->dev, sizeof(struct ath10k_sdio_irq_proc_regs),
|
||||
GFP_KERNEL);
|
||||
if (!ar_sdio->irq_data.irq_proc_reg) {
|
||||
ret = -ENOMEM;
|
||||
goto err_core_destroy;
|
||||
}
|
||||
|
||||
ar_sdio->irq_data.irq_en_reg =
|
||||
kzalloc(sizeof(struct ath10k_sdio_irq_enable_regs),
|
||||
GFP_KERNEL);
|
||||
devm_kzalloc(ar->dev, sizeof(struct ath10k_sdio_irq_enable_regs),
|
||||
GFP_KERNEL);
|
||||
if (!ar_sdio->irq_data.irq_en_reg) {
|
||||
ret = -ENOMEM;
|
||||
goto err_free_proc_reg;
|
||||
goto err_core_destroy;
|
||||
}
|
||||
|
||||
ar_sdio->bmi_buf = kzalloc(BMI_MAX_CMDBUF_SIZE, GFP_KERNEL);
|
||||
ar_sdio->bmi_buf = devm_kzalloc(ar->dev, BMI_MAX_CMDBUF_SIZE, GFP_KERNEL);
|
||||
if (!ar_sdio->bmi_buf) {
|
||||
ret = -ENOMEM;
|
||||
goto err_free_en_reg;
|
||||
goto err_core_destroy;
|
||||
}
|
||||
|
||||
ar_sdio->func = func;
|
||||
|
@ -1995,7 +1995,7 @@ static int ath10k_sdio_probe(struct sdio_func *func,
|
|||
ar_sdio->workqueue = create_singlethread_workqueue("ath10k_sdio_wq");
|
||||
if (!ar_sdio->workqueue) {
|
||||
ret = -ENOMEM;
|
||||
goto err_free_bmi_buf;
|
||||
goto err_core_destroy;
|
||||
}
|
||||
|
||||
for (i = 0; i < ATH10K_SDIO_BUS_REQUEST_MAX_NUM; i++)
|
||||
|
@ -2011,7 +2011,7 @@ static int ath10k_sdio_probe(struct sdio_func *func,
|
|||
ret = -ENODEV;
|
||||
ath10k_err(ar, "unsupported device id %u (0x%x)\n",
|
||||
dev_id_base, id->device);
|
||||
goto err_free_bmi_buf;
|
||||
goto err_core_destroy;
|
||||
}
|
||||
|
||||
ar->id.vendor = id->vendor;
|
||||
|
@ -2040,12 +2040,6 @@ static int ath10k_sdio_probe(struct sdio_func *func,
|
|||
|
||||
err_free_wq:
|
||||
destroy_workqueue(ar_sdio->workqueue);
|
||||
err_free_bmi_buf:
|
||||
kfree(ar_sdio->bmi_buf);
|
||||
err_free_en_reg:
|
||||
kfree(ar_sdio->irq_data.irq_en_reg);
|
||||
err_free_proc_reg:
|
||||
kfree(ar_sdio->irq_data.irq_proc_reg);
|
||||
err_core_destroy:
|
||||
ath10k_core_destroy(ar);
|
||||
|
||||
|
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -0,0 +1,95 @@
|
|||
/*
|
||||
* Copyright (c) 2018 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _SNOC_H_
|
||||
#define _SNOC_H_
|
||||
|
||||
#include "hw.h"
|
||||
#include "ce.h"
|
||||
#include "pci.h"
|
||||
|
||||
struct ath10k_snoc_drv_priv {
|
||||
enum ath10k_hw_rev hw_rev;
|
||||
u64 dma_mask;
|
||||
};
|
||||
|
||||
struct snoc_state {
|
||||
u32 pipe_cfg_addr;
|
||||
u32 svc_to_pipe_map;
|
||||
};
|
||||
|
||||
struct ath10k_snoc_pipe {
|
||||
struct ath10k_ce_pipe *ce_hdl;
|
||||
u8 pipe_num;
|
||||
struct ath10k *hif_ce_state;
|
||||
size_t buf_sz;
|
||||
/* protect ce info */
|
||||
spinlock_t pipe_lock;
|
||||
struct ath10k_snoc *ar_snoc;
|
||||
};
|
||||
|
||||
struct ath10k_snoc_target_info {
|
||||
u32 target_version;
|
||||
u32 target_type;
|
||||
u32 target_revision;
|
||||
u32 soc_version;
|
||||
};
|
||||
|
||||
struct ath10k_snoc_ce_irq {
|
||||
u32 irq_line;
|
||||
};
|
||||
|
||||
struct ath10k_wcn3990_vreg_info {
|
||||
struct regulator *reg;
|
||||
const char *name;
|
||||
u32 min_v;
|
||||
u32 max_v;
|
||||
u32 load_ua;
|
||||
unsigned long settle_delay;
|
||||
bool required;
|
||||
};
|
||||
|
||||
struct ath10k_wcn3990_clk_info {
|
||||
struct clk *handle;
|
||||
const char *name;
|
||||
u32 freq;
|
||||
bool required;
|
||||
};
|
||||
|
||||
struct ath10k_snoc {
|
||||
struct platform_device *dev;
|
||||
struct ath10k *ar;
|
||||
void __iomem *mem;
|
||||
dma_addr_t mem_pa;
|
||||
struct ath10k_snoc_target_info target_info;
|
||||
size_t mem_len;
|
||||
struct ath10k_snoc_pipe pipe_info[CE_COUNT_MAX];
|
||||
struct ath10k_snoc_ce_irq ce_irqs[CE_COUNT_MAX];
|
||||
struct ath10k_ce ce;
|
||||
struct timer_list rx_post_retry;
|
||||
struct ath10k_wcn3990_vreg_info *vreg;
|
||||
struct ath10k_wcn3990_clk_info *clk;
|
||||
};
|
||||
|
||||
static inline struct ath10k_snoc *ath10k_snoc_priv(struct ath10k *ar)
|
||||
{
|
||||
return (struct ath10k_snoc *)ar->drv_priv;
|
||||
}
|
||||
|
||||
void ath10k_snoc_write32(struct ath10k *ar, u32 offset, u32 value);
|
||||
u32 ath10k_snoc_read32(struct ath10k *ar, u32 offset);
|
||||
|
||||
#endif /* _SNOC_H_ */
|
|
@ -1,6 +1,7 @@
|
|||
/*
|
||||
* Copyright (c) 2005-2011 Atheros Communications Inc.
|
||||
* Copyright (c) 2011-2016 Qualcomm Atheros, Inc.
|
||||
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
|
@ -119,6 +120,13 @@ int ath10k_txrx_tx_unref(struct ath10k_htt *htt,
|
|||
info->flags &= ~IEEE80211_TX_STAT_ACK;
|
||||
}
|
||||
|
||||
if (tx_done->status == HTT_TX_COMPL_STATE_ACK &&
|
||||
tx_done->ack_rssi != ATH10K_INVALID_RSSI) {
|
||||
info->status.ack_signal = ATH10K_DEFAULT_NOISE_FLOOR +
|
||||
tx_done->ack_rssi;
|
||||
info->status.is_valid_ack_signal = true;
|
||||
}
|
||||
|
||||
ieee80211_tx_status(htt->ar->hw, msdu);
|
||||
/* we do not own the msdu anymore */
|
||||
|
||||
|
|
|
@ -25,6 +25,7 @@ struct sk_buff;
|
|||
struct wmi_ops {
|
||||
void (*rx)(struct ath10k *ar, struct sk_buff *skb);
|
||||
void (*map_svc)(const __le32 *in, unsigned long *out, size_t len);
|
||||
void (*map_svc_ext)(const __le32 *in, unsigned long *out, size_t len);
|
||||
|
||||
int (*pull_scan)(struct ath10k *ar, struct sk_buff *skb,
|
||||
struct wmi_scan_ev_arg *arg);
|
||||
|
@ -54,6 +55,9 @@ struct wmi_ops {
|
|||
struct wmi_wow_ev_arg *arg);
|
||||
int (*pull_echo_ev)(struct ath10k *ar, struct sk_buff *skb,
|
||||
struct wmi_echo_ev_arg *arg);
|
||||
int (*pull_svc_avail)(struct ath10k *ar, struct sk_buff *skb,
|
||||
struct wmi_svc_avail_ev_arg *arg);
|
||||
|
||||
enum wmi_txbf_conf (*get_txbf_conf_scheme)(struct ath10k *ar);
|
||||
|
||||
struct sk_buff *(*gen_pdev_suspend)(struct ath10k *ar, u32 suspend_opt);
|
||||
|
@ -115,6 +119,8 @@ struct wmi_ops {
|
|||
u32 value);
|
||||
struct sk_buff *(*gen_scan_chan_list)(struct ath10k *ar,
|
||||
const struct wmi_scan_chan_list_arg *arg);
|
||||
struct sk_buff *(*gen_scan_prob_req_oui)(struct ath10k *ar,
|
||||
u32 prob_req_oui);
|
||||
struct sk_buff *(*gen_beacon_dma)(struct ath10k *ar, u32 vdev_id,
|
||||
const void *bcn, size_t bcn_len,
|
||||
u32 bcn_paddr, bool dtim_zero,
|
||||
|
@ -229,6 +235,17 @@ ath10k_wmi_map_svc(struct ath10k *ar, const __le32 *in, unsigned long *out,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
ath10k_wmi_map_svc_ext(struct ath10k *ar, const __le32 *in, unsigned long *out,
|
||||
size_t len)
|
||||
{
|
||||
if (!ar->wmi.ops->map_svc_ext)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
ar->wmi.ops->map_svc_ext(in, out, len);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
ath10k_wmi_pull_scan(struct ath10k *ar, struct sk_buff *skb,
|
||||
struct wmi_scan_ev_arg *arg)
|
||||
|
@ -329,6 +346,15 @@ ath10k_wmi_pull_rdy(struct ath10k *ar, struct sk_buff *skb,
|
|||
return ar->wmi.ops->pull_rdy(ar, skb, arg);
|
||||
}
|
||||
|
||||
static inline int
|
||||
ath10k_wmi_pull_svc_avail(struct ath10k *ar, struct sk_buff *skb,
|
||||
struct wmi_svc_avail_ev_arg *arg)
|
||||
{
|
||||
if (!ar->wmi.ops->pull_svc_avail)
|
||||
return -EOPNOTSUPP;
|
||||
return ar->wmi.ops->pull_svc_avail(ar, skb, arg);
|
||||
}
|
||||
|
||||
static inline int
|
||||
ath10k_wmi_pull_fw_stats(struct ath10k *ar, struct sk_buff *skb,
|
||||
struct ath10k_fw_stats *stats)
|
||||
|
@ -890,6 +916,26 @@ ath10k_wmi_scan_chan_list(struct ath10k *ar,
|
|||
return ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->scan_chan_list_cmdid);
|
||||
}
|
||||
|
||||
static inline int
|
||||
ath10k_wmi_scan_prob_req_oui(struct ath10k *ar, const u8 mac_addr[ETH_ALEN])
|
||||
{
|
||||
struct sk_buff *skb;
|
||||
u32 prob_req_oui;
|
||||
|
||||
prob_req_oui = (((u32)mac_addr[0]) << 16) |
|
||||
(((u32)mac_addr[1]) << 8) | mac_addr[2];
|
||||
|
||||
if (!ar->wmi.ops->gen_scan_prob_req_oui)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
skb = ar->wmi.ops->gen_scan_prob_req_oui(ar, prob_req_oui);
|
||||
if (IS_ERR(skb))
|
||||
return PTR_ERR(skb);
|
||||
|
||||
return ath10k_wmi_cmd_send(ar, skb,
|
||||
ar->wmi.cmd->scan_prob_req_oui_cmdid);
|
||||
}
|
||||
|
||||
static inline int
|
||||
ath10k_wmi_peer_assoc(struct ath10k *ar,
|
||||
const struct wmi_peer_assoc_complete_arg *arg)
|
||||
|
|
|
@ -594,6 +594,9 @@ static void ath10k_wmi_tlv_op_rx(struct ath10k *ar, struct sk_buff *skb)
|
|||
case WMI_TLV_READY_EVENTID:
|
||||
ath10k_wmi_event_ready(ar, skb);
|
||||
break;
|
||||
case WMI_TLV_SERVICE_AVAILABLE_EVENTID:
|
||||
ath10k_wmi_event_service_available(ar, skb);
|
||||
break;
|
||||
case WMI_TLV_OFFLOAD_BCN_TX_STATUS_EVENTID:
|
||||
ath10k_wmi_tlv_event_bcn_tx_status(ar, skb);
|
||||
break;
|
||||
|
@ -1117,6 +1120,39 @@ static int ath10k_wmi_tlv_op_pull_rdy_ev(struct ath10k *ar,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int ath10k_wmi_tlv_svc_avail_parse(struct ath10k *ar, u16 tag, u16 len,
|
||||
const void *ptr, void *data)
|
||||
{
|
||||
struct wmi_svc_avail_ev_arg *arg = data;
|
||||
|
||||
switch (tag) {
|
||||
case WMI_TLV_TAG_STRUCT_SERVICE_AVAILABLE_EVENT:
|
||||
arg->service_map_ext_len = *(__le32 *)ptr;
|
||||
arg->service_map_ext = ptr + sizeof(__le32);
|
||||
return 0;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return -EPROTO;
|
||||
}
|
||||
|
||||
static int ath10k_wmi_tlv_op_pull_svc_avail(struct ath10k *ar,
|
||||
struct sk_buff *skb,
|
||||
struct wmi_svc_avail_ev_arg *arg)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = ath10k_wmi_tlv_iter(ar, skb->data, skb->len,
|
||||
ath10k_wmi_tlv_svc_avail_parse, arg);
|
||||
|
||||
if (ret) {
|
||||
ath10k_warn(ar, "failed to parse svc_avail tlv: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ath10k_wmi_tlv_pull_vdev_stats(const struct wmi_tlv_vdev_stats *src,
|
||||
struct ath10k_fw_stats_vdev *dst)
|
||||
{
|
||||
|
@ -1600,6 +1636,8 @@ ath10k_wmi_tlv_op_gen_start_scan(struct ath10k *ar,
|
|||
cmd->num_bssids = __cpu_to_le32(arg->n_bssids);
|
||||
cmd->ie_len = __cpu_to_le32(arg->ie_len);
|
||||
cmd->num_probes = __cpu_to_le32(3);
|
||||
ether_addr_copy(cmd->mac_addr.addr, arg->mac_addr.addr);
|
||||
ether_addr_copy(cmd->mac_mask.addr, arg->mac_mask.addr);
|
||||
|
||||
/* FIXME: There are some scan flag inconsistencies across firmwares,
|
||||
* e.g. WMI-TLV inverts the logic behind the following flag.
|
||||
|
@ -2446,6 +2484,27 @@ ath10k_wmi_tlv_op_gen_scan_chan_list(struct ath10k *ar,
|
|||
return skb;
|
||||
}
|
||||
|
||||
static struct sk_buff *
|
||||
ath10k_wmi_tlv_op_gen_scan_prob_req_oui(struct ath10k *ar, u32 prob_req_oui)
|
||||
{
|
||||
struct wmi_scan_prob_req_oui_cmd *cmd;
|
||||
struct wmi_tlv *tlv;
|
||||
struct sk_buff *skb;
|
||||
|
||||
skb = ath10k_wmi_alloc_skb(ar, sizeof(*tlv) + sizeof(*cmd));
|
||||
if (!skb)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
tlv = (void *)skb->data;
|
||||
tlv->tag = __cpu_to_le16(WMI_TLV_TAG_STRUCT_SCAN_PROB_REQ_OUI_CMD);
|
||||
tlv->len = __cpu_to_le16(sizeof(*cmd));
|
||||
cmd = (void *)tlv->value;
|
||||
cmd->prob_req_oui = __cpu_to_le32(prob_req_oui);
|
||||
|
||||
ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi tlv scan prob req oui\n");
|
||||
return skb;
|
||||
}
|
||||
|
||||
static struct sk_buff *
|
||||
ath10k_wmi_tlv_op_gen_beacon_dma(struct ath10k *ar, u32 vdev_id,
|
||||
const void *bcn, size_t bcn_len,
|
||||
|
@ -3416,6 +3475,7 @@ static struct wmi_cmd_map wmi_tlv_cmd_map = {
|
|||
.stop_scan_cmdid = WMI_TLV_STOP_SCAN_CMDID,
|
||||
.scan_chan_list_cmdid = WMI_TLV_SCAN_CHAN_LIST_CMDID,
|
||||
.scan_sch_prio_tbl_cmdid = WMI_TLV_SCAN_SCH_PRIO_TBL_CMDID,
|
||||
.scan_prob_req_oui_cmdid = WMI_TLV_SCAN_PROB_REQ_OUI_CMDID,
|
||||
.pdev_set_regdomain_cmdid = WMI_TLV_PDEV_SET_REGDOMAIN_CMDID,
|
||||
.pdev_set_channel_cmdid = WMI_TLV_PDEV_SET_CHANNEL_CMDID,
|
||||
.pdev_set_param_cmdid = WMI_TLV_PDEV_SET_PARAM_CMDID,
|
||||
|
@ -3740,6 +3800,7 @@ static struct wmi_vdev_param_map wmi_tlv_vdev_param_map = {
|
|||
static const struct wmi_ops wmi_tlv_ops = {
|
||||
.rx = ath10k_wmi_tlv_op_rx,
|
||||
.map_svc = wmi_tlv_svc_map,
|
||||
.map_svc_ext = wmi_tlv_svc_map_ext,
|
||||
|
||||
.pull_scan = ath10k_wmi_tlv_op_pull_scan_ev,
|
||||
.pull_mgmt_rx = ath10k_wmi_tlv_op_pull_mgmt_rx_ev,
|
||||
|
@ -3751,6 +3812,7 @@ static const struct wmi_ops wmi_tlv_ops = {
|
|||
.pull_phyerr = ath10k_wmi_op_pull_phyerr_ev,
|
||||
.pull_svc_rdy = ath10k_wmi_tlv_op_pull_svc_rdy_ev,
|
||||
.pull_rdy = ath10k_wmi_tlv_op_pull_rdy_ev,
|
||||
.pull_svc_avail = ath10k_wmi_tlv_op_pull_svc_avail,
|
||||
.pull_fw_stats = ath10k_wmi_tlv_op_pull_fw_stats,
|
||||
.pull_roam_ev = ath10k_wmi_tlv_op_pull_roam_ev,
|
||||
.pull_wow_event = ath10k_wmi_tlv_op_pull_wow_ev,
|
||||
|
@ -3782,6 +3844,7 @@ static const struct wmi_ops wmi_tlv_ops = {
|
|||
.gen_set_sta_ps = ath10k_wmi_tlv_op_gen_set_sta_ps,
|
||||
.gen_set_ap_ps = ath10k_wmi_tlv_op_gen_set_ap_ps,
|
||||
.gen_scan_chan_list = ath10k_wmi_tlv_op_gen_scan_chan_list,
|
||||
.gen_scan_prob_req_oui = ath10k_wmi_tlv_op_gen_scan_prob_req_oui,
|
||||
.gen_beacon_dma = ath10k_wmi_tlv_op_gen_beacon_dma,
|
||||
.gen_pdev_set_wmm = ath10k_wmi_tlv_op_gen_pdev_set_wmm,
|
||||
.gen_request_stats = ath10k_wmi_tlv_op_gen_request_stats,
|
||||
|
|
|
@ -295,6 +295,7 @@ enum wmi_tlv_cmd_id {
|
|||
enum wmi_tlv_event_id {
|
||||
WMI_TLV_SERVICE_READY_EVENTID = 0x1,
|
||||
WMI_TLV_READY_EVENTID,
|
||||
WMI_TLV_SERVICE_AVAILABLE_EVENTID,
|
||||
WMI_TLV_SCAN_EVENTID = WMI_TLV_EV(WMI_TLV_GRP_SCAN),
|
||||
WMI_TLV_PDEV_TPC_CONFIG_EVENTID = WMI_TLV_EV(WMI_TLV_GRP_PDEV),
|
||||
WMI_TLV_CHAN_INFO_EVENTID,
|
||||
|
@ -949,6 +950,275 @@ enum wmi_tlv_tag {
|
|||
WMI_TLV_TAG_STRUCT_PACKET_FILTER_ENABLE,
|
||||
WMI_TLV_TAG_STRUCT_SAP_SET_BLACKLIST_PARAM_CMD,
|
||||
WMI_TLV_TAG_STRUCT_MGMT_TX_CMD,
|
||||
WMI_TLV_TAG_STRUCT_MGMT_TX_COMPL_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_SOC_SET_ANTENNA_MODE_CMD,
|
||||
WMI_TLV_TAG_STRUCT_WOW_UDP_SVC_OFLD_CMD,
|
||||
WMI_TLV_TAG_STRUCT_LRO_INFO_CMD,
|
||||
WMI_TLV_TAG_STRUCT_ROAM_EARLYSTOP_RSSI_THRES_PARAM,
|
||||
WMI_TLV_TAG_STRUCT_SERVICE_READY_EXT_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_MAWC_SENSOR_REPORT_IND_CMD,
|
||||
WMI_TLV_TAG_STRUCT_MAWC_ENABLE_SENSOR_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_ROAM_CONFIGURE_MAWC_CMD,
|
||||
WMI_TLV_TAG_STRUCT_NLO_CONFIGURE_MAWC_CMD,
|
||||
WMI_TLV_TAG_STRUCT_EXTSCAN_CONFIGURE_MAWC_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PEER_ASSOC_CONF_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMD,
|
||||
WMI_TLV_TAG_STRUCT_AP_PS_EGAP_PARAM_CMD,
|
||||
WMI_TLV_TAG_STRUCT_AP_PS_EGAP_INFO_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_PMF_OFFLOAD_SET_SA_QUERY_CMD,
|
||||
WMI_TLV_TAG_STRUCT_TRANSFER_DATA_TO_FLASH_CMD,
|
||||
WMI_TLV_TAG_STRUCT_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_SCPC_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_AP_PS_EGAP_INFO_CHAINMASK_LIST,
|
||||
WMI_TLV_TAG_STRUCT_STA_SMPS_FORCE_MODE_COMPLETE_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_BPF_GET_CAPABILITY_CMD,
|
||||
WMI_TLV_TAG_STRUCT_BPF_CAPABILITY_INFO_EVT,
|
||||
WMI_TLV_TAG_STRUCT_BPF_GET_VDEV_STATS_CMD,
|
||||
WMI_TLV_TAG_STRUCT_BPF_VDEV_STATS_INFO_EVT,
|
||||
WMI_TLV_TAG_STRUCT_BPF_SET_VDEV_INSTRUCTIONS_CMD,
|
||||
WMI_TLV_TAG_STRUCT_BPF_DEL_VDEV_INSTRUCTIONS_CMD,
|
||||
WMI_TLV_TAG_STRUCT_VDEV_DELETE_RESP_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_PEER_DELETE_RESP_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_ROAM_DENSE_THRES_PARAM,
|
||||
WMI_TLV_TAG_STRUCT_ENLO_CANDIDATE_SCORE_PARAM,
|
||||
WMI_TLV_TAG_STRUCT_PEER_UPDATE_WDS_ENTRY_CMD,
|
||||
WMI_TLV_TAG_STRUCT_VDEV_CONFIG_RATEMASK,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_FIPS_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_SMART_ANT_ENABLE_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_SMART_ANT_SET_RX_ANTENNA_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PEER_SMART_ANT_SET_TX_ANTENNA_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PEER_SMART_ANT_SET_TRAIN_ANTENNA_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_SET_ANT_SWITCH_TBL_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_SET_CTL_TABLE_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_SET_MIMOGAIN_TABLE_CMD,
|
||||
WMI_TLV_TAG_STRUCT_FWTEST_SET_PARAM_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PEER_ATF_REQUEST,
|
||||
WMI_TLV_TAG_STRUCT_VDEV_ATF_REQUEST,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_GET_ANI_CCK_CONFIG_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_GET_ANI_OFDM_CONFIG_CMD,
|
||||
WMI_TLV_TAG_STRUCT_INST_RSSI_STATS_RESP,
|
||||
WMI_TLV_TAG_STRUCT_MED_UTIL_REPORT_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_PEER_STA_PS_STATECHANGE_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_WDS_ADDR_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_PEER_RATECODE_LIST_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_TPC_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_ANI_OFDM_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_ANI_CCK_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_CHANNEL_HOPPING_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_FIPS_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_ATF_PEER_INFO,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_GET_TPC_CMD,
|
||||
WMI_TLV_TAG_STRUCT_VDEV_FILTER_NRP_CONFIG_CMD,
|
||||
WMI_TLV_TAG_STRUCT_QBOOST_CFG_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_SMART_ANT_GPIO_HANDLE,
|
||||
WMI_TLV_TAG_STRUCT_PEER_SMART_ANT_SET_TX_ANTENNA_SERIES,
|
||||
WMI_TLV_TAG_STRUCT_PEER_SMART_ANT_SET_TRAIN_ANTENNA_PARAM,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_SET_ANT_CTRL_CHAIN,
|
||||
WMI_TLV_TAG_STRUCT_PEER_CCK_OFDM_RATE_INFO,
|
||||
WMI_TLV_TAG_STRUCT_PEER_MCS_RATE_INFO,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBR,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBM,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_NFCAL_POWER_ALL_CHANNELS_FREQNUM,
|
||||
WMI_TLV_TAG_STRUCT_MU_REPORT_TOTAL_MU,
|
||||
WMI_TLV_TAG_STRUCT_VDEV_SET_DSCP_TID_MAP_CMD,
|
||||
WMI_TLV_TAG_STRUCT_ROAM_SET_MBO,
|
||||
WMI_TLV_TAG_STRUCT_MIB_STATS_ENABLE_CMD,
|
||||
WMI_TLV_TAG_STRUCT_NAN_DISC_IFACE_CREATED_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_NAN_DISC_IFACE_DELETED_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_NAN_STARTED_CLUSTER_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_NAN_JOINED_CLUSTER_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_NDI_GET_CAP_REQ,
|
||||
WMI_TLV_TAG_STRUCT_NDP_INITIATOR_REQ,
|
||||
WMI_TLV_TAG_STRUCT_NDP_RESPONDER_REQ,
|
||||
WMI_TLV_TAG_STRUCT_NDP_END_REQ,
|
||||
WMI_TLV_TAG_STRUCT_NDI_CAP_RSP_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_NDP_INITIATOR_RSP_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_NDP_RESPONDER_RSP_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_NDP_END_RSP_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_NDP_INDICATION_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_NDP_CONFIRM_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_NDP_END_INDICATION_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_VDEV_SET_QUIET_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_SET_PCL_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_SET_HW_MODE_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_SET_MAC_CONFIG_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_SET_ANTENNA_MODE_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_SET_HW_MODE_RESPONSE_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_HW_MODE_TRANSITION_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_SET_MAC_CONFIG_RESPONSE_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_COEX_CONFIG_CMD,
|
||||
WMI_TLV_TAG_STRUCT_CONFIG_ENHANCED_MCAST_FILTER,
|
||||
WMI_TLV_TAG_STRUCT_CHAN_AVOID_RPT_ALLOW_CMD,
|
||||
WMI_TLV_TAG_STRUCT_SET_PERIODIC_CHANNEL_STATS_CONFIG,
|
||||
WMI_TLV_TAG_STRUCT_VDEV_SET_CUSTOM_AGGR_SIZE_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_WAL_POWER_DEBUG_CMD,
|
||||
WMI_TLV_TAG_STRUCT_MAC_PHY_CAPABILITIES,
|
||||
WMI_TLV_TAG_STRUCT_HW_MODE_CAPABILITIES,
|
||||
WMI_TLV_TAG_STRUCT_SOC_MAC_PHY_HW_MODE_CAPS,
|
||||
WMI_TLV_TAG_STRUCT_HAL_REG_CAPABILITIES_EXT,
|
||||
WMI_TLV_TAG_STRUCT_SOC_HAL_REG_CAPABILITIES,
|
||||
WMI_TLV_TAG_STRUCT_VDEV_WISA_CMD,
|
||||
WMI_TLV_TAG_STRUCT_TX_POWER_LEVEL_STATS_EVT,
|
||||
WMI_TLV_TAG_STRUCT_SCAN_ADAPTIVE_DWELL_PARAMETERS_TLV,
|
||||
WMI_TLV_TAG_STRUCT_SCAN_ADAPTIVE_DWELL_CONFIG,
|
||||
WMI_TLV_TAG_STRUCT_WOW_SET_ACTION_WAKE_UP_CMD,
|
||||
WMI_TLV_TAG_STRUCT_NDP_END_RSP_PER_NDI,
|
||||
WMI_TLV_TAG_STRUCT_PEER_BWF_REQUEST,
|
||||
WMI_TLV_TAG_STRUCT_BWF_PEER_INFO,
|
||||
WMI_TLV_TAG_STRUCT_DBGLOG_TIME_STAMP_SYNC_CMD,
|
||||
WMI_TLV_TAG_STRUCT_RMC_SET_LEADER_CMD,
|
||||
WMI_TLV_TAG_STRUCT_RMC_MANUAL_LEADER_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_PER_CHAIN_RSSI_STATS,
|
||||
WMI_TLV_TAG_STRUCT_RSSI_STATS,
|
||||
WMI_TLV_TAG_STRUCT_P2P_LO_START_CMD,
|
||||
WMI_TLV_TAG_STRUCT_P2P_LO_STOP_CMD,
|
||||
WMI_TLV_TAG_STRUCT_P2P_LO_STOPPED_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_PEER_REORDER_QUEUE_SETUP_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PEER_REORDER_QUEUE_REMOVE_CMD,
|
||||
WMI_TLV_TAG_STRUCT_SET_MULTIPLE_MCAST_FILTER_CMD,
|
||||
WMI_TLV_TAG_STRUCT_MGMT_TX_COMPL_BUNDLE_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_READ_DATA_FROM_FLASH_CMD,
|
||||
WMI_TLV_TAG_STRUCT_READ_DATA_FROM_FLASH_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_SET_REORDER_TIMEOUT_VAL_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PEER_SET_RX_BLOCKSIZE_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_SET_WAKEUP_CONFIG_CMDID,
|
||||
WMI_TLV_TAG_STRUCT_TLV_BUF_LEN_PARAM,
|
||||
WMI_TLV_TAG_STRUCT_SERVICE_AVAILABLE_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_PEER_ANTDIV_INFO_REQ_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PEER_ANTDIV_INFO_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_PEER_ANTDIV_INFO,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_GET_ANTDIV_STATUS_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_ANTDIV_STATUS_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_MNT_FILTER_CMD,
|
||||
WMI_TLV_TAG_STRUCT_GET_CHIP_POWER_STATS_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_CHIP_POWER_STATS_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_COEX_GET_ANTENNA_ISOLATION_CMD,
|
||||
WMI_TLV_TAG_STRUCT_COEX_REPORT_ISOLATION_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_CHAN_CCA_STATS,
|
||||
WMI_TLV_TAG_STRUCT_PEER_SIGNAL_STATS,
|
||||
WMI_TLV_TAG_STRUCT_TX_STATS,
|
||||
WMI_TLV_TAG_STRUCT_PEER_AC_TX_STATS,
|
||||
WMI_TLV_TAG_STRUCT_RX_STATS,
|
||||
WMI_TLV_TAG_STRUCT_PEER_AC_RX_STATS,
|
||||
WMI_TLV_TAG_STRUCT_REPORT_STATS_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_CHAN_CCA_STATS_THRESH,
|
||||
WMI_TLV_TAG_STRUCT_PEER_SIGNAL_STATS_THRESH,
|
||||
WMI_TLV_TAG_STRUCT_TX_STATS_THRESH,
|
||||
WMI_TLV_TAG_STRUCT_RX_STATS_THRESH,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_SET_STATS_THRESHOLD_CMD,
|
||||
WMI_TLV_TAG_STRUCT_REQUEST_WLAN_STATS_CMD,
|
||||
WMI_TLV_TAG_STRUCT_RX_AGGR_FAILURE_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_RX_AGGR_FAILURE_INFO,
|
||||
WMI_TLV_TAG_STRUCT_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMD,
|
||||
WMI_TLV_TAG_STRUCT_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_BAND_TO_MAC,
|
||||
WMI_TLV_TAG_STRUCT_TBTT_OFFSET_INFO,
|
||||
WMI_TLV_TAG_STRUCT_TBTT_OFFSET_EXT_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_SAR_LIMITS_CMD,
|
||||
WMI_TLV_TAG_STRUCT_SAR_LIMIT_CMD_ROW,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMD,
|
||||
WMI_TLV_TAG_STRUCT_VDEV_ADFS_CH_CFG_CMD,
|
||||
WMI_TLV_TAG_STRUCT_VDEV_ADFS_OCAC_ABORT_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_DFS_RADAR_DETECTION_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_VDEV_ADFS_OCAC_COMPLETE_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_VDEV_DFS_CAC_COMPLETE_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_VENDOR_OUI,
|
||||
WMI_TLV_TAG_STRUCT_REQUEST_RCPI_CMD,
|
||||
WMI_TLV_TAG_STRUCT_UPDATE_RCPI_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_REQUEST_PEER_STATS_INFO_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PEER_STATS_INFO,
|
||||
WMI_TLV_TAG_STRUCT_PEER_STATS_INFO_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_PKGID_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_CONNECTED_NLO_RSSI_PARAMS,
|
||||
WMI_TLV_TAG_STRUCT_SET_CURRENT_COUNTRY_CMD,
|
||||
WMI_TLV_TAG_STRUCT_REGULATORY_RULE_STRUCT,
|
||||
WMI_TLV_TAG_STRUCT_REG_CHAN_LIST_CC_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_11D_SCAN_START_CMD,
|
||||
WMI_TLV_TAG_STRUCT_11D_SCAN_STOP_CMD,
|
||||
WMI_TLV_TAG_STRUCT_11D_NEW_COUNTRY_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_REQUEST_RADIO_CHAN_STATS_CMD,
|
||||
WMI_TLV_TAG_STRUCT_RADIO_CHAN_STATS,
|
||||
WMI_TLV_TAG_STRUCT_RADIO_CHAN_STATS_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_ROAM_PER_CONFIG,
|
||||
WMI_TLV_TAG_STRUCT_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMD,
|
||||
WMI_TLV_TAG_STRUCT_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_BPF_SET_VDEV_ACTIVE_MODE_CMD,
|
||||
WMI_TLV_TAG_STRUCT_HW_DATA_FILTER_CMD,
|
||||
WMI_TLV_TAG_STRUCT_CONNECTED_NLO_BSS_BAND_RSSI_PREF,
|
||||
WMI_TLV_TAG_STRUCT_PEER_OPER_MODE_CHANGE_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_CHIP_POWER_SAVE_FAILURE_DETECTED,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_CSA_SWITCH_COUNT_STATUS_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_UPDATE_PKT_ROUTING_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_CHECK_CAL_VERSION_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_CHECK_CAL_VERSION_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_SET_DIVERSITY_GAIN_CMD,
|
||||
WMI_TLV_TAG_STRUCT_MAC_PHY_CHAINMASK_COMBO,
|
||||
WMI_TLV_TAG_STRUCT_MAC_PHY_CHAINMASK_CAPABILITY,
|
||||
WMI_TLV_TAG_STRUCT_VDEV_SET_ARP_STATS_CMD,
|
||||
WMI_TLV_TAG_STRUCT_VDEV_GET_ARP_STATS_CMD,
|
||||
WMI_TLV_TAG_STRUCT_VDEV_GET_ARP_STATS_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_IFACE_OFFLOAD_STATS,
|
||||
WMI_TLV_TAG_STRUCT_REQUEST_STATS_CMD_SUB_STRUCT_PARAM,
|
||||
WMI_TLV_TAG_STRUCT_RSSI_CTL_EXT,
|
||||
WMI_TLV_TAG_STRUCT_SINGLE_PHYERR_EXT_RX_HDR,
|
||||
WMI_TLV_TAG_STRUCT_COEX_BT_ACTIVITY_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_VDEV_GET_TX_POWER_CMD,
|
||||
WMI_TLV_TAG_STRUCT_VDEV_TX_POWER_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_OFFCHAN_DATA_TX_COMPL_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_OFFCHAN_DATA_TX_SEND_CMD,
|
||||
WMI_TLV_TAG_STRUCT_TX_SEND_PARAMS,
|
||||
WMI_TLV_TAG_STRUCT_HE_RATE_SET,
|
||||
WMI_TLV_TAG_STRUCT_CONGESTION_STATS,
|
||||
WMI_TLV_TAG_STRUCT_SET_INIT_COUNTRY_CMD,
|
||||
WMI_TLV_TAG_STRUCT_SCAN_DBS_DUTY_CYCLE,
|
||||
WMI_TLV_TAG_STRUCT_SCAN_DBS_DUTY_CYCLE_PARAM_TLV,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_DIV_GET_RSSI_ANTID,
|
||||
WMI_TLV_TAG_STRUCT_THERM_THROT_CONFIG_REQUEST,
|
||||
WMI_TLV_TAG_STRUCT_THERM_THROT_LEVEL_CONFIG_INFO,
|
||||
WMI_TLV_TAG_STRUCT_THERM_THROT_STATS_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_THERM_THROT_LEVEL_STATS_INFO,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_DIV_RSSI_ANTID_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_OEM_DMA_RING_CAPABILITIES,
|
||||
WMI_TLV_TAG_STRUCT_OEM_DMA_RING_CFG_REQ,
|
||||
WMI_TLV_TAG_STRUCT_OEM_DMA_RING_CFG_RSP,
|
||||
WMI_TLV_TAG_STRUCT_OEM_INDIRECT_DATA,
|
||||
WMI_TLV_TAG_STRUCT_OEM_DMA_BUF_RELEASE,
|
||||
WMI_TLV_TAG_STRUCT_OEM_DMA_BUF_RELEASE_ENTRY,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_BSS_CHAN_INFO_REQUEST,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_BSS_CHAN_INFO_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_ROAM_LCA_DISALLOW_CONFIG_TLV_PARAM,
|
||||
WMI_TLV_TAG_STRUCT_VDEV_LIMIT_OFFCHAN_CMD,
|
||||
WMI_TLV_TAG_STRUCT_ROAM_RSSI_REJECTION_OCE_CONFIG_PARAM,
|
||||
WMI_TLV_TAG_STRUCT_UNIT_TEST_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_ROAM_FILS_OFFLOAD_TLV_PARAM,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_UPDATE_PMK_CACHE_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PMK_CACHE,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_UPDATE_FILS_HLP_PKT_CMD,
|
||||
WMI_TLV_TAG_STRUCT_ROAM_FILS_SYNCH_TLV_PARAM,
|
||||
WMI_TLV_TAG_STRUCT_GTK_OFFLOAD_EXTENDED_TLV_PARAM,
|
||||
WMI_TLV_TAG_STRUCT_ROAM_BG_SCAN_ROAMING_PARAM,
|
||||
WMI_TLV_TAG_STRUCT_OIC_PING_OFFLOAD_PARAMS_CMD,
|
||||
WMI_TLV_TAG_STRUCT_OIC_PING_OFFLOAD_SET_ENABLE_CMD,
|
||||
WMI_TLV_TAG_STRUCT_OIC_PING_HANDOFF_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_DHCP_LEASE_RENEW_OFFLOAD_CMD,
|
||||
WMI_TLV_TAG_STRUCT_DHCP_LEASE_RENEW_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_BTM_CONFIG,
|
||||
WMI_TLV_TAG_STRUCT_DEBUG_MESG_FW_DATA_STALL_PARAM,
|
||||
WMI_TLV_TAG_STRUCT_WLM_CONFIG_CMD,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_UPDATE_CTLTABLE_REQUEST,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_UPDATE_CTLTABLE_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_ROAM_CND_SCORING_PARAM,
|
||||
WMI_TLV_TAG_STRUCT_PDEV_CONFIG_VENDOR_OUI_ACTION,
|
||||
WMI_TLV_TAG_STRUCT_VENDOR_OUI_EXT,
|
||||
WMI_TLV_TAG_STRUCT_ROAM_SYNCH_FRAME_EVENT,
|
||||
WMI_TLV_TAG_STRUCT_FD_SEND_FROM_HOST_CMD,
|
||||
WMI_TLV_TAG_STRUCT_ENABLE_FILS_CMD,
|
||||
WMI_TLV_TAG_STRUCT_HOST_SWFDA_EVENT,
|
||||
|
||||
WMI_TLV_TAG_MAX
|
||||
};
|
||||
|
@ -1068,16 +1338,74 @@ enum wmi_tlv_service {
|
|||
WMI_TLV_SERVICE_WLAN_STATS_REPORT,
|
||||
WMI_TLV_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT,
|
||||
WMI_TLV_SERVICE_DFS_PHYERR_OFFLOAD,
|
||||
WMI_TLV_SERVICE_RCPI_SUPPORT,
|
||||
WMI_TLV_SERVICE_FW_MEM_DUMP_SUPPORT,
|
||||
WMI_TLV_SERVICE_PEER_STATS_INFO,
|
||||
WMI_TLV_SERVICE_REGULATORY_DB,
|
||||
WMI_TLV_SERVICE_11D_OFFLOAD,
|
||||
WMI_TLV_SERVICE_HW_DATA_FILTERING,
|
||||
WMI_TLV_SERVICE_MULTIPLE_VDEV_RESTART,
|
||||
WMI_TLV_SERVICE_PKT_ROUTING,
|
||||
WMI_TLV_SERVICE_CHECK_CAL_VERSION,
|
||||
WMI_TLV_SERVICE_OFFCHAN_TX_WMI,
|
||||
WMI_TLV_SERVICE_8SS_TX_BFEE,
|
||||
WMI_TLV_SERVICE_EXTENDED_NSS_SUPPORT,
|
||||
WMI_TLV_SERVICE_ACK_TIMEOUT,
|
||||
WMI_TLV_SERVICE_PDEV_BSS_CHANNEL_INFO_64,
|
||||
WMI_TLV_MAX_SERVICE = 128,
|
||||
|
||||
/* NOTE:
|
||||
* The above service flags are delivered in the wmi_service_bitmap field
|
||||
* of the WMI_TLV_SERVICE_READY_EVENT message.
|
||||
* The below service flags are delivered in a WMI_TLV_SERVICE_AVAILABLE_EVENT
|
||||
* message rather than in the WMI_TLV_SERVICE_READY_EVENT message's
|
||||
* wmi_service_bitmap field.
|
||||
* The WMI_TLV_SERVICE_AVAILABLE_EVENT message immediately precedes the
|
||||
* WMI_TLV_SERVICE_READY_EVENT message.
|
||||
*/
|
||||
|
||||
WMI_TLV_SERVICE_CHAN_LOAD_INFO = 128,
|
||||
WMI_TLV_SERVICE_TX_PPDU_INFO_STATS_SUPPORT,
|
||||
WMI_TLV_SERVICE_VDEV_LIMIT_OFFCHAN_SUPPORT,
|
||||
WMI_TLV_SERVICE_FILS_SUPPORT,
|
||||
WMI_TLV_SERVICE_WLAN_OIC_PING_OFFLOAD,
|
||||
WMI_TLV_SERVICE_WLAN_DHCP_RENEW,
|
||||
WMI_TLV_SERVICE_MAWC_SUPPORT,
|
||||
WMI_TLV_SERVICE_VDEV_LATENCY_CONFIG,
|
||||
WMI_TLV_SERVICE_PDEV_UPDATE_CTLTABLE_SUPPORT,
|
||||
WMI_TLV_SERVICE_PKTLOG_SUPPORT_OVER_HTT,
|
||||
WMI_TLV_SERVICE_VDEV_MULTI_GROUP_KEY_SUPPORT,
|
||||
WMI_TLV_SERVICE_SCAN_PHYMODE_SUPPORT,
|
||||
WMI_TLV_SERVICE_THERM_THROT,
|
||||
WMI_TLV_SERVICE_BCN_OFFLOAD_START_STOP_SUPPORT,
|
||||
WMI_TLV_SERVICE_WOW_WAKEUP_BY_TIMER_PATTERN,
|
||||
WMI_TLV_SERVICE_PEER_MAP_UNMAP_V2_SUPPORT = 143,
|
||||
WMI_TLV_SERVICE_OFFCHAN_DATA_TID_SUPPORT = 144,
|
||||
WMI_TLV_SERVICE_RX_PROMISC_ENABLE_SUPPORT = 145,
|
||||
WMI_TLV_SERVICE_SUPPORT_DIRECT_DMA = 146,
|
||||
WMI_TLV_SERVICE_AP_OBSS_DETECTION_OFFLOAD = 147,
|
||||
WMI_TLV_SERVICE_11K_NEIGHBOUR_REPORT_SUPPORT = 148,
|
||||
WMI_TLV_SERVICE_LISTEN_INTERVAL_OFFLOAD_SUPPORT = 149,
|
||||
WMI_TLV_SERVICE_BSS_COLOR_OFFLOAD = 150,
|
||||
WMI_TLV_SERVICE_RUNTIME_DPD_RECAL = 151,
|
||||
WMI_TLV_SERVICE_STA_TWT = 152,
|
||||
WMI_TLV_SERVICE_AP_TWT = 153,
|
||||
WMI_TLV_SERVICE_GMAC_OFFLOAD_SUPPORT = 154,
|
||||
WMI_TLV_SERVICE_SPOOF_MAC_SUPPORT = 155,
|
||||
|
||||
WMI_TLV_MAX_EXT_SERVICE = 256,
|
||||
};
|
||||
|
||||
#define WMI_SERVICE_IS_ENABLED(wmi_svc_bmap, svc_id, len) \
|
||||
((svc_id) < (len) && \
|
||||
__le32_to_cpu((wmi_svc_bmap)[(svc_id) / (sizeof(u32))]) & \
|
||||
BIT((svc_id) % (sizeof(u32))))
|
||||
#define WMI_TLV_EXT_SERVICE_IS_ENABLED(wmi_svc_bmap, svc_id, len) \
|
||||
((svc_id) < (WMI_TLV_MAX_EXT_SERVICE) && \
|
||||
(svc_id) >= (len) && \
|
||||
__le32_to_cpu((wmi_svc_bmap)[((svc_id) - (len)) / 32]) & \
|
||||
BIT(((((svc_id) - (len)) % 32) & 0x1f)))
|
||||
|
||||
#define SVCMAP(x, y, len) \
|
||||
do { \
|
||||
if (WMI_SERVICE_IS_ENABLED((in), (x), (len))) \
|
||||
if ((WMI_SERVICE_IS_ENABLED((in), (x), (len))) || \
|
||||
(WMI_TLV_EXT_SERVICE_IS_ENABLED((in), (x), (len)))) \
|
||||
__set_bit(y, out); \
|
||||
} while (0)
|
||||
|
||||
|
@ -1228,6 +1556,14 @@ wmi_tlv_svc_map(const __le32 *in, unsigned long *out, size_t len)
|
|||
WMI_SERVICE_MGMT_TX_WMI, len);
|
||||
}
|
||||
|
||||
static inline void
|
||||
wmi_tlv_svc_map_ext(const __le32 *in, unsigned long *out, size_t len)
|
||||
{
|
||||
SVCMAP(WMI_TLV_SERVICE_SPOOF_MAC_SUPPORT,
|
||||
WMI_SERVICE_SPOOF_MAC_SUPPORT,
|
||||
WMI_TLV_MAX_SERVICE);
|
||||
}
|
||||
|
||||
#undef SVCMAP
|
||||
|
||||
struct wmi_tlv {
|
||||
|
@ -1370,6 +1706,15 @@ struct wmi_tlv_scan_chan_list_cmd {
|
|||
__le32 num_scan_chans;
|
||||
} __packed;
|
||||
|
||||
struct wmi_scan_prob_req_oui_cmd {
|
||||
/* OUI to be used in Probe Request frame when random MAC address is
|
||||
* requested part of scan parameters. This is applied to both FW internal
|
||||
* scans and host initiated scans. Host can request for random MAC address
|
||||
* with WMI_SCAN_ADD_SPOOFED_MAC_IN_PROBE_REQ flag.
|
||||
*/
|
||||
__le32 prob_req_oui;
|
||||
} __packed;
|
||||
|
||||
struct wmi_tlv_start_scan_cmd {
|
||||
struct wmi_start_scan_common common;
|
||||
__le32 burst_duration_ms;
|
||||
|
@ -1378,6 +1723,8 @@ struct wmi_tlv_start_scan_cmd {
|
|||
__le32 num_ssids;
|
||||
__le32 ie_len;
|
||||
__le32 num_probes;
|
||||
struct wmi_mac_addr mac_addr;
|
||||
struct wmi_mac_addr mac_mask;
|
||||
} __packed;
|
||||
|
||||
struct wmi_tlv_vdev_start_cmd {
|
||||
|
|
|
@ -42,6 +42,7 @@ static struct wmi_cmd_map wmi_cmd_map = {
|
|||
.stop_scan_cmdid = WMI_STOP_SCAN_CMDID,
|
||||
.scan_chan_list_cmdid = WMI_SCAN_CHAN_LIST_CMDID,
|
||||
.scan_sch_prio_tbl_cmdid = WMI_SCAN_SCH_PRIO_TBL_CMDID,
|
||||
.scan_prob_req_oui_cmdid = WMI_CMD_UNSUPPORTED,
|
||||
.pdev_set_regdomain_cmdid = WMI_PDEV_SET_REGDOMAIN_CMDID,
|
||||
.pdev_set_channel_cmdid = WMI_PDEV_SET_CHANNEL_CMDID,
|
||||
.pdev_set_param_cmdid = WMI_PDEV_SET_PARAM_CMDID,
|
||||
|
@ -207,6 +208,7 @@ static struct wmi_cmd_map wmi_10x_cmd_map = {
|
|||
.stop_scan_cmdid = WMI_10X_STOP_SCAN_CMDID,
|
||||
.scan_chan_list_cmdid = WMI_10X_SCAN_CHAN_LIST_CMDID,
|
||||
.scan_sch_prio_tbl_cmdid = WMI_CMD_UNSUPPORTED,
|
||||
.scan_prob_req_oui_cmdid = WMI_CMD_UNSUPPORTED,
|
||||
.pdev_set_regdomain_cmdid = WMI_10X_PDEV_SET_REGDOMAIN_CMDID,
|
||||
.pdev_set_channel_cmdid = WMI_10X_PDEV_SET_CHANNEL_CMDID,
|
||||
.pdev_set_param_cmdid = WMI_10X_PDEV_SET_PARAM_CMDID,
|
||||
|
@ -374,6 +376,7 @@ static struct wmi_cmd_map wmi_10_2_4_cmd_map = {
|
|||
.stop_scan_cmdid = WMI_10_2_STOP_SCAN_CMDID,
|
||||
.scan_chan_list_cmdid = WMI_10_2_SCAN_CHAN_LIST_CMDID,
|
||||
.scan_sch_prio_tbl_cmdid = WMI_CMD_UNSUPPORTED,
|
||||
.scan_prob_req_oui_cmdid = WMI_CMD_UNSUPPORTED,
|
||||
.pdev_set_regdomain_cmdid = WMI_10_2_PDEV_SET_REGDOMAIN_CMDID,
|
||||
.pdev_set_channel_cmdid = WMI_10_2_PDEV_SET_CHANNEL_CMDID,
|
||||
.pdev_set_param_cmdid = WMI_10_2_PDEV_SET_PARAM_CMDID,
|
||||
|
@ -541,6 +544,7 @@ static struct wmi_cmd_map wmi_10_4_cmd_map = {
|
|||
.stop_scan_cmdid = WMI_10_4_STOP_SCAN_CMDID,
|
||||
.scan_chan_list_cmdid = WMI_10_4_SCAN_CHAN_LIST_CMDID,
|
||||
.scan_sch_prio_tbl_cmdid = WMI_10_4_SCAN_SCH_PRIO_TBL_CMDID,
|
||||
.scan_prob_req_oui_cmdid = WMI_CMD_UNSUPPORTED,
|
||||
.pdev_set_regdomain_cmdid = WMI_10_4_PDEV_SET_REGDOMAIN_CMDID,
|
||||
.pdev_set_channel_cmdid = WMI_10_4_PDEV_SET_CHANNEL_CMDID,
|
||||
.pdev_set_param_cmdid = WMI_10_4_PDEV_SET_PARAM_CMDID,
|
||||
|
@ -1338,6 +1342,7 @@ static struct wmi_cmd_map wmi_10_2_cmd_map = {
|
|||
.stop_scan_cmdid = WMI_10_2_STOP_SCAN_CMDID,
|
||||
.scan_chan_list_cmdid = WMI_10_2_SCAN_CHAN_LIST_CMDID,
|
||||
.scan_sch_prio_tbl_cmdid = WMI_CMD_UNSUPPORTED,
|
||||
.scan_prob_req_oui_cmdid = WMI_CMD_UNSUPPORTED,
|
||||
.pdev_set_regdomain_cmdid = WMI_10_2_PDEV_SET_REGDOMAIN_CMDID,
|
||||
.pdev_set_channel_cmdid = WMI_10_2_PDEV_SET_CHANNEL_CMDID,
|
||||
.pdev_set_param_cmdid = WMI_10_2_PDEV_SET_PARAM_CMDID,
|
||||
|
@ -4357,7 +4362,7 @@ static void ath10k_tpc_config_disp_tables(struct ath10k *ar,
|
|||
rate_code[i],
|
||||
type);
|
||||
snprintf(buff, sizeof(buff), "%8d ", tpc[j]);
|
||||
strncat(tpc_value, buff, strlen(buff));
|
||||
strlcat(tpc_value, buff, sizeof(tpc_value));
|
||||
}
|
||||
tpc_stats->tpc_table[type].pream_idx[i] = pream_idx;
|
||||
tpc_stats->tpc_table[type].rate_code[i] = rate_code[i];
|
||||
|
@ -4694,7 +4699,7 @@ ath10k_wmi_tpc_stats_final_disp_tables(struct ath10k *ar,
|
|||
rate_code[i],
|
||||
type, pream_idx);
|
||||
snprintf(buff, sizeof(buff), "%8d ", tpc[j]);
|
||||
strncat(tpc_value, buff, strlen(buff));
|
||||
strlcat(tpc_value, buff, sizeof(tpc_value));
|
||||
}
|
||||
tpc_stats->tpc_table_final[type].pream_idx[i] = pream_idx;
|
||||
tpc_stats->tpc_table_final[type].rate_code[i] = rate_code[i];
|
||||
|
@ -5059,7 +5064,6 @@ static void ath10k_wmi_event_service_ready_work(struct work_struct *work)
|
|||
return;
|
||||
}
|
||||
|
||||
memset(&ar->wmi.svc_map, 0, sizeof(ar->wmi.svc_map));
|
||||
ath10k_wmi_map_svc(ar, arg.service_map, ar->wmi.svc_map,
|
||||
arg.service_map_len);
|
||||
|
||||
|
@ -5269,6 +5273,21 @@ int ath10k_wmi_event_ready(struct ath10k *ar, struct sk_buff *skb)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void ath10k_wmi_event_service_available(struct ath10k *ar, struct sk_buff *skb)
|
||||
{
|
||||
int ret;
|
||||
struct wmi_svc_avail_ev_arg arg = {};
|
||||
|
||||
ret = ath10k_wmi_pull_svc_avail(ar, skb, &arg);
|
||||
if (ret) {
|
||||
ath10k_warn(ar, "failed to parse servive available event: %d\n",
|
||||
ret);
|
||||
}
|
||||
|
||||
ath10k_wmi_map_svc_ext(ar, arg.service_map_ext, ar->wmi.svc_map,
|
||||
__le32_to_cpu(arg.service_map_ext_len));
|
||||
}
|
||||
|
||||
static int ath10k_wmi_event_temperature(struct ath10k *ar, struct sk_buff *skb)
|
||||
{
|
||||
const struct wmi_pdev_temperature_event *ev;
|
||||
|
@ -5465,6 +5484,9 @@ static void ath10k_wmi_op_rx(struct ath10k *ar, struct sk_buff *skb)
|
|||
ath10k_wmi_event_ready(ar, skb);
|
||||
ath10k_wmi_queue_set_coverage_class_work(ar);
|
||||
break;
|
||||
case WMI_SERVICE_AVAILABLE_EVENTID:
|
||||
ath10k_wmi_event_service_available(ar, skb);
|
||||
break;
|
||||
default:
|
||||
ath10k_warn(ar, "Unknown eventid: %d\n", id);
|
||||
break;
|
||||
|
@ -5880,6 +5902,8 @@ int ath10k_wmi_connect(struct ath10k *ar)
|
|||
struct ath10k_htc_svc_conn_req conn_req;
|
||||
struct ath10k_htc_svc_conn_resp conn_resp;
|
||||
|
||||
memset(&ar->wmi.svc_map, 0, sizeof(ar->wmi.svc_map));
|
||||
|
||||
memset(&conn_req, 0, sizeof(conn_req));
|
||||
memset(&conn_resp, 0, sizeof(conn_resp));
|
||||
|
||||
|
@ -7648,7 +7672,7 @@ ath10k_wmi_10_2_4_op_gen_pdev_get_tpc_config(struct ath10k *ar, u32 param)
|
|||
cmd->param = __cpu_to_le32(param);
|
||||
|
||||
ath10k_dbg(ar, ATH10K_DBG_WMI,
|
||||
"wmi pdev get tcp config param:%d\n", param);
|
||||
"wmi pdev get tpc config param %d\n", param);
|
||||
return skb;
|
||||
}
|
||||
|
||||
|
@ -7768,7 +7792,7 @@ ath10k_wmi_fw_pdev_tx_stats_fill(const struct ath10k_fw_stats_pdev *pdev,
|
|||
len += scnprintf(buf + len, buf_len - len, "%30s %10d\n",
|
||||
"HW rate", pdev->data_rc);
|
||||
len += scnprintf(buf + len, buf_len - len, "%30s %10d\n",
|
||||
"Sched self tiggers", pdev->self_triggers);
|
||||
"Sched self triggers", pdev->self_triggers);
|
||||
len += scnprintf(buf + len, buf_len - len, "%30s %10d\n",
|
||||
"Dropped due to SW retries",
|
||||
pdev->sw_retry_failure);
|
||||
|
|
|
@ -201,6 +201,8 @@ enum wmi_service {
|
|||
WMI_SERVICE_HTT_MGMT_TX_COMP_VALID_FLAGS,
|
||||
WMI_SERVICE_HOST_DFS_CHECK_SUPPORT,
|
||||
WMI_SERVICE_TPC_STATS_FINAL,
|
||||
WMI_SERVICE_RESET_CHIP,
|
||||
WMI_SERVICE_SPOOF_MAC_SUPPORT,
|
||||
|
||||
/* keep last */
|
||||
WMI_SERVICE_MAX,
|
||||
|
@ -238,6 +240,8 @@ enum wmi_10x_service {
|
|||
WMI_10X_SERVICE_MESH,
|
||||
WMI_10X_SERVICE_EXT_RES_CFG_SUPPORT,
|
||||
WMI_10X_SERVICE_PEER_STATS,
|
||||
WMI_10X_SERVICE_RESET_CHIP,
|
||||
WMI_10X_SERVICE_HTT_MGMT_TX_COMP_VALID_FLAGS,
|
||||
};
|
||||
|
||||
enum wmi_main_service {
|
||||
|
@ -548,6 +552,10 @@ static inline void wmi_10x_svc_map(const __le32 *in, unsigned long *out,
|
|||
WMI_SERVICE_EXT_RES_CFG_SUPPORT, len);
|
||||
SVCMAP(WMI_10X_SERVICE_PEER_STATS,
|
||||
WMI_SERVICE_PEER_STATS, len);
|
||||
SVCMAP(WMI_10X_SERVICE_RESET_CHIP,
|
||||
WMI_SERVICE_RESET_CHIP, len);
|
||||
SVCMAP(WMI_10X_SERVICE_HTT_MGMT_TX_COMP_VALID_FLAGS,
|
||||
WMI_SERVICE_HTT_MGMT_TX_COMP_VALID_FLAGS, len);
|
||||
}
|
||||
|
||||
static inline void wmi_main_svc_map(const __le32 *in, unsigned long *out,
|
||||
|
@ -783,6 +791,7 @@ struct wmi_cmd_map {
|
|||
u32 stop_scan_cmdid;
|
||||
u32 scan_chan_list_cmdid;
|
||||
u32 scan_sch_prio_tbl_cmdid;
|
||||
u32 scan_prob_req_oui_cmdid;
|
||||
u32 pdev_set_regdomain_cmdid;
|
||||
u32 pdev_set_channel_cmdid;
|
||||
u32 pdev_set_param_cmdid;
|
||||
|
@ -1183,6 +1192,7 @@ enum wmi_cmd_id {
|
|||
enum wmi_event_id {
|
||||
WMI_SERVICE_READY_EVENTID = 0x1,
|
||||
WMI_READY_EVENTID,
|
||||
WMI_SERVICE_AVAILABLE_EVENTID,
|
||||
|
||||
/* Scan specific events */
|
||||
WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN),
|
||||
|
@ -3159,6 +3169,8 @@ struct wmi_start_scan_arg {
|
|||
u16 channels[64];
|
||||
struct wmi_ssid_arg ssids[WLAN_SCAN_PARAMS_MAX_SSID];
|
||||
struct wmi_bssid_arg bssids[WLAN_SCAN_PARAMS_MAX_BSSID];
|
||||
struct wmi_mac_addr mac_addr;
|
||||
struct wmi_mac_addr mac_mask;
|
||||
};
|
||||
|
||||
/* scan control flags */
|
||||
|
@ -3182,6 +3194,12 @@ struct wmi_start_scan_arg {
|
|||
*/
|
||||
#define WMI_SCAN_CONTINUE_ON_ERROR 0x80
|
||||
|
||||
/* Use random MAC address for TA for Probe Request frame and add
|
||||
* OUI specified by WMI_SCAN_PROB_REQ_OUI_CMDID to the Probe Request frame.
|
||||
* if OUI is not set by WMI_SCAN_PROB_REQ_OUI_CMDID then the flag is ignored.
|
||||
*/
|
||||
#define WMI_SCAN_ADD_SPOOFED_MAC_IN_PROBE_REQ 0x1000
|
||||
|
||||
/* WMI_SCAN_CLASS_MASK must be the same value as IEEE80211_SCAN_CLASS_MASK */
|
||||
#define WMI_SCAN_CLASS_MASK 0xFF000000
|
||||
|
||||
|
@ -6632,6 +6650,11 @@ struct wmi_svc_rdy_ev_arg {
|
|||
const struct wlan_host_mem_req *mem_reqs[WMI_MAX_MEM_REQS];
|
||||
};
|
||||
|
||||
struct wmi_svc_avail_ev_arg {
|
||||
__le32 service_map_ext_len;
|
||||
const __le32 *service_map_ext;
|
||||
};
|
||||
|
||||
struct wmi_rdy_ev_arg {
|
||||
__le32 sw_version;
|
||||
__le32 abi_version;
|
||||
|
@ -6812,6 +6835,10 @@ struct wmi_wow_ev_arg {
|
|||
#define WOW_MIN_PATTERN_SIZE 1
|
||||
#define WOW_MAX_PATTERN_SIZE 148
|
||||
#define WOW_MAX_PKT_OFFSET 128
|
||||
#define WOW_HDR_LEN (sizeof(struct ieee80211_hdr_3addr) + \
|
||||
sizeof(struct rfc1042_hdr))
|
||||
#define WOW_MAX_REDUCE (WOW_HDR_LEN - sizeof(struct ethhdr) - \
|
||||
offsetof(struct ieee80211_hdr_3addr, addr1))
|
||||
|
||||
enum wmi_tdls_state {
|
||||
WMI_TDLS_DISABLE,
|
||||
|
@ -7052,6 +7079,7 @@ void ath10k_wmi_event_vdev_standby_req(struct ath10k *ar, struct sk_buff *skb);
|
|||
void ath10k_wmi_event_vdev_resume_req(struct ath10k *ar, struct sk_buff *skb);
|
||||
void ath10k_wmi_event_service_ready(struct ath10k *ar, struct sk_buff *skb);
|
||||
int ath10k_wmi_event_ready(struct ath10k *ar, struct sk_buff *skb);
|
||||
void ath10k_wmi_event_service_available(struct ath10k *ar, struct sk_buff *skb);
|
||||
int ath10k_wmi_op_pull_phyerr_ev(struct ath10k *ar, const void *phyerr_buf,
|
||||
int left_len, struct wmi_phyerr_ev_arg *arg);
|
||||
void ath10k_wmi_main_op_fw_stats_fill(struct ath10k *ar,
|
||||
|
|
|
@ -1,5 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017 Qualcomm Atheros, Inc.
|
||||
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
|
@ -76,6 +77,109 @@ static int ath10k_wow_cleanup(struct ath10k *ar)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert a 802.3 format to a 802.11 format.
|
||||
* +------------+-----------+--------+----------------+
|
||||
* 802.3: |dest mac(6B)|src mac(6B)|type(2B)| body... |
|
||||
* +------------+-----------+--------+----------------+
|
||||
* |__ |_______ |____________ |________
|
||||
* | | | |
|
||||
* +--+------------+----+-----------+---------------+-----------+
|
||||
* 802.11: |4B|dest mac(6B)| 6B |src mac(6B)| 8B |type(2B)| body... |
|
||||
* +--+------------+----+-----------+---------------+-----------+
|
||||
*/
|
||||
static void ath10k_wow_convert_8023_to_80211
|
||||
(struct cfg80211_pkt_pattern *new,
|
||||
const struct cfg80211_pkt_pattern *old)
|
||||
{
|
||||
u8 hdr_8023_pattern[ETH_HLEN] = {};
|
||||
u8 hdr_8023_bit_mask[ETH_HLEN] = {};
|
||||
u8 hdr_80211_pattern[WOW_HDR_LEN] = {};
|
||||
u8 hdr_80211_bit_mask[WOW_HDR_LEN] = {};
|
||||
|
||||
int total_len = old->pkt_offset + old->pattern_len;
|
||||
int hdr_80211_end_offset;
|
||||
|
||||
struct ieee80211_hdr_3addr *new_hdr_pattern =
|
||||
(struct ieee80211_hdr_3addr *)hdr_80211_pattern;
|
||||
struct ieee80211_hdr_3addr *new_hdr_mask =
|
||||
(struct ieee80211_hdr_3addr *)hdr_80211_bit_mask;
|
||||
struct ethhdr *old_hdr_pattern = (struct ethhdr *)hdr_8023_pattern;
|
||||
struct ethhdr *old_hdr_mask = (struct ethhdr *)hdr_8023_bit_mask;
|
||||
int hdr_len = sizeof(*new_hdr_pattern);
|
||||
|
||||
struct rfc1042_hdr *new_rfc_pattern =
|
||||
(struct rfc1042_hdr *)(hdr_80211_pattern + hdr_len);
|
||||
struct rfc1042_hdr *new_rfc_mask =
|
||||
(struct rfc1042_hdr *)(hdr_80211_bit_mask + hdr_len);
|
||||
int rfc_len = sizeof(*new_rfc_pattern);
|
||||
|
||||
memcpy(hdr_8023_pattern + old->pkt_offset,
|
||||
old->pattern, ETH_HLEN - old->pkt_offset);
|
||||
memcpy(hdr_8023_bit_mask + old->pkt_offset,
|
||||
old->mask, ETH_HLEN - old->pkt_offset);
|
||||
|
||||
/* Copy destination address */
|
||||
memcpy(new_hdr_pattern->addr1, old_hdr_pattern->h_dest, ETH_ALEN);
|
||||
memcpy(new_hdr_mask->addr1, old_hdr_mask->h_dest, ETH_ALEN);
|
||||
|
||||
/* Copy source address */
|
||||
memcpy(new_hdr_pattern->addr3, old_hdr_pattern->h_source, ETH_ALEN);
|
||||
memcpy(new_hdr_mask->addr3, old_hdr_mask->h_source, ETH_ALEN);
|
||||
|
||||
/* Copy logic link type */
|
||||
memcpy(&new_rfc_pattern->snap_type,
|
||||
&old_hdr_pattern->h_proto,
|
||||
sizeof(old_hdr_pattern->h_proto));
|
||||
memcpy(&new_rfc_mask->snap_type,
|
||||
&old_hdr_mask->h_proto,
|
||||
sizeof(old_hdr_mask->h_proto));
|
||||
|
||||
/* Caculate new pkt_offset */
|
||||
if (old->pkt_offset < ETH_ALEN)
|
||||
new->pkt_offset = old->pkt_offset +
|
||||
offsetof(struct ieee80211_hdr_3addr, addr1);
|
||||
else if (old->pkt_offset < offsetof(struct ethhdr, h_proto))
|
||||
new->pkt_offset = old->pkt_offset +
|
||||
offsetof(struct ieee80211_hdr_3addr, addr3) -
|
||||
offsetof(struct ethhdr, h_source);
|
||||
else
|
||||
new->pkt_offset = old->pkt_offset + hdr_len + rfc_len - ETH_HLEN;
|
||||
|
||||
/* Caculate new hdr end offset */
|
||||
if (total_len > ETH_HLEN)
|
||||
hdr_80211_end_offset = hdr_len + rfc_len;
|
||||
else if (total_len > offsetof(struct ethhdr, h_proto))
|
||||
hdr_80211_end_offset = hdr_len + rfc_len + total_len - ETH_HLEN;
|
||||
else if (total_len > ETH_ALEN)
|
||||
hdr_80211_end_offset = total_len - ETH_ALEN +
|
||||
offsetof(struct ieee80211_hdr_3addr, addr3);
|
||||
else
|
||||
hdr_80211_end_offset = total_len +
|
||||
offsetof(struct ieee80211_hdr_3addr, addr1);
|
||||
|
||||
new->pattern_len = hdr_80211_end_offset - new->pkt_offset;
|
||||
|
||||
memcpy((u8 *)new->pattern,
|
||||
hdr_80211_pattern + new->pkt_offset,
|
||||
new->pattern_len);
|
||||
memcpy((u8 *)new->mask,
|
||||
hdr_80211_bit_mask + new->pkt_offset,
|
||||
new->pattern_len);
|
||||
|
||||
if (total_len > ETH_HLEN) {
|
||||
/* Copy frame body */
|
||||
memcpy((u8 *)new->pattern + new->pattern_len,
|
||||
(void *)old->pattern + ETH_HLEN - old->pkt_offset,
|
||||
total_len - ETH_HLEN);
|
||||
memcpy((u8 *)new->mask + new->pattern_len,
|
||||
(void *)old->mask + ETH_HLEN - old->pkt_offset,
|
||||
total_len - ETH_HLEN);
|
||||
|
||||
new->pattern_len += total_len - ETH_HLEN;
|
||||
}
|
||||
}
|
||||
|
||||
static int ath10k_vif_wow_set_wakeups(struct ath10k_vif *arvif,
|
||||
struct cfg80211_wowlan *wowlan)
|
||||
{
|
||||
|
@ -116,22 +220,40 @@ static int ath10k_vif_wow_set_wakeups(struct ath10k_vif *arvif,
|
|||
|
||||
for (i = 0; i < wowlan->n_patterns; i++) {
|
||||
u8 bitmask[WOW_MAX_PATTERN_SIZE] = {};
|
||||
u8 ath_pattern[WOW_MAX_PATTERN_SIZE] = {};
|
||||
u8 ath_bitmask[WOW_MAX_PATTERN_SIZE] = {};
|
||||
struct cfg80211_pkt_pattern new_pattern = {};
|
||||
struct cfg80211_pkt_pattern old_pattern = patterns[i];
|
||||
int j;
|
||||
|
||||
new_pattern.pattern = ath_pattern;
|
||||
new_pattern.mask = ath_bitmask;
|
||||
if (patterns[i].pattern_len > WOW_MAX_PATTERN_SIZE)
|
||||
continue;
|
||||
|
||||
/* convert bytemask to bitmask */
|
||||
for (j = 0; j < patterns[i].pattern_len; j++)
|
||||
if (patterns[i].mask[j / 8] & BIT(j % 8))
|
||||
bitmask[j] = 0xff;
|
||||
old_pattern.mask = bitmask;
|
||||
new_pattern = old_pattern;
|
||||
|
||||
if (ar->wmi.rx_decap_mode == ATH10K_HW_TXRX_NATIVE_WIFI) {
|
||||
if (patterns[i].pkt_offset < ETH_HLEN)
|
||||
ath10k_wow_convert_8023_to_80211(&new_pattern,
|
||||
&old_pattern);
|
||||
else
|
||||
new_pattern.pkt_offset += WOW_HDR_LEN - ETH_HLEN;
|
||||
}
|
||||
|
||||
if (WARN_ON(new_pattern.pattern_len > WOW_MAX_PATTERN_SIZE))
|
||||
return -EINVAL;
|
||||
|
||||
ret = ath10k_wmi_wow_add_pattern(ar, arvif->vdev_id,
|
||||
pattern_id,
|
||||
patterns[i].pattern,
|
||||
bitmask,
|
||||
patterns[i].pattern_len,
|
||||
patterns[i].pkt_offset);
|
||||
new_pattern.pattern,
|
||||
new_pattern.mask,
|
||||
new_pattern.pattern_len,
|
||||
new_pattern.pkt_offset);
|
||||
if (ret) {
|
||||
ath10k_warn(ar, "failed to add pattern %i to vdev %i: %d\n",
|
||||
pattern_id,
|
||||
|
@ -345,6 +467,12 @@ int ath10k_wow_init(struct ath10k *ar)
|
|||
return -EINVAL;
|
||||
|
||||
ar->wow.wowlan_support = ath10k_wowlan_support;
|
||||
|
||||
if (ar->wmi.rx_decap_mode == ATH10K_HW_TXRX_NATIVE_WIFI) {
|
||||
ar->wow.wowlan_support.pattern_max_len -= WOW_MAX_REDUCE;
|
||||
ar->wow.wowlan_support.max_pkt_offset -= WOW_MAX_REDUCE;
|
||||
}
|
||||
|
||||
ar->wow.wowlan_support.n_patterns = ar->wow.max_num_patterns;
|
||||
ar->hw->wiphy->wowlan = &ar->wow.wowlan_support;
|
||||
|
||||
|
|
|
@ -645,7 +645,7 @@ static ssize_t read_file_tgt_stats(struct file *file, char __user *user_buf,
|
|||
len += scnprintf(buf + len, buf_len - len, "%20s %10llu\n",
|
||||
"CRC Err", tgt_stats->rx_crc_err);
|
||||
len += scnprintf(buf + len, buf_len - len, "%20s %10llu\n",
|
||||
"Key chache miss", tgt_stats->rx_key_cache_miss);
|
||||
"Key cache miss", tgt_stats->rx_key_cache_miss);
|
||||
len += scnprintf(buf + len, buf_len - len, "%20s %10llu\n",
|
||||
"Decrypt Err", tgt_stats->rx_decrypt_err);
|
||||
len += scnprintf(buf + len, buf_len - len, "%20s %10llu\n",
|
||||
|
|
|
@ -426,7 +426,7 @@ void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr,
|
|||
{
|
||||
u8 *ies = NULL, *wpa_ie = NULL, *pos;
|
||||
size_t ies_len = 0;
|
||||
struct station_info sinfo;
|
||||
struct station_info *sinfo;
|
||||
|
||||
ath6kl_dbg(ATH6KL_DBG_TRC, "new station %pM aid=%d\n", mac_addr, aid);
|
||||
|
||||
|
@ -482,16 +482,20 @@ void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr,
|
|||
keymgmt, ucipher, auth, apsd_info);
|
||||
|
||||
/* send event to application */
|
||||
memset(&sinfo, 0, sizeof(sinfo));
|
||||
sinfo = kzalloc(sizeof(*sinfo), GFP_KERNEL);
|
||||
if (!sinfo)
|
||||
return;
|
||||
|
||||
/* TODO: sinfo.generation */
|
||||
|
||||
sinfo.assoc_req_ies = ies;
|
||||
sinfo.assoc_req_ies_len = ies_len;
|
||||
sinfo->assoc_req_ies = ies;
|
||||
sinfo->assoc_req_ies_len = ies_len;
|
||||
|
||||
cfg80211_new_sta(vif->ndev, mac_addr, &sinfo, GFP_KERNEL);
|
||||
cfg80211_new_sta(vif->ndev, mac_addr, sinfo, GFP_KERNEL);
|
||||
|
||||
netif_wake_queue(vif->ndev);
|
||||
|
||||
kfree(sinfo);
|
||||
}
|
||||
|
||||
void disconnect_timer_handler(struct timer_list *t)
|
||||
|
|
|
@ -41,7 +41,7 @@ static const int BIN_DELTA_MAX = 10;
|
|||
|
||||
/* we need at least 3 deltas / 4 samples for a reliable chirp detection */
|
||||
#define NUM_DIFFS 3
|
||||
static const int FFT_NUM_SAMPLES = (NUM_DIFFS + 1);
|
||||
#define FFT_NUM_SAMPLES (NUM_DIFFS + 1)
|
||||
|
||||
/* Threshold for difference of delta peaks */
|
||||
static const int MAX_DIFF = 2;
|
||||
|
@ -114,7 +114,7 @@ static bool ath9k_check_chirping(struct ath_softc *sc, u8 *data,
|
|||
|
||||
ath_dbg(common, DFS, "HT40: datalen=%d, num_fft_packets=%d\n",
|
||||
datalen, num_fft_packets);
|
||||
if (num_fft_packets < (FFT_NUM_SAMPLES)) {
|
||||
if (num_fft_packets < FFT_NUM_SAMPLES) {
|
||||
ath_dbg(common, DFS, "not enough packets for chirp\n");
|
||||
return false;
|
||||
}
|
||||
|
@ -136,7 +136,7 @@ static bool ath9k_check_chirping(struct ath_softc *sc, u8 *data,
|
|||
return false;
|
||||
ath_dbg(common, DFS, "HT20: datalen=%d, num_fft_packets=%d\n",
|
||||
datalen, num_fft_packets);
|
||||
if (num_fft_packets < (FFT_NUM_SAMPLES)) {
|
||||
if (num_fft_packets < FFT_NUM_SAMPLES) {
|
||||
ath_dbg(common, DFS, "not enough packets for chirp\n");
|
||||
return false;
|
||||
}
|
||||
|
|
|
@ -78,7 +78,6 @@ static int wcn36xx_dxe_allocate_ctl_block(struct wcn36xx_dxe_ch *ch)
|
|||
if (!cur_ctl)
|
||||
goto out_fail;
|
||||
|
||||
spin_lock_init(&cur_ctl->skb_lock);
|
||||
cur_ctl->ctl_blk_order = i;
|
||||
if (i == 0) {
|
||||
ch->head_blk_ctl = cur_ctl;
|
||||
|
@ -275,12 +274,14 @@ static int wcn36xx_dxe_enable_ch_int(struct wcn36xx *wcn, u16 wcn_ch)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int wcn36xx_dxe_fill_skb(struct device *dev, struct wcn36xx_dxe_ctl *ctl)
|
||||
static int wcn36xx_dxe_fill_skb(struct device *dev,
|
||||
struct wcn36xx_dxe_ctl *ctl,
|
||||
gfp_t gfp)
|
||||
{
|
||||
struct wcn36xx_dxe_desc *dxe = ctl->desc;
|
||||
struct sk_buff *skb;
|
||||
|
||||
skb = alloc_skb(WCN36XX_PKT_SIZE, GFP_ATOMIC);
|
||||
skb = alloc_skb(WCN36XX_PKT_SIZE, gfp);
|
||||
if (skb == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
|
@ -307,7 +308,7 @@ static int wcn36xx_dxe_ch_alloc_skb(struct wcn36xx *wcn,
|
|||
cur_ctl = wcn_ch->head_blk_ctl;
|
||||
|
||||
for (i = 0; i < wcn_ch->desc_num; i++) {
|
||||
wcn36xx_dxe_fill_skb(wcn->dev, cur_ctl);
|
||||
wcn36xx_dxe_fill_skb(wcn->dev, cur_ctl, GFP_KERNEL);
|
||||
cur_ctl = cur_ctl->next;
|
||||
}
|
||||
|
||||
|
@ -367,7 +368,7 @@ static void reap_tx_dxes(struct wcn36xx *wcn, struct wcn36xx_dxe_ch *ch)
|
|||
spin_lock_irqsave(&ch->lock, flags);
|
||||
ctl = ch->tail_blk_ctl;
|
||||
do {
|
||||
if (ctl->desc->ctrl & WCN36xx_DXE_CTRL_VLD)
|
||||
if (READ_ONCE(ctl->desc->ctrl) & WCN36xx_DXE_CTRL_VLD)
|
||||
break;
|
||||
if (ctl->skb) {
|
||||
dma_unmap_single(wcn->dev, ctl->desc->src_addr_l,
|
||||
|
@ -377,18 +378,16 @@ static void reap_tx_dxes(struct wcn36xx *wcn, struct wcn36xx_dxe_ch *ch)
|
|||
/* Keep frame until TX status comes */
|
||||
ieee80211_free_txskb(wcn->hw, ctl->skb);
|
||||
}
|
||||
spin_lock(&ctl->skb_lock);
|
||||
|
||||
if (wcn->queues_stopped) {
|
||||
wcn->queues_stopped = false;
|
||||
ieee80211_wake_queues(wcn->hw);
|
||||
}
|
||||
spin_unlock(&ctl->skb_lock);
|
||||
|
||||
ctl->skb = NULL;
|
||||
}
|
||||
ctl = ctl->next;
|
||||
} while (ctl != ch->head_blk_ctl &&
|
||||
!(ctl->desc->ctrl & WCN36xx_DXE_CTRL_VLD));
|
||||
} while (ctl != ch->head_blk_ctl);
|
||||
|
||||
ch->tail_blk_ctl = ctl;
|
||||
spin_unlock_irqrestore(&ch->lock, flags);
|
||||
|
@ -530,10 +529,10 @@ static int wcn36xx_rx_handle_packets(struct wcn36xx *wcn,
|
|||
int_mask = WCN36XX_DXE_INT_CH3_MASK;
|
||||
}
|
||||
|
||||
while (!(dxe->ctrl & WCN36xx_DXE_CTRL_VLD)) {
|
||||
while (!(READ_ONCE(dxe->ctrl) & WCN36xx_DXE_CTRL_VLD)) {
|
||||
skb = ctl->skb;
|
||||
dma_addr = dxe->dst_addr_l;
|
||||
ret = wcn36xx_dxe_fill_skb(wcn->dev, ctl);
|
||||
ret = wcn36xx_dxe_fill_skb(wcn->dev, ctl, GFP_ATOMIC);
|
||||
if (0 == ret) {
|
||||
/* new skb allocation ok. Use the new one and queue
|
||||
* the old one to network system.
|
||||
|
@ -654,8 +653,6 @@ int wcn36xx_dxe_tx_frame(struct wcn36xx *wcn,
|
|||
spin_lock_irqsave(&ch->lock, flags);
|
||||
ctl = ch->head_blk_ctl;
|
||||
|
||||
spin_lock(&ctl->next->skb_lock);
|
||||
|
||||
/*
|
||||
* If skb is not null that means that we reached the tail of the ring
|
||||
* hence ring is full. Stop queues to let mac80211 back off until ring
|
||||
|
@ -664,11 +661,9 @@ int wcn36xx_dxe_tx_frame(struct wcn36xx *wcn,
|
|||
if (NULL != ctl->next->skb) {
|
||||
ieee80211_stop_queues(wcn->hw);
|
||||
wcn->queues_stopped = true;
|
||||
spin_unlock(&ctl->next->skb_lock);
|
||||
spin_unlock_irqrestore(&ch->lock, flags);
|
||||
return -EBUSY;
|
||||
}
|
||||
spin_unlock(&ctl->next->skb_lock);
|
||||
|
||||
ctl->skb = NULL;
|
||||
desc = ctl->desc;
|
||||
|
@ -693,7 +688,6 @@ int wcn36xx_dxe_tx_frame(struct wcn36xx *wcn,
|
|||
|
||||
/* Set source address of the SKB we send */
|
||||
ctl = ctl->next;
|
||||
ctl->skb = skb;
|
||||
desc = ctl->desc;
|
||||
if (ctl->bd_cpu_addr) {
|
||||
wcn36xx_err("bd_cpu_addr cannot be NULL for skb DXE\n");
|
||||
|
@ -702,10 +696,16 @@ int wcn36xx_dxe_tx_frame(struct wcn36xx *wcn,
|
|||
}
|
||||
|
||||
desc->src_addr_l = dma_map_single(wcn->dev,
|
||||
ctl->skb->data,
|
||||
ctl->skb->len,
|
||||
skb->data,
|
||||
skb->len,
|
||||
DMA_TO_DEVICE);
|
||||
if (dma_mapping_error(wcn->dev, desc->src_addr_l)) {
|
||||
dev_err(wcn->dev, "unable to DMA map src_addr_l\n");
|
||||
ret = -ENOMEM;
|
||||
goto unlock;
|
||||
}
|
||||
|
||||
ctl->skb = skb;
|
||||
desc->dst_addr_l = ch->dxe_wq;
|
||||
desc->fr_len = ctl->skb->len;
|
||||
|
||||
|
|
|
@ -422,7 +422,6 @@ struct wcn36xx_dxe_ctl {
|
|||
unsigned int desc_phy_addr;
|
||||
int ctl_blk_order;
|
||||
struct sk_buff *skb;
|
||||
spinlock_t skb_lock;
|
||||
void *bd_cpu_addr;
|
||||
dma_addr_t bd_phy_addr;
|
||||
};
|
||||
|
|
|
@ -88,6 +88,12 @@
|
|||
/* version string max length (including NULL) */
|
||||
#define WCN36XX_HAL_VERSION_LENGTH 64
|
||||
|
||||
/* How many frames until we start a-mpdu TX session */
|
||||
#define WCN36XX_AMPDU_START_THRESH 20
|
||||
|
||||
#define WCN36XX_MAX_SCAN_SSIDS 9
|
||||
#define WCN36XX_MAX_SCAN_IE_LEN 500
|
||||
|
||||
/* message types for messages exchanged between WDI and HAL */
|
||||
enum wcn36xx_hal_host_msg_type {
|
||||
/* Init/De-Init */
|
||||
|
@ -1170,7 +1176,7 @@ struct wcn36xx_hal_start_scan_offload_req_msg {
|
|||
|
||||
/* IE field */
|
||||
u16 ie_len;
|
||||
u8 ie[0];
|
||||
u8 ie[WCN36XX_MAX_SCAN_IE_LEN];
|
||||
} __packed;
|
||||
|
||||
struct wcn36xx_hal_start_scan_offload_rsp_msg {
|
||||
|
|
|
@ -353,6 +353,19 @@ static void wcn36xx_stop(struct ieee80211_hw *hw)
|
|||
|
||||
wcn36xx_dbg(WCN36XX_DBG_MAC, "mac stop\n");
|
||||
|
||||
cancel_work_sync(&wcn->scan_work);
|
||||
|
||||
mutex_lock(&wcn->scan_lock);
|
||||
if (wcn->scan_req) {
|
||||
struct cfg80211_scan_info scan_info = {
|
||||
.aborted = true,
|
||||
};
|
||||
|
||||
ieee80211_scan_completed(wcn->hw, &scan_info);
|
||||
}
|
||||
wcn->scan_req = NULL;
|
||||
mutex_unlock(&wcn->scan_lock);
|
||||
|
||||
wcn36xx_debugfs_exit(wcn);
|
||||
wcn36xx_smd_stop(wcn);
|
||||
wcn36xx_dxe_deinit(wcn);
|
||||
|
@ -549,6 +562,7 @@ static int wcn36xx_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
|
|||
} else {
|
||||
wcn36xx_smd_set_bsskey(wcn,
|
||||
vif_priv->encrypt_type,
|
||||
vif_priv->bss_index,
|
||||
key_conf->keyidx,
|
||||
key_conf->keylen,
|
||||
key);
|
||||
|
@ -566,10 +580,13 @@ static int wcn36xx_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
|
|||
break;
|
||||
case DISABLE_KEY:
|
||||
if (!(IEEE80211_KEY_FLAG_PAIRWISE & key_conf->flags)) {
|
||||
if (vif_priv->bss_index != WCN36XX_HAL_BSS_INVALID_IDX)
|
||||
wcn36xx_smd_remove_bsskey(wcn,
|
||||
vif_priv->encrypt_type,
|
||||
vif_priv->bss_index,
|
||||
key_conf->keyidx);
|
||||
|
||||
vif_priv->encrypt_type = WCN36XX_HAL_ED_NONE;
|
||||
wcn36xx_smd_remove_bsskey(wcn,
|
||||
vif_priv->encrypt_type,
|
||||
key_conf->keyidx);
|
||||
} else {
|
||||
sta_priv->is_data_encrypted = false;
|
||||
/* do not remove key if disassociated */
|
||||
|
@ -670,10 +687,18 @@ static void wcn36xx_cancel_hw_scan(struct ieee80211_hw *hw,
|
|||
wcn->scan_aborted = true;
|
||||
mutex_unlock(&wcn->scan_lock);
|
||||
|
||||
/* ieee80211_scan_completed will be called on FW scan indication */
|
||||
wcn36xx_smd_stop_hw_scan(wcn);
|
||||
if (get_feat_caps(wcn->fw_feat_caps, SCAN_OFFLOAD)) {
|
||||
/* ieee80211_scan_completed will be called on FW scan
|
||||
* indication */
|
||||
wcn36xx_smd_stop_hw_scan(wcn);
|
||||
} else {
|
||||
struct cfg80211_scan_info scan_info = {
|
||||
.aborted = true,
|
||||
};
|
||||
|
||||
cancel_work_sync(&wcn->scan_work);
|
||||
cancel_work_sync(&wcn->scan_work);
|
||||
ieee80211_scan_completed(wcn->hw, &scan_info);
|
||||
}
|
||||
}
|
||||
|
||||
static void wcn36xx_update_allowed_rates(struct ieee80211_sta *sta,
|
||||
|
@ -953,6 +978,7 @@ static int wcn36xx_add_interface(struct ieee80211_hw *hw,
|
|||
|
||||
mutex_lock(&wcn->conf_mutex);
|
||||
|
||||
vif_priv->bss_index = WCN36XX_HAL_BSS_INVALID_IDX;
|
||||
list_add(&vif_priv->list, &wcn->vif_list);
|
||||
wcn36xx_smd_add_sta_self(wcn, vif);
|
||||
|
||||
|
|
|
@ -620,9 +620,13 @@ out:
|
|||
int wcn36xx_smd_start_hw_scan(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
||||
struct cfg80211_scan_request *req)
|
||||
{
|
||||
struct wcn36xx_vif *vif_priv = wcn36xx_vif_to_priv(vif);
|
||||
struct wcn36xx_hal_start_scan_offload_req_msg msg_body;
|
||||
int ret, i;
|
||||
|
||||
if (req->ie_len > WCN36XX_MAX_SCAN_IE_LEN)
|
||||
return -EINVAL;
|
||||
|
||||
mutex_lock(&wcn->hal_mutex);
|
||||
INIT_HAL_MSG(msg_body, WCN36XX_HAL_START_SCAN_OFFLOAD_REQ);
|
||||
|
||||
|
@ -631,6 +635,7 @@ int wcn36xx_smd_start_hw_scan(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
|||
msg_body.max_ch_time = 100;
|
||||
msg_body.scan_hidden = 1;
|
||||
memcpy(msg_body.mac, vif->addr, ETH_ALEN);
|
||||
msg_body.bss_type = vif_priv->bss_type;
|
||||
msg_body.p2p_search = vif->p2p;
|
||||
|
||||
msg_body.num_ssid = min_t(u8, req->n_ssids, ARRAY_SIZE(msg_body.ssids));
|
||||
|
@ -646,6 +651,14 @@ int wcn36xx_smd_start_hw_scan(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
|||
for (i = 0; i < msg_body.num_channel; i++)
|
||||
msg_body.channels[i] = req->channels[i]->hw_value;
|
||||
|
||||
msg_body.header.len -= WCN36XX_MAX_SCAN_IE_LEN;
|
||||
|
||||
if (req->ie_len > 0) {
|
||||
msg_body.ie_len = req->ie_len;
|
||||
msg_body.header.len += req->ie_len;
|
||||
memcpy(msg_body.ie, req->ie, req->ie_len);
|
||||
}
|
||||
|
||||
PREPARE_HAL_BUF(wcn->hal_buf, msg_body);
|
||||
|
||||
wcn36xx_dbg(WCN36XX_DBG_HAL,
|
||||
|
@ -1399,9 +1412,10 @@ int wcn36xx_smd_config_bss(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
|||
bss->spectrum_mgt_enable = 0;
|
||||
bss->tx_mgmt_power = 0;
|
||||
bss->max_tx_power = WCN36XX_MAX_POWER(wcn);
|
||||
|
||||
bss->action = update;
|
||||
|
||||
vif_priv->bss_type = bss->bss_type;
|
||||
|
||||
wcn36xx_dbg(WCN36XX_DBG_HAL,
|
||||
"hal config bss bssid %pM self_mac_addr %pM bss_type %d oper_mode %d nw_type %d\n",
|
||||
bss->bssid, bss->self_mac_addr, bss->bss_type,
|
||||
|
@ -1446,6 +1460,10 @@ int wcn36xx_smd_delete_bss(struct wcn36xx *wcn, struct ieee80211_vif *vif)
|
|||
int ret = 0;
|
||||
|
||||
mutex_lock(&wcn->hal_mutex);
|
||||
|
||||
if (vif_priv->bss_index == WCN36XX_HAL_BSS_INVALID_IDX)
|
||||
goto out;
|
||||
|
||||
INIT_HAL_MSG(msg_body, WCN36XX_HAL_DELETE_BSS_REQ);
|
||||
|
||||
msg_body.bss_index = vif_priv->bss_index;
|
||||
|
@ -1464,6 +1482,8 @@ int wcn36xx_smd_delete_bss(struct wcn36xx *wcn, struct ieee80211_vif *vif)
|
|||
wcn36xx_err("hal_delete_bss response failed err=%d\n", ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
vif_priv->bss_index = WCN36XX_HAL_BSS_INVALID_IDX;
|
||||
out:
|
||||
mutex_unlock(&wcn->hal_mutex);
|
||||
return ret;
|
||||
|
@ -1630,6 +1650,7 @@ out:
|
|||
|
||||
int wcn36xx_smd_set_bsskey(struct wcn36xx *wcn,
|
||||
enum ani_ed_type enc_type,
|
||||
u8 bssidx,
|
||||
u8 keyidx,
|
||||
u8 keylen,
|
||||
u8 *key)
|
||||
|
@ -1639,7 +1660,7 @@ int wcn36xx_smd_set_bsskey(struct wcn36xx *wcn,
|
|||
|
||||
mutex_lock(&wcn->hal_mutex);
|
||||
INIT_HAL_MSG(msg_body, WCN36XX_HAL_SET_BSSKEY_REQ);
|
||||
msg_body.bss_idx = 0;
|
||||
msg_body.bss_idx = bssidx;
|
||||
msg_body.enc_type = enc_type;
|
||||
msg_body.num_keys = 1;
|
||||
msg_body.keys[0].id = keyidx;
|
||||
|
@ -1700,6 +1721,7 @@ out:
|
|||
|
||||
int wcn36xx_smd_remove_bsskey(struct wcn36xx *wcn,
|
||||
enum ani_ed_type enc_type,
|
||||
u8 bssidx,
|
||||
u8 keyidx)
|
||||
{
|
||||
struct wcn36xx_hal_remove_bss_key_req_msg msg_body;
|
||||
|
@ -1707,7 +1729,7 @@ int wcn36xx_smd_remove_bsskey(struct wcn36xx *wcn,
|
|||
|
||||
mutex_lock(&wcn->hal_mutex);
|
||||
INIT_HAL_MSG(msg_body, WCN36XX_HAL_RMV_BSSKEY_REQ);
|
||||
msg_body.bss_idx = 0;
|
||||
msg_body.bss_idx = bssidx;
|
||||
msg_body.enc_type = enc_type;
|
||||
msg_body.key_id = keyidx;
|
||||
|
||||
|
@ -2132,11 +2154,13 @@ static int wcn36xx_smd_hw_scan_ind(struct wcn36xx *wcn, void *buf, size_t len)
|
|||
return -EIO;
|
||||
}
|
||||
|
||||
wcn36xx_dbg(WCN36XX_DBG_HAL, "scan indication (type %x)", rsp->type);
|
||||
wcn36xx_dbg(WCN36XX_DBG_HAL, "scan indication (type %x)\n", rsp->type);
|
||||
|
||||
switch (rsp->type) {
|
||||
case WCN36XX_HAL_SCAN_IND_FAILED:
|
||||
case WCN36XX_HAL_SCAN_IND_DEQUEUED:
|
||||
scan_info.aborted = true;
|
||||
/* fall through */
|
||||
case WCN36XX_HAL_SCAN_IND_COMPLETED:
|
||||
mutex_lock(&wcn->scan_lock);
|
||||
wcn->scan_req = NULL;
|
||||
|
@ -2147,7 +2171,6 @@ static int wcn36xx_smd_hw_scan_ind(struct wcn36xx *wcn, void *buf, size_t len)
|
|||
break;
|
||||
case WCN36XX_HAL_SCAN_IND_STARTED:
|
||||
case WCN36XX_HAL_SCAN_IND_FOREIGN_CHANNEL:
|
||||
case WCN36XX_HAL_SCAN_IND_DEQUEUED:
|
||||
case WCN36XX_HAL_SCAN_IND_PREEMPTED:
|
||||
case WCN36XX_HAL_SCAN_IND_RESTARTED:
|
||||
break;
|
||||
|
|
|
@ -97,6 +97,7 @@ int wcn36xx_smd_set_stakey(struct wcn36xx *wcn,
|
|||
u8 sta_index);
|
||||
int wcn36xx_smd_set_bsskey(struct wcn36xx *wcn,
|
||||
enum ani_ed_type enc_type,
|
||||
u8 bssidx,
|
||||
u8 keyidx,
|
||||
u8 keylen,
|
||||
u8 *key);
|
||||
|
@ -106,6 +107,7 @@ int wcn36xx_smd_remove_stakey(struct wcn36xx *wcn,
|
|||
u8 sta_index);
|
||||
int wcn36xx_smd_remove_bsskey(struct wcn36xx *wcn,
|
||||
enum ani_ed_type enc_type,
|
||||
u8 bssidx,
|
||||
u8 keyidx);
|
||||
int wcn36xx_smd_enter_bmps(struct wcn36xx *wcn, struct ieee80211_vif *vif);
|
||||
int wcn36xx_smd_exit_bmps(struct wcn36xx *wcn, struct ieee80211_vif *vif);
|
||||
|
|
|
@ -273,6 +273,7 @@ int wcn36xx_start_tx(struct wcn36xx *wcn,
|
|||
bool bcast = is_broadcast_ether_addr(hdr->addr1) ||
|
||||
is_multicast_ether_addr(hdr->addr1);
|
||||
struct wcn36xx_tx_bd bd;
|
||||
int ret;
|
||||
|
||||
memset(&bd, 0, sizeof(bd));
|
||||
|
||||
|
@ -317,5 +318,17 @@ int wcn36xx_start_tx(struct wcn36xx *wcn,
|
|||
buff_to_be((u32 *)&bd, sizeof(bd)/sizeof(u32));
|
||||
bd.tx_bd_sign = 0xbdbdbdbd;
|
||||
|
||||
return wcn36xx_dxe_tx_frame(wcn, vif_priv, &bd, skb, is_low);
|
||||
ret = wcn36xx_dxe_tx_frame(wcn, vif_priv, &bd, skb, is_low);
|
||||
if (ret && bd.tx_comp) {
|
||||
/* If the skb has not been transmitted,
|
||||
* don't keep a reference to it.
|
||||
*/
|
||||
spin_lock_irqsave(&wcn->dxe_lock, flags);
|
||||
wcn->tx_ack_skb = NULL;
|
||||
spin_unlock_irqrestore(&wcn->dxe_lock, flags);
|
||||
|
||||
ieee80211_wake_queues(wcn->hw);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -32,12 +32,6 @@
|
|||
#define WLAN_NV_FILE "wlan/prima/WCNSS_qcom_wlan_nv.bin"
|
||||
#define WCN36XX_AGGR_BUFFER_SIZE 64
|
||||
|
||||
/* How many frames until we start a-mpdu TX session */
|
||||
#define WCN36XX_AMPDU_START_THRESH 20
|
||||
|
||||
#define WCN36XX_MAX_SCAN_SSIDS 9
|
||||
#define WCN36XX_MAX_SCAN_IE_LEN 500
|
||||
|
||||
extern unsigned int wcn36xx_dbg_mask;
|
||||
|
||||
enum wcn36xx_debug_mask {
|
||||
|
@ -123,6 +117,7 @@ struct wcn36xx_vif {
|
|||
bool is_joining;
|
||||
bool sta_assoc;
|
||||
struct wcn36xx_hal_mac_ssid ssid;
|
||||
enum wcn36xx_hal_bss_type bss_type;
|
||||
|
||||
/* Power management */
|
||||
enum wcn36xx_power_state pw_state;
|
||||
|
|
|
@ -1200,8 +1200,12 @@ static const struct file_operations fops_freq = {
|
|||
static int wil_link_debugfs_show(struct seq_file *s, void *data)
|
||||
{
|
||||
struct wil6210_priv *wil = s->private;
|
||||
struct station_info sinfo;
|
||||
int i, rc;
|
||||
struct station_info *sinfo;
|
||||
int i, rc = 0;
|
||||
|
||||
sinfo = kzalloc(sizeof(*sinfo), GFP_KERNEL);
|
||||
if (!sinfo)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(wil->sta); i++) {
|
||||
struct wil_sta_info *p = &wil->sta[i];
|
||||
|
@ -1229,19 +1233,21 @@ static int wil_link_debugfs_show(struct seq_file *s, void *data)
|
|||
|
||||
vif = (mid < wil->max_vifs) ? wil->vifs[mid] : NULL;
|
||||
if (vif) {
|
||||
rc = wil_cid_fill_sinfo(vif, i, &sinfo);
|
||||
rc = wil_cid_fill_sinfo(vif, i, sinfo);
|
||||
if (rc)
|
||||
return rc;
|
||||
goto out;
|
||||
|
||||
seq_printf(s, " Tx_mcs = %d\n", sinfo.txrate.mcs);
|
||||
seq_printf(s, " Rx_mcs = %d\n", sinfo.rxrate.mcs);
|
||||
seq_printf(s, " SQ = %d\n", sinfo.signal);
|
||||
seq_printf(s, " Tx_mcs = %d\n", sinfo->txrate.mcs);
|
||||
seq_printf(s, " Rx_mcs = %d\n", sinfo->rxrate.mcs);
|
||||
seq_printf(s, " SQ = %d\n", sinfo->signal);
|
||||
} else {
|
||||
seq_puts(s, " INVALID MID\n");
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
out:
|
||||
kfree(sinfo);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int wil_link_seq_open(struct inode *inode, struct file *file)
|
||||
|
|
|
@ -391,7 +391,7 @@ static void wil_fw_error_worker(struct work_struct *work)
|
|||
struct wil6210_priv *wil = container_of(work, struct wil6210_priv,
|
||||
fw_error_worker);
|
||||
struct net_device *ndev = wil->main_ndev;
|
||||
struct wireless_dev *wdev = ndev->ieee80211_ptr;
|
||||
struct wireless_dev *wdev;
|
||||
|
||||
wil_dbg_misc(wil, "fw error worker\n");
|
||||
|
||||
|
@ -399,6 +399,7 @@ static void wil_fw_error_worker(struct work_struct *work)
|
|||
wil_info(wil, "No recovery - interface is down\n");
|
||||
return;
|
||||
}
|
||||
wdev = ndev->ieee80211_ptr;
|
||||
|
||||
/* increment @recovery_count if less then WIL6210_FW_RECOVERY_TO
|
||||
* passed since last recovery attempt
|
||||
|
|
|
@ -824,7 +824,7 @@ static void wmi_evt_connect(struct wil6210_vif *vif, int id, void *d, int len)
|
|||
struct wireless_dev *wdev = vif_to_wdev(vif);
|
||||
struct wmi_connect_event *evt = d;
|
||||
int ch; /* channel number */
|
||||
struct station_info sinfo;
|
||||
struct station_info *sinfo;
|
||||
u8 *assoc_req_ie, *assoc_resp_ie;
|
||||
size_t assoc_req_ielen, assoc_resp_ielen;
|
||||
/* capinfo(u16) + listen_interval(u16) + IEs */
|
||||
|
@ -940,6 +940,7 @@ static void wmi_evt_connect(struct wil6210_vif *vif, int id, void *d, int len)
|
|||
vif->bss = NULL;
|
||||
} else if ((wdev->iftype == NL80211_IFTYPE_AP) ||
|
||||
(wdev->iftype == NL80211_IFTYPE_P2P_GO)) {
|
||||
|
||||
if (rc) {
|
||||
if (disable_ap_sme)
|
||||
/* notify new_sta has failed */
|
||||
|
@ -947,16 +948,22 @@ static void wmi_evt_connect(struct wil6210_vif *vif, int id, void *d, int len)
|
|||
goto out;
|
||||
}
|
||||
|
||||
memset(&sinfo, 0, sizeof(sinfo));
|
||||
|
||||
sinfo.generation = wil->sinfo_gen++;
|
||||
|
||||
if (assoc_req_ie) {
|
||||
sinfo.assoc_req_ies = assoc_req_ie;
|
||||
sinfo.assoc_req_ies_len = assoc_req_ielen;
|
||||
sinfo = kzalloc(sizeof(*sinfo), GFP_KERNEL);
|
||||
if (!sinfo) {
|
||||
rc = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
cfg80211_new_sta(ndev, evt->bssid, &sinfo, GFP_KERNEL);
|
||||
sinfo->generation = wil->sinfo_gen++;
|
||||
|
||||
if (assoc_req_ie) {
|
||||
sinfo->assoc_req_ies = assoc_req_ie;
|
||||
sinfo->assoc_req_ies_len = assoc_req_ielen;
|
||||
}
|
||||
|
||||
cfg80211_new_sta(ndev, evt->bssid, sinfo, GFP_KERNEL);
|
||||
|
||||
kfree(sinfo);
|
||||
} else {
|
||||
wil_err(wil, "unhandled iftype %d for CID %d\n", wdev->iftype,
|
||||
evt->cid);
|
||||
|
|
|
@ -1484,7 +1484,7 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev,
|
|||
int slot, firstused;
|
||||
bool frame_succeed;
|
||||
int skip;
|
||||
static u8 err_out1, err_out2;
|
||||
static u8 err_out1;
|
||||
|
||||
ring = parse_cookie(dev, status->cookie, &slot);
|
||||
if (unlikely(!ring))
|
||||
|
@ -1518,13 +1518,13 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev,
|
|||
}
|
||||
} else {
|
||||
/* More than a single header/data pair were missed.
|
||||
* Report this error once.
|
||||
* Report this error, and reset the controller to
|
||||
* revive operation.
|
||||
*/
|
||||
if (!err_out2)
|
||||
b43dbg(dev->wl,
|
||||
"Out of order TX status report on DMA ring %d. Expected %d, but got %d\n",
|
||||
ring->index, firstused, slot);
|
||||
err_out2 = 1;
|
||||
b43dbg(dev->wl,
|
||||
"Out of order TX status report on DMA ring %d. Expected %d, but got %d\n",
|
||||
ring->index, firstused, slot);
|
||||
b43_controller_restart(dev, "Out of order TX");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -1064,7 +1064,7 @@ static int dma_tx_fragment(struct b43legacy_dmaring *ring,
|
|||
meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
|
||||
/* create a bounce buffer in zone_dma on mapping failure. */
|
||||
if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
|
||||
bounce_skb = alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
|
||||
bounce_skb = alloc_skb(skb->len, GFP_KERNEL | GFP_DMA);
|
||||
if (!bounce_skb) {
|
||||
ring->current_slot = old_top_slot;
|
||||
ring->used_slots = old_used_slots;
|
||||
|
|
|
@ -963,6 +963,7 @@ static const struct sdio_device_id brcmf_sdmmc_ids[] = {
|
|||
BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_43340),
|
||||
BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_43341),
|
||||
BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_43362),
|
||||
BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_43364),
|
||||
BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_4335_4339),
|
||||
BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_4339),
|
||||
BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_43430),
|
||||
|
|
|
@ -2728,9 +2728,8 @@ static s32 brcmf_inform_single_bss(struct brcmf_cfg80211_info *cfg,
|
|||
struct brcmf_bss_info_le *bi)
|
||||
{
|
||||
struct wiphy *wiphy = cfg_to_wiphy(cfg);
|
||||
struct ieee80211_channel *notify_channel;
|
||||
struct cfg80211_bss *bss;
|
||||
struct ieee80211_supported_band *band;
|
||||
enum nl80211_band band;
|
||||
struct brcmu_chan ch;
|
||||
u16 channel;
|
||||
u32 freq;
|
||||
|
@ -2738,7 +2737,7 @@ static s32 brcmf_inform_single_bss(struct brcmf_cfg80211_info *cfg,
|
|||
u16 notify_interval;
|
||||
u8 *notify_ie;
|
||||
size_t notify_ielen;
|
||||
s32 notify_signal;
|
||||
struct cfg80211_inform_bss bss_data = {};
|
||||
|
||||
if (le32_to_cpu(bi->length) > WL_BSS_INFO_MAX) {
|
||||
brcmf_err("Bss info is larger than buffer. Discarding\n");
|
||||
|
@ -2753,32 +2752,33 @@ static s32 brcmf_inform_single_bss(struct brcmf_cfg80211_info *cfg,
|
|||
channel = bi->ctl_ch;
|
||||
|
||||
if (channel <= CH_MAX_2G_CHANNEL)
|
||||
band = wiphy->bands[NL80211_BAND_2GHZ];
|
||||
band = NL80211_BAND_2GHZ;
|
||||
else
|
||||
band = wiphy->bands[NL80211_BAND_5GHZ];
|
||||
band = NL80211_BAND_5GHZ;
|
||||
|
||||
freq = ieee80211_channel_to_frequency(channel, band->band);
|
||||
notify_channel = ieee80211_get_channel(wiphy, freq);
|
||||
freq = ieee80211_channel_to_frequency(channel, band);
|
||||
bss_data.chan = ieee80211_get_channel(wiphy, freq);
|
||||
bss_data.scan_width = NL80211_BSS_CHAN_WIDTH_20;
|
||||
bss_data.boottime_ns = ktime_to_ns(ktime_get_boottime());
|
||||
|
||||
notify_capability = le16_to_cpu(bi->capability);
|
||||
notify_interval = le16_to_cpu(bi->beacon_period);
|
||||
notify_ie = (u8 *)bi + le16_to_cpu(bi->ie_offset);
|
||||
notify_ielen = le32_to_cpu(bi->ie_length);
|
||||
notify_signal = (s16)le16_to_cpu(bi->RSSI) * 100;
|
||||
bss_data.signal = (s16)le16_to_cpu(bi->RSSI) * 100;
|
||||
|
||||
brcmf_dbg(CONN, "bssid: %pM\n", bi->BSSID);
|
||||
brcmf_dbg(CONN, "Channel: %d(%d)\n", channel, freq);
|
||||
brcmf_dbg(CONN, "Capability: %X\n", notify_capability);
|
||||
brcmf_dbg(CONN, "Beacon interval: %d\n", notify_interval);
|
||||
brcmf_dbg(CONN, "Signal: %d\n", notify_signal);
|
||||
brcmf_dbg(CONN, "Signal: %d\n", bss_data.signal);
|
||||
|
||||
bss = cfg80211_inform_bss(wiphy, notify_channel,
|
||||
CFG80211_BSS_FTYPE_UNKNOWN,
|
||||
(const u8 *)bi->BSSID,
|
||||
0, notify_capability,
|
||||
notify_interval, notify_ie,
|
||||
notify_ielen, notify_signal,
|
||||
GFP_KERNEL);
|
||||
bss = cfg80211_inform_bss_data(wiphy, &bss_data,
|
||||
CFG80211_BSS_FTYPE_UNKNOWN,
|
||||
(const u8 *)bi->BSSID,
|
||||
0, notify_capability,
|
||||
notify_interval, notify_ie,
|
||||
notify_ielen, GFP_KERNEL);
|
||||
|
||||
if (!bss)
|
||||
return -ENOMEM;
|
||||
|
@ -5498,7 +5498,7 @@ brcmf_notify_connect_status_ap(struct brcmf_cfg80211_info *cfg,
|
|||
static int generation;
|
||||
u32 event = e->event_code;
|
||||
u32 reason = e->reason;
|
||||
struct station_info sinfo;
|
||||
struct station_info *sinfo;
|
||||
|
||||
brcmf_dbg(CONN, "event %s (%u), reason %d\n",
|
||||
brcmf_fweh_event_name(event), event, reason);
|
||||
|
@ -5511,16 +5511,22 @@ brcmf_notify_connect_status_ap(struct brcmf_cfg80211_info *cfg,
|
|||
|
||||
if (((event == BRCMF_E_ASSOC_IND) || (event == BRCMF_E_REASSOC_IND)) &&
|
||||
(reason == BRCMF_E_STATUS_SUCCESS)) {
|
||||
memset(&sinfo, 0, sizeof(sinfo));
|
||||
if (!data) {
|
||||
brcmf_err("No IEs present in ASSOC/REASSOC_IND");
|
||||
return -EINVAL;
|
||||
}
|
||||
sinfo.assoc_req_ies = data;
|
||||
sinfo.assoc_req_ies_len = e->datalen;
|
||||
|
||||
sinfo = kzalloc(sizeof(*sinfo), GFP_KERNEL);
|
||||
if (!sinfo)
|
||||
return -ENOMEM;
|
||||
|
||||
sinfo->assoc_req_ies = data;
|
||||
sinfo->assoc_req_ies_len = e->datalen;
|
||||
generation++;
|
||||
sinfo.generation = generation;
|
||||
cfg80211_new_sta(ndev, e->addr, &sinfo, GFP_KERNEL);
|
||||
sinfo->generation = generation;
|
||||
cfg80211_new_sta(ndev, e->addr, sinfo, GFP_KERNEL);
|
||||
|
||||
kfree(sinfo);
|
||||
} else if ((event == BRCMF_E_DISASSOC_IND) ||
|
||||
(event == BRCMF_E_DEAUTH_IND) ||
|
||||
(event == BRCMF_E_DEAUTH)) {
|
||||
|
@ -6512,6 +6518,7 @@ static int brcmf_setup_wiphy(struct wiphy *wiphy, struct brcmf_if *ifp)
|
|||
|
||||
wiphy->flags |= WIPHY_FLAG_NETNS_OK |
|
||||
WIPHY_FLAG_PS_ON_BY_DEFAULT |
|
||||
WIPHY_FLAG_HAVE_AP_SME |
|
||||
WIPHY_FLAG_OFFCHAN_TX |
|
||||
WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
|
||||
if (brcmf_feat_is_enabled(ifp, BRCMF_FEAT_TDLS))
|
||||
|
|
|
@ -689,6 +689,7 @@ static u32 brcmf_chip_tcm_rambase(struct brcmf_chip_priv *ci)
|
|||
case BRCM_CC_43525_CHIP_ID:
|
||||
case BRCM_CC_4365_CHIP_ID:
|
||||
case BRCM_CC_4366_CHIP_ID:
|
||||
case BRCM_CC_43664_CHIP_ID:
|
||||
return 0x200000;
|
||||
case CY_CC_4373_CHIP_ID:
|
||||
return 0x160000;
|
||||
|
|
|
@ -634,7 +634,7 @@ int brcmf_fw_get_firmwares(struct device *dev, struct brcmf_fw_request *req,
|
|||
|
||||
struct brcmf_fw_request *
|
||||
brcmf_fw_alloc_request(u32 chip, u32 chiprev,
|
||||
struct brcmf_firmware_mapping mapping_table[],
|
||||
const struct brcmf_firmware_mapping mapping_table[],
|
||||
u32 table_size, struct brcmf_fw_name *fwnames,
|
||||
u32 n_fwnames)
|
||||
{
|
||||
|
|
|
@ -80,7 +80,7 @@ struct brcmf_fw_name {
|
|||
|
||||
struct brcmf_fw_request *
|
||||
brcmf_fw_alloc_request(u32 chip, u32 chiprev,
|
||||
struct brcmf_firmware_mapping mapping_table[],
|
||||
const struct brcmf_firmware_mapping mapping_table[],
|
||||
u32 table_size, struct brcmf_fw_name *fwnames,
|
||||
u32 n_fwnames);
|
||||
|
||||
|
|
|
@ -27,8 +27,10 @@
|
|||
#define BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE 40
|
||||
#define BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE 32
|
||||
#define BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE 24
|
||||
#define BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE 16
|
||||
#define BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE 32
|
||||
#define BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE_PRE_V7 16
|
||||
#define BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE 24
|
||||
#define BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE_PRE_V7 32
|
||||
#define BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE 40
|
||||
#define BRCMF_H2D_TXFLOWRING_ITEMSIZE 48
|
||||
|
||||
struct msgbuf_buf_addr {
|
||||
|
|
|
@ -2073,6 +2073,13 @@ static struct wireless_dev *brcmf_p2p_create_p2pdev(struct brcmf_p2p_info *p2p,
|
|||
}
|
||||
|
||||
pri_ifp = p2p->bss_idx[P2PAPI_BSSCFG_PRIMARY].vif->ifp;
|
||||
|
||||
/* firmware requires unique mac address for p2pdev interface */
|
||||
if (addr && ether_addr_equal(addr, pri_ifp->mac_addr)) {
|
||||
brcmf_err("discovery vif must be different from primary interface\n");
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
brcmf_p2p_generate_bss_mac(p2p, addr);
|
||||
brcmf_p2p_set_firmware(pri_ifp, p2p->dev_addr);
|
||||
|
||||
|
|
|
@ -59,7 +59,7 @@ BRCMF_FW_DEF(4366B, "brcmfmac4366b-pcie");
|
|||
BRCMF_FW_DEF(4366C, "brcmfmac4366c-pcie");
|
||||
BRCMF_FW_DEF(4371, "brcmfmac4371-pcie");
|
||||
|
||||
static struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
|
||||
static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
|
||||
BRCMF_FW_ENTRY(BRCM_CC_43602_CHIP_ID, 0xFFFFFFFF, 43602),
|
||||
BRCMF_FW_ENTRY(BRCM_CC_43465_CHIP_ID, 0xFFFFFFF0, 4366C),
|
||||
BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0x000000FF, 4350C),
|
||||
|
@ -75,6 +75,7 @@ static struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
|
|||
BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0xFFFFFFF0, 4365C),
|
||||
BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0x0000000F, 4366B),
|
||||
BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0xFFFFFFF0, 4366C),
|
||||
BRCMF_FW_ENTRY(BRCM_CC_43664_CHIP_ID, 0xFFFFFFF0, 4366C),
|
||||
BRCMF_FW_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371),
|
||||
};
|
||||
|
||||
|
@ -104,7 +105,8 @@ static struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
|
|||
#define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C
|
||||
#define BRCMF_PCIE_PCIE2REG_CONFIGADDR 0x120
|
||||
#define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124
|
||||
#define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX 0x140
|
||||
#define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0 0x140
|
||||
#define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1 0x144
|
||||
|
||||
#define BRCMF_PCIE2_INTA 0x01
|
||||
#define BRCMF_PCIE2_INTB 0x02
|
||||
|
@ -134,11 +136,13 @@ static struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
|
|||
BRCMF_PCIE_MB_INT_D2H3_DB0 | \
|
||||
BRCMF_PCIE_MB_INT_D2H3_DB1)
|
||||
|
||||
#define BRCMF_PCIE_SHARED_VERSION_7 7
|
||||
#define BRCMF_PCIE_MIN_SHARED_VERSION 5
|
||||
#define BRCMF_PCIE_MAX_SHARED_VERSION 6
|
||||
#define BRCMF_PCIE_MAX_SHARED_VERSION BRCMF_PCIE_SHARED_VERSION_7
|
||||
#define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF
|
||||
#define BRCMF_PCIE_SHARED_DMA_INDEX 0x10000
|
||||
#define BRCMF_PCIE_SHARED_DMA_2B_IDX 0x100000
|
||||
#define BRCMF_PCIE_SHARED_HOSTRDY_DB1 0x10000000
|
||||
|
||||
#define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000
|
||||
#define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000
|
||||
|
@ -315,6 +319,14 @@ static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
|
|||
BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
|
||||
};
|
||||
|
||||
static const u32 brcmf_ring_itemsize_pre_v7[BRCMF_NROF_COMMON_MSGRINGS] = {
|
||||
BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
|
||||
BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
|
||||
BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
|
||||
BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE_PRE_V7,
|
||||
BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE_PRE_V7
|
||||
};
|
||||
|
||||
static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
|
||||
BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
|
||||
BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
|
||||
|
@ -781,6 +793,12 @@ static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
|
|||
BRCMF_PCIE_MB_INT_FN0_1);
|
||||
}
|
||||
|
||||
static void brcmf_pcie_hostready(struct brcmf_pciedev_info *devinfo)
|
||||
{
|
||||
if (devinfo->shared.flags & BRCMF_PCIE_SHARED_HOSTRDY_DB1)
|
||||
brcmf_pcie_write_reg32(devinfo,
|
||||
BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1, 1);
|
||||
}
|
||||
|
||||
static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg)
|
||||
{
|
||||
|
@ -923,7 +941,7 @@ static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
|
|||
|
||||
brcmf_dbg(PCIE, "RING !\n");
|
||||
/* Any arbitrary value will do, lets use 1 */
|
||||
brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
|
||||
brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -998,8 +1016,14 @@ brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
|
|||
struct brcmf_pcie_ringbuf *ring;
|
||||
u32 size;
|
||||
u32 addr;
|
||||
const u32 *ring_itemsize_array;
|
||||
|
||||
size = brcmf_ring_max_item[ring_id] * brcmf_ring_itemsize[ring_id];
|
||||
if (devinfo->shared.version < BRCMF_PCIE_SHARED_VERSION_7)
|
||||
ring_itemsize_array = brcmf_ring_itemsize_pre_v7;
|
||||
else
|
||||
ring_itemsize_array = brcmf_ring_itemsize;
|
||||
|
||||
size = brcmf_ring_max_item[ring_id] * ring_itemsize_array[ring_id];
|
||||
dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
|
||||
tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
|
||||
&dma_handle);
|
||||
|
@ -1009,7 +1033,7 @@ brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
|
|||
addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
|
||||
brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
|
||||
addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
|
||||
brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_itemsize[ring_id]);
|
||||
brcmf_pcie_write_tcm16(devinfo, addr, ring_itemsize_array[ring_id]);
|
||||
|
||||
ring = kzalloc(sizeof(*ring), GFP_KERNEL);
|
||||
if (!ring) {
|
||||
|
@ -1018,7 +1042,7 @@ brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
|
|||
return NULL;
|
||||
}
|
||||
brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
|
||||
brcmf_ring_itemsize[ring_id], dma_buf);
|
||||
ring_itemsize_array[ring_id], dma_buf);
|
||||
ring->dma_handle = dma_handle;
|
||||
ring->devinfo = devinfo;
|
||||
brcmf_commonring_register_cb(&ring->commonring,
|
||||
|
@ -1727,6 +1751,7 @@ static void brcmf_pcie_setup(struct device *dev, int ret,
|
|||
init_waitqueue_head(&devinfo->mbdata_resp_wait);
|
||||
|
||||
brcmf_pcie_intr_enable(devinfo);
|
||||
brcmf_pcie_hostready(devinfo);
|
||||
if (brcmf_attach(&devinfo->pdev->dev, devinfo->settings) == 0)
|
||||
return;
|
||||
|
||||
|
@ -1949,6 +1974,7 @@ static int brcmf_pcie_pm_leave_D3(struct device *dev)
|
|||
brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
|
||||
brcmf_bus_change_state(bus, BRCMF_BUS_UP);
|
||||
brcmf_pcie_intr_enable(devinfo);
|
||||
brcmf_pcie_hostready(devinfo);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -619,7 +619,7 @@ BRCMF_FW_DEF(4354, "brcmfmac4354-sdio");
|
|||
BRCMF_FW_DEF(4356, "brcmfmac4356-sdio");
|
||||
BRCMF_FW_DEF(4373, "brcmfmac4373-sdio");
|
||||
|
||||
static struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
|
||||
static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
|
||||
BRCMF_FW_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143),
|
||||
BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0),
|
||||
BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4),
|
||||
|
|
|
@ -52,7 +52,7 @@ BRCMF_FW_DEF(43242A, "brcmfmac43242a");
|
|||
BRCMF_FW_DEF(43569, "brcmfmac43569");
|
||||
BRCMF_FW_DEF(4373, "brcmfmac4373");
|
||||
|
||||
static struct brcmf_firmware_mapping brcmf_usb_fwnames[] = {
|
||||
static const struct brcmf_firmware_mapping brcmf_usb_fwnames[] = {
|
||||
BRCMF_FW_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143),
|
||||
BRCMF_FW_ENTRY(BRCM_CC_43235_CHIP_ID, 0x00000008, 43236B),
|
||||
BRCMF_FW_ENTRY(BRCM_CC_43236_CHIP_ID, 0x00000008, 43236B),
|
||||
|
|
|
@ -3388,13 +3388,8 @@ void wlc_lcnphy_deaf_mode(struct brcms_phy *pi, bool mode)
|
|||
u8 phybw40;
|
||||
phybw40 = CHSPEC_IS40(pi->radio_chanspec);
|
||||
|
||||
if (LCNREV_LT(pi->pubpi.phy_rev, 2)) {
|
||||
mod_phy_reg(pi, 0x4b0, (0x1 << 5), (mode) << 5);
|
||||
mod_phy_reg(pi, 0x4b1, (0x1 << 9), 0 << 9);
|
||||
} else {
|
||||
mod_phy_reg(pi, 0x4b0, (0x1 << 5), (mode) << 5);
|
||||
mod_phy_reg(pi, 0x4b1, (0x1 << 9), 0 << 9);
|
||||
}
|
||||
mod_phy_reg(pi, 0x4b0, (0x1 << 5), (mode) << 5);
|
||||
mod_phy_reg(pi, 0x4b1, (0x1 << 9), 0 << 9);
|
||||
|
||||
if (phybw40 == 0) {
|
||||
mod_phy_reg((pi), 0x410,
|
||||
|
|
|
@ -57,6 +57,7 @@
|
|||
#define BRCM_CC_43602_CHIP_ID 43602
|
||||
#define BRCM_CC_4365_CHIP_ID 0x4365
|
||||
#define BRCM_CC_4366_CHIP_ID 0x4366
|
||||
#define BRCM_CC_43664_CHIP_ID 43664
|
||||
#define BRCM_CC_4371_CHIP_ID 0x4371
|
||||
#define CY_CC_4373_CHIP_ID 0x4373
|
||||
|
||||
|
|
|
@ -3732,7 +3732,7 @@ IPW2100_ORD(STAT_TX_HOST_REQUESTS, "requested Host Tx's (MSDU)"),
|
|||
IPW2100_ORD(ASSOCIATED_AP_PTR,
|
||||
"0 if not associated, else pointer to AP table entry"),
|
||||
IPW2100_ORD(AVAILABLE_AP_CNT,
|
||||
"AP's decsribed in the AP table"),
|
||||
"AP's described in the AP table"),
|
||||
IPW2100_ORD(AP_LIST_PTR, "Ptr to list of available APs"),
|
||||
IPW2100_ORD(STAT_AP_ASSNS, "associations"),
|
||||
IPW2100_ORD(STAT_ASSN_FAIL, "association failures"),
|
||||
|
|
|
@ -1009,7 +1009,7 @@ typedef enum _ORDINAL_TABLE_1 { // NS - means Not Supported by FW
|
|||
IPW_ORD_STAT_PERCENT_RETRIES, // current calculation of % missed tx retries
|
||||
IPW_ORD_ASSOCIATED_AP_PTR, // If associated, this is ptr to the associated
|
||||
// AP table entry. set to 0 if not associated
|
||||
IPW_ORD_AVAILABLE_AP_CNT, // # of AP's decsribed in the AP table
|
||||
IPW_ORD_AVAILABLE_AP_CNT, // # of AP's described in the AP table
|
||||
IPW_ORD_AP_LIST_PTR, // Ptr to list of available APs
|
||||
IPW_ORD_STAT_AP_ASSNS, // # of associations
|
||||
IPW_ORD_STAT_ASSN_FAIL, // # of association failures
|
||||
|
|
|
@ -12012,7 +12012,7 @@ MODULE_PARM_DESC(rtap_iface, "create the rtap interface (1 - create, default 0)"
|
|||
|
||||
#ifdef CONFIG_IPW2200_QOS
|
||||
module_param(qos_enable, int, 0444);
|
||||
MODULE_PARM_DESC(qos_enable, "enable all QoS functionalitis");
|
||||
MODULE_PARM_DESC(qos_enable, "enable all QoS functionalities");
|
||||
|
||||
module_param(qos_burst_enable, int, 0444);
|
||||
MODULE_PARM_DESC(qos_burst_enable, "enable QoS burst mode");
|
||||
|
|
|
@ -13,7 +13,7 @@ iwlwifi-$(CONFIG_IWLMVM) += cfg/7000.o cfg/8000.o cfg/9000.o cfg/22000.o
|
|||
iwlwifi-objs += iwl-trans.o
|
||||
iwlwifi-objs += fw/notif-wait.o
|
||||
iwlwifi-$(CONFIG_IWLMVM) += fw/paging.o fw/smem.o fw/init.o fw/dbg.o
|
||||
iwlwifi-$(CONFIG_IWLMVM) += fw/common_rx.o fw/nvm.o
|
||||
iwlwifi-$(CONFIG_IWLMVM) += fw/common_rx.o
|
||||
iwlwifi-$(CONFIG_ACPI) += fw/acpi.o
|
||||
iwlwifi-$(CONFIG_IWLWIFI_DEBUGFS) += fw/debugfs.o
|
||||
|
||||
|
|
|
@ -1,6 +1,7 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
|
@ -27,7 +28,6 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/stringify.h>
|
||||
#include "iwl-config.h"
|
||||
#include "iwl-csr.h"
|
||||
#include "iwl-agn-hw.h"
|
||||
|
||||
/* Highest firmware API version supported */
|
||||
|
@ -91,7 +91,8 @@ static const struct iwl_eeprom_params iwl1000_eeprom_params = {
|
|||
.base_params = &iwl1000_base_params, \
|
||||
.eeprom_params = &iwl1000_eeprom_params, \
|
||||
.led_mode = IWL_LED_BLINK, \
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
|
||||
.csr = &iwl_csr_v1
|
||||
|
||||
const struct iwl_cfg iwl1000_bgn_cfg = {
|
||||
.name = "Intel(R) Centrino(R) Wireless-N 1000 BGN",
|
||||
|
@ -117,7 +118,8 @@ const struct iwl_cfg iwl1000_bg_cfg = {
|
|||
.eeprom_params = &iwl1000_eeprom_params, \
|
||||
.led_mode = IWL_LED_RF_STATE, \
|
||||
.rx_with_siso_diversity = true, \
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
|
||||
.csr = &iwl_csr_v1
|
||||
|
||||
const struct iwl_cfg iwl100_bgn_cfg = {
|
||||
.name = "Intel(R) Centrino(R) Wireless-N 100 BGN",
|
||||
|
|
|
@ -1,6 +1,7 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
|
@ -115,7 +116,8 @@ static const struct iwl_eeprom_params iwl20x0_eeprom_params = {
|
|||
.base_params = &iwl2000_base_params, \
|
||||
.eeprom_params = &iwl20x0_eeprom_params, \
|
||||
.led_mode = IWL_LED_RF_STATE, \
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
|
||||
.csr = &iwl_csr_v1
|
||||
|
||||
|
||||
const struct iwl_cfg iwl2000_2bgn_cfg = {
|
||||
|
@ -142,7 +144,8 @@ const struct iwl_cfg iwl2000_2bgn_d_cfg = {
|
|||
.base_params = &iwl2030_base_params, \
|
||||
.eeprom_params = &iwl20x0_eeprom_params, \
|
||||
.led_mode = IWL_LED_RF_STATE, \
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
|
||||
.csr = &iwl_csr_v1
|
||||
|
||||
const struct iwl_cfg iwl2030_2bgn_cfg = {
|
||||
.name = "Intel(R) Centrino(R) Wireless-N 2230 BGN",
|
||||
|
@ -163,7 +166,8 @@ const struct iwl_cfg iwl2030_2bgn_cfg = {
|
|||
.eeprom_params = &iwl20x0_eeprom_params, \
|
||||
.led_mode = IWL_LED_RF_STATE, \
|
||||
.rx_with_siso_diversity = true, \
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
|
||||
.csr = &iwl_csr_v1
|
||||
|
||||
const struct iwl_cfg iwl105_bgn_cfg = {
|
||||
.name = "Intel(R) Centrino(R) Wireless-N 105 BGN",
|
||||
|
@ -190,7 +194,8 @@ const struct iwl_cfg iwl105_bgn_d_cfg = {
|
|||
.eeprom_params = &iwl20x0_eeprom_params, \
|
||||
.led_mode = IWL_LED_RF_STATE, \
|
||||
.rx_with_siso_diversity = true, \
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
|
||||
.csr = &iwl_csr_v1
|
||||
|
||||
const struct iwl_cfg iwl135_bgn_cfg = {
|
||||
.name = "Intel(R) Centrino(R) Wireless-N 135 BGN",
|
||||
|
|
|
@ -54,7 +54,6 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/stringify.h>
|
||||
#include "iwl-config.h"
|
||||
#include "iwl-agn-hw.h"
|
||||
|
||||
/* Highest firmware API version supported */
|
||||
#define IWL_22000_UCODE_API_MAX 38
|
||||
|
@ -115,8 +114,6 @@ static const struct iwl_ht_params iwl_22000_ht_params = {
|
|||
.ucode_api_max = IWL_22000_UCODE_API_MAX, \
|
||||
.ucode_api_min = IWL_22000_UCODE_API_MIN, \
|
||||
.device_family = IWL_DEVICE_FAMILY_22000, \
|
||||
.max_inst_size = IWL60_RTC_INST_SIZE, \
|
||||
.max_data_size = IWL60_RTC_DATA_SIZE, \
|
||||
.base_params = &iwl_22000_base_params, \
|
||||
.led_mode = IWL_LED_RF_STATE, \
|
||||
.nvm_hw_section_num = NVM_HW_SECTION_NUM_FAMILY_22000, \
|
||||
|
@ -137,13 +134,13 @@ static const struct iwl_ht_params iwl_22000_ht_params = {
|
|||
.gen2 = true, \
|
||||
.nvm_type = IWL_NVM_EXT, \
|
||||
.dbgc_supported = true, \
|
||||
.tx_cmd_queue_size = 32, \
|
||||
.min_umac_error_event_table = 0x400000
|
||||
|
||||
const struct iwl_cfg iwl22000_2ac_cfg_hr = {
|
||||
.name = "Intel(R) Dual Band Wireless AC 22000",
|
||||
.fw_name_pre = IWL_22000_HR_FW_PRE,
|
||||
IWL_DEVICE_22000,
|
||||
.csr = &iwl_csr_v1,
|
||||
.ht_params = &iwl_22000_ht_params,
|
||||
.nvm_ver = IWL_22000_NVM_VERSION,
|
||||
.nvm_calib_ver = IWL_22000_TX_POWER_VERSION,
|
||||
|
@ -154,6 +151,7 @@ const struct iwl_cfg iwl22000_2ac_cfg_hr_cdb = {
|
|||
.name = "Intel(R) Dual Band Wireless AC 22000",
|
||||
.fw_name_pre = IWL_22000_HR_CDB_FW_PRE,
|
||||
IWL_DEVICE_22000,
|
||||
.csr = &iwl_csr_v1,
|
||||
.ht_params = &iwl_22000_ht_params,
|
||||
.nvm_ver = IWL_22000_NVM_VERSION,
|
||||
.nvm_calib_ver = IWL_22000_TX_POWER_VERSION,
|
||||
|
@ -165,6 +163,7 @@ const struct iwl_cfg iwl22000_2ac_cfg_jf = {
|
|||
.name = "Intel(R) Dual Band Wireless AC 22000",
|
||||
.fw_name_pre = IWL_22000_JF_FW_PRE,
|
||||
IWL_DEVICE_22000,
|
||||
.csr = &iwl_csr_v1,
|
||||
.ht_params = &iwl_22000_ht_params,
|
||||
.nvm_ver = IWL_22000_NVM_VERSION,
|
||||
.nvm_calib_ver = IWL_22000_TX_POWER_VERSION,
|
||||
|
@ -175,6 +174,7 @@ const struct iwl_cfg iwl22000_2ax_cfg_hr = {
|
|||
.name = "Intel(R) Dual Band Wireless AX 22000",
|
||||
.fw_name_pre = IWL_22000_HR_FW_PRE,
|
||||
IWL_DEVICE_22000,
|
||||
.csr = &iwl_csr_v1,
|
||||
.ht_params = &iwl_22000_ht_params,
|
||||
.nvm_ver = IWL_22000_NVM_VERSION,
|
||||
.nvm_calib_ver = IWL_22000_TX_POWER_VERSION,
|
||||
|
@ -185,6 +185,7 @@ const struct iwl_cfg iwl22000_2ax_cfg_qnj_hr_f0 = {
|
|||
.name = "Intel(R) Dual Band Wireless AX 22000",
|
||||
.fw_name_pre = IWL_22000_HR_F0_FW_PRE,
|
||||
IWL_DEVICE_22000,
|
||||
.csr = &iwl_csr_v1,
|
||||
.ht_params = &iwl_22000_ht_params,
|
||||
.nvm_ver = IWL_22000_NVM_VERSION,
|
||||
.nvm_calib_ver = IWL_22000_TX_POWER_VERSION,
|
||||
|
@ -195,6 +196,7 @@ const struct iwl_cfg iwl22000_2ax_cfg_qnj_jf_b0 = {
|
|||
.name = "Intel(R) Dual Band Wireless AX 22000",
|
||||
.fw_name_pre = IWL_22000_JF_B0_FW_PRE,
|
||||
IWL_DEVICE_22000,
|
||||
.csr = &iwl_csr_v1,
|
||||
.ht_params = &iwl_22000_ht_params,
|
||||
.nvm_ver = IWL_22000_NVM_VERSION,
|
||||
.nvm_calib_ver = IWL_22000_TX_POWER_VERSION,
|
||||
|
@ -205,6 +207,7 @@ const struct iwl_cfg iwl22000_2ax_cfg_qnj_hr_a0 = {
|
|||
.name = "Intel(R) Dual Band Wireless AX 22000",
|
||||
.fw_name_pre = IWL_22000_HR_A0_FW_PRE,
|
||||
IWL_DEVICE_22000,
|
||||
.csr = &iwl_csr_v1,
|
||||
.ht_params = &iwl_22000_ht_params,
|
||||
.nvm_ver = IWL_22000_NVM_VERSION,
|
||||
.nvm_calib_ver = IWL_22000_TX_POWER_VERSION,
|
||||
|
|
|
@ -1,6 +1,7 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
|
@ -28,7 +29,6 @@
|
|||
#include <linux/stringify.h>
|
||||
#include "iwl-config.h"
|
||||
#include "iwl-agn-hw.h"
|
||||
#include "iwl-csr.h"
|
||||
|
||||
/* Highest firmware API version supported */
|
||||
#define IWL5000_UCODE_API_MAX 5
|
||||
|
@ -89,7 +89,8 @@ static const struct iwl_eeprom_params iwl5000_eeprom_params = {
|
|||
.base_params = &iwl5000_base_params, \
|
||||
.eeprom_params = &iwl5000_eeprom_params, \
|
||||
.led_mode = IWL_LED_BLINK, \
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
|
||||
.csr = &iwl_csr_v1
|
||||
|
||||
const struct iwl_cfg iwl5300_agn_cfg = {
|
||||
.name = "Intel(R) Ultimate N WiFi Link 5300 AGN",
|
||||
|
@ -153,7 +154,8 @@ const struct iwl_cfg iwl5350_agn_cfg = {
|
|||
.eeprom_params = &iwl5000_eeprom_params, \
|
||||
.led_mode = IWL_LED_BLINK, \
|
||||
.internal_wimax_coex = true, \
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
|
||||
.csr = &iwl_csr_v1
|
||||
|
||||
const struct iwl_cfg iwl5150_agn_cfg = {
|
||||
.name = "Intel(R) WiMAX/WiFi Link 5150 AGN",
|
||||
|
|
|
@ -1,6 +1,7 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
|
@ -135,7 +136,8 @@ static const struct iwl_eeprom_params iwl6000_eeprom_params = {
|
|||
.base_params = &iwl6000_g2_base_params, \
|
||||
.eeprom_params = &iwl6000_eeprom_params, \
|
||||
.led_mode = IWL_LED_RF_STATE, \
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
|
||||
.csr = &iwl_csr_v1
|
||||
|
||||
const struct iwl_cfg iwl6005_2agn_cfg = {
|
||||
.name = "Intel(R) Centrino(R) Advanced-N 6205 AGN",
|
||||
|
@ -189,7 +191,8 @@ const struct iwl_cfg iwl6005_2agn_mow2_cfg = {
|
|||
.base_params = &iwl6000_g2_base_params, \
|
||||
.eeprom_params = &iwl6000_eeprom_params, \
|
||||
.led_mode = IWL_LED_RF_STATE, \
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
|
||||
.csr = &iwl_csr_v1
|
||||
|
||||
const struct iwl_cfg iwl6030_2agn_cfg = {
|
||||
.name = "Intel(R) Centrino(R) Advanced-N 6230 AGN",
|
||||
|
@ -225,7 +228,8 @@ const struct iwl_cfg iwl6030_2bg_cfg = {
|
|||
.base_params = &iwl6000_g2_base_params, \
|
||||
.eeprom_params = &iwl6000_eeprom_params, \
|
||||
.led_mode = IWL_LED_RF_STATE, \
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
|
||||
.csr = &iwl_csr_v1
|
||||
|
||||
const struct iwl_cfg iwl6035_2agn_cfg = {
|
||||
.name = "Intel(R) Centrino(R) Advanced-N 6235 AGN",
|
||||
|
@ -280,7 +284,8 @@ const struct iwl_cfg iwl130_bg_cfg = {
|
|||
.base_params = &iwl6000_base_params, \
|
||||
.eeprom_params = &iwl6000_eeprom_params, \
|
||||
.led_mode = IWL_LED_BLINK, \
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
|
||||
.csr = &iwl_csr_v1
|
||||
|
||||
const struct iwl_cfg iwl6000i_2agn_cfg = {
|
||||
.name = "Intel(R) Centrino(R) Advanced-N 6200 AGN",
|
||||
|
@ -313,7 +318,8 @@ const struct iwl_cfg iwl6000i_2bg_cfg = {
|
|||
.eeprom_params = &iwl6000_eeprom_params, \
|
||||
.led_mode = IWL_LED_BLINK, \
|
||||
.internal_wimax_coex = true, \
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
|
||||
.csr = &iwl_csr_v1
|
||||
|
||||
const struct iwl_cfg iwl6050_2agn_cfg = {
|
||||
.name = "Intel(R) Centrino(R) Advanced-N + WiMAX 6250 AGN",
|
||||
|
@ -339,7 +345,8 @@ const struct iwl_cfg iwl6050_2abg_cfg = {
|
|||
.eeprom_params = &iwl6000_eeprom_params, \
|
||||
.led_mode = IWL_LED_BLINK, \
|
||||
.internal_wimax_coex = true, \
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
|
||||
.csr = &iwl_csr_v1
|
||||
|
||||
const struct iwl_cfg iwl6150_bgn_cfg = {
|
||||
.name = "Intel(R) Centrino(R) Wireless-N + WiMAX 6150 BGN",
|
||||
|
|
|
@ -7,7 +7,8 @@
|
|||
*
|
||||
* Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2015 Intel Deutschland GmbH
|
||||
* Copyright(c) 2015 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
|
@ -34,7 +35,8 @@
|
|||
*
|
||||
* Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2015 Intel Deutschland GmbH
|
||||
* Copyright(c) 2015 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
@ -68,7 +70,6 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/stringify.h>
|
||||
#include "iwl-config.h"
|
||||
#include "iwl-agn-hw.h"
|
||||
|
||||
/* Highest firmware API version supported */
|
||||
#define IWL7260_UCODE_API_MAX 17
|
||||
|
@ -160,14 +161,13 @@ static const struct iwl_ht_params iwl7000_ht_params = {
|
|||
|
||||
#define IWL_DEVICE_7000_COMMON \
|
||||
.device_family = IWL_DEVICE_FAMILY_7000, \
|
||||
.max_inst_size = IWL60_RTC_INST_SIZE, \
|
||||
.max_data_size = IWL60_RTC_DATA_SIZE, \
|
||||
.base_params = &iwl7000_base_params, \
|
||||
.led_mode = IWL_LED_RF_STATE, \
|
||||
.nvm_hw_section_num = NVM_HW_SECTION_NUM_FAMILY_7000, \
|
||||
.non_shared_ant = ANT_A, \
|
||||
.max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
|
||||
.dccm_offset = IWL7000_DCCM_OFFSET
|
||||
.dccm_offset = IWL7000_DCCM_OFFSET, \
|
||||
.csr = &iwl_csr_v1
|
||||
|
||||
#define IWL_DEVICE_7000 \
|
||||
IWL_DEVICE_7000_COMMON, \
|
||||
|
|
|
@ -7,7 +7,8 @@
|
|||
*
|
||||
* Copyright(c) 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2014 - 2015 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2016 Intel Deutschland GmbH
|
||||
* Copyright(c) 2016 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
|
@ -34,6 +35,7 @@
|
|||
*
|
||||
* Copyright(c) 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2014 - 2015 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
@ -67,7 +69,6 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/stringify.h>
|
||||
#include "iwl-config.h"
|
||||
#include "iwl-agn-hw.h"
|
||||
|
||||
/* Highest firmware API version supported */
|
||||
#define IWL8000_UCODE_API_MAX 36
|
||||
|
@ -140,8 +141,6 @@ static const struct iwl_tt_params iwl8000_tt_params = {
|
|||
|
||||
#define IWL_DEVICE_8000_COMMON \
|
||||
.device_family = IWL_DEVICE_FAMILY_8000, \
|
||||
.max_inst_size = IWL60_RTC_INST_SIZE, \
|
||||
.max_data_size = IWL60_RTC_DATA_SIZE, \
|
||||
.base_params = &iwl8000_base_params, \
|
||||
.led_mode = IWL_LED_RF_STATE, \
|
||||
.nvm_hw_section_num = NVM_HW_SECTION_NUM_FAMILY_8000, \
|
||||
|
@ -158,7 +157,8 @@ static const struct iwl_tt_params iwl8000_tt_params = {
|
|||
.apmg_not_supported = true, \
|
||||
.nvm_type = IWL_NVM_EXT, \
|
||||
.dbgc_supported = true, \
|
||||
.min_umac_error_event_table = 0x800000
|
||||
.min_umac_error_event_table = 0x800000, \
|
||||
.csr = &iwl_csr_v1
|
||||
|
||||
#define IWL_DEVICE_8000 \
|
||||
IWL_DEVICE_8000_COMMON, \
|
||||
|
|
|
@ -54,7 +54,6 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/stringify.h>
|
||||
#include "iwl-config.h"
|
||||
#include "iwl-agn-hw.h"
|
||||
#include "fw/file.h"
|
||||
|
||||
/* Highest firmware API version supported */
|
||||
|
@ -135,8 +134,6 @@ static const struct iwl_tt_params iwl9000_tt_params = {
|
|||
.ucode_api_max = IWL9000_UCODE_API_MAX, \
|
||||
.ucode_api_min = IWL9000_UCODE_API_MIN, \
|
||||
.device_family = IWL_DEVICE_FAMILY_9000, \
|
||||
.max_inst_size = IWL60_RTC_INST_SIZE, \
|
||||
.max_data_size = IWL60_RTC_DATA_SIZE, \
|
||||
.base_params = &iwl9000_base_params, \
|
||||
.led_mode = IWL_LED_RF_STATE, \
|
||||
.nvm_hw_section_num = NVM_HW_SECTION_NUM_FAMILY_9000, \
|
||||
|
@ -156,7 +153,8 @@ static const struct iwl_tt_params iwl9000_tt_params = {
|
|||
.rf_id = true, \
|
||||
.nvm_type = IWL_NVM_EXT, \
|
||||
.dbgc_supported = true, \
|
||||
.min_umac_error_event_table = 0x800000
|
||||
.min_umac_error_event_table = 0x800000, \
|
||||
.csr = &iwl_csr_v1
|
||||
|
||||
const struct iwl_cfg iwl9160_2ac_cfg = {
|
||||
.name = "Intel(R) Dual Band Wireless AC 9160",
|
||||
|
|
|
@ -1200,16 +1200,16 @@ static int iwl_eeprom_init_hw_params(struct iwl_priv *priv)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!data->sku_cap_11n_enable && !data->sku_cap_band_24GHz_enable &&
|
||||
!data->sku_cap_band_52GHz_enable) {
|
||||
if (!data->sku_cap_11n_enable && !data->sku_cap_band_24ghz_enable &&
|
||||
!data->sku_cap_band_52ghz_enable) {
|
||||
IWL_ERR(priv, "Invalid device sku\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
IWL_DEBUG_INFO(priv,
|
||||
"Device SKU: 24GHz %s %s, 52GHz %s %s, 11.n %s %s\n",
|
||||
data->sku_cap_band_24GHz_enable ? "" : "NOT", "enabled",
|
||||
data->sku_cap_band_52GHz_enable ? "" : "NOT", "enabled",
|
||||
data->sku_cap_band_24ghz_enable ? "" : "NOT", "enabled",
|
||||
data->sku_cap_band_52ghz_enable ? "" : "NOT", "enabled",
|
||||
data->sku_cap_11n_enable ? "" : "NOT", "enabled");
|
||||
|
||||
priv->hw_params.tx_chains_num =
|
||||
|
|
|
@ -87,11 +87,6 @@ enum iwl_data_path_subcmd_ids {
|
|||
*/
|
||||
TLC_MNG_CONFIG_CMD = 0xF,
|
||||
|
||||
/**
|
||||
* @TLC_MNG_NOTIF_REQ_CMD: &struct iwl_tlc_notif_req_config_cmd
|
||||
*/
|
||||
TLC_MNG_NOTIF_REQ_CMD = 0x10,
|
||||
|
||||
/**
|
||||
* @TLC_MNG_UPDATE_NOTIF: &struct iwl_tlc_update_notif
|
||||
*/
|
||||
|
|
|
@ -189,23 +189,37 @@ struct iwl_nvm_get_info_general {
|
|||
u8 reserved;
|
||||
} __packed; /* GRP_REGULATORY_NVM_GET_INFO_GENERAL_S_VER_1 */
|
||||
|
||||
/**
|
||||
* enum iwl_nvm_mac_sku_flags - flags in &iwl_nvm_get_info_sku
|
||||
* @NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED: true if 2.4 band enabled
|
||||
* @NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED: true if 5.2 band enabled
|
||||
* @NVM_MAC_SKU_FLAGS_802_11N_ENABLED: true if 11n enabled
|
||||
* @NVM_MAC_SKU_FLAGS_802_11AC_ENABLED: true if 11ac enabled
|
||||
* @NVM_MAC_SKU_FLAGS_802_11AX_ENABLED: true if 11ax enabled
|
||||
* @NVM_MAC_SKU_FLAGS_MIMO_DISABLED: true if MIMO disabled
|
||||
* @NVM_MAC_SKU_FLAGS_WAPI_ENABLED: true if WAPI enabled
|
||||
* @NVM_MAC_SKU_FLAGS_REG_CHECK_ENABLED: true if regulatory checker enabled
|
||||
* @NVM_MAC_SKU_FLAGS_API_LOCK_ENABLED: true if API lock enabled
|
||||
*/
|
||||
enum iwl_nvm_mac_sku_flags {
|
||||
NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED = BIT(0),
|
||||
NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED = BIT(1),
|
||||
NVM_MAC_SKU_FLAGS_802_11N_ENABLED = BIT(2),
|
||||
NVM_MAC_SKU_FLAGS_802_11AC_ENABLED = BIT(3),
|
||||
NVM_MAC_SKU_FLAGS_802_11AX_ENABLED = BIT(4),
|
||||
NVM_MAC_SKU_FLAGS_MIMO_DISABLED = BIT(5),
|
||||
NVM_MAC_SKU_FLAGS_WAPI_ENABLED = BIT(8),
|
||||
NVM_MAC_SKU_FLAGS_REG_CHECK_ENABLED = BIT(14),
|
||||
NVM_MAC_SKU_FLAGS_API_LOCK_ENABLED = BIT(15),
|
||||
};
|
||||
|
||||
/**
|
||||
* struct iwl_nvm_get_info_sku - mac information
|
||||
* @enable_24g: band 2.4G enabled
|
||||
* @enable_5g: band 5G enabled
|
||||
* @enable_11n: 11n enabled
|
||||
* @enable_11ac: 11ac enabled
|
||||
* @mimo_disable: MIMO enabled
|
||||
* @ext_crypto: Extended crypto enabled
|
||||
* @mac_sku_flags: flags for SKU, see &enum iwl_nvm_mac_sku_flags
|
||||
*/
|
||||
struct iwl_nvm_get_info_sku {
|
||||
__le32 enable_24g;
|
||||
__le32 enable_5g;
|
||||
__le32 enable_11n;
|
||||
__le32 enable_11ac;
|
||||
__le32 mimo_disable;
|
||||
__le32 ext_crypto;
|
||||
} __packed; /* GRP_REGULATORY_NVM_GET_INFO_MAC_SKU_SECTION_S_VER_1 */
|
||||
__le32 mac_sku_flags;
|
||||
} __packed; /* REGULATORY_NVM_GET_INFO_MAC_SKU_SECTION_S_VER_2 */
|
||||
|
||||
/**
|
||||
* struct iwl_nvm_get_info_phy - phy information
|
||||
|
@ -243,7 +257,7 @@ struct iwl_nvm_get_info_rsp {
|
|||
struct iwl_nvm_get_info_sku mac_sku;
|
||||
struct iwl_nvm_get_info_phy phy_sku;
|
||||
struct iwl_nvm_get_info_regulatory regulatory;
|
||||
} __packed; /* GRP_REGULATORY_NVM_GET_INFO_CMD_RSP_S_VER_1 */
|
||||
} __packed; /* GRP_REGULATORY_NVM_GET_INFO_CMD_RSP_S_VER_2 */
|
||||
|
||||
/**
|
||||
* struct iwl_nvm_access_complete_cmd - NVM_ACCESS commands are completed
|
||||
|
|
|
@ -7,6 +7,7 @@
|
|||
*
|
||||
* Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2017 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
|
@ -28,6 +29,7 @@
|
|||
*
|
||||
* Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2017 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
@ -64,62 +66,38 @@
|
|||
|
||||
/**
|
||||
* enum iwl_tlc_mng_cfg_flags_enum - options for TLC config flags
|
||||
* @IWL_TLC_MNG_CFG_FLAGS_CCK_MSK: CCK support
|
||||
* @IWL_TLC_MNG_CFG_FLAGS_DD_MSK: enable DD
|
||||
* @IWL_TLC_MNG_CFG_FLAGS_STBC_MSK: enable STBC
|
||||
* @IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK: enable LDPC
|
||||
* @IWL_TLC_MNG_CFG_FLAGS_BF_MSK: enable BFER
|
||||
* @IWL_TLC_MNG_CFG_FLAGS_DCM_MSK: enable DCM
|
||||
*/
|
||||
enum iwl_tlc_mng_cfg_flags {
|
||||
IWL_TLC_MNG_CFG_FLAGS_CCK_MSK = BIT(0),
|
||||
IWL_TLC_MNG_CFG_FLAGS_DD_MSK = BIT(1),
|
||||
IWL_TLC_MNG_CFG_FLAGS_STBC_MSK = BIT(2),
|
||||
IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK = BIT(3),
|
||||
IWL_TLC_MNG_CFG_FLAGS_BF_MSK = BIT(4),
|
||||
IWL_TLC_MNG_CFG_FLAGS_DCM_MSK = BIT(5),
|
||||
IWL_TLC_MNG_CFG_FLAGS_STBC_MSK = BIT(0),
|
||||
IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK = BIT(1),
|
||||
};
|
||||
|
||||
/**
|
||||
* enum iwl_tlc_mng_cfg_cw - channel width options
|
||||
* @IWL_TLC_MNG_MAX_CH_WIDTH_20MHZ: 20MHZ channel
|
||||
* @IWL_TLC_MNG_MAX_CH_WIDTH_40MHZ: 40MHZ channel
|
||||
* @IWL_TLC_MNG_MAX_CH_WIDTH_80MHZ: 80MHZ channel
|
||||
* @IWL_TLC_MNG_MAX_CH_WIDTH_160MHZ: 160MHZ channel
|
||||
* @IWL_TLC_MNG_MAX_CH_WIDTH_LAST: maximum value
|
||||
* @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
|
||||
* @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
|
||||
* @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
|
||||
* @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
|
||||
* @IWL_TLC_MNG_CH_WIDTH_LAST: maximum value
|
||||
*/
|
||||
enum iwl_tlc_mng_cfg_cw {
|
||||
IWL_TLC_MNG_MAX_CH_WIDTH_20MHZ,
|
||||
IWL_TLC_MNG_MAX_CH_WIDTH_40MHZ,
|
||||
IWL_TLC_MNG_MAX_CH_WIDTH_80MHZ,
|
||||
IWL_TLC_MNG_MAX_CH_WIDTH_160MHZ,
|
||||
IWL_TLC_MNG_MAX_CH_WIDTH_LAST = IWL_TLC_MNG_MAX_CH_WIDTH_160MHZ,
|
||||
IWL_TLC_MNG_CH_WIDTH_20MHZ,
|
||||
IWL_TLC_MNG_CH_WIDTH_40MHZ,
|
||||
IWL_TLC_MNG_CH_WIDTH_80MHZ,
|
||||
IWL_TLC_MNG_CH_WIDTH_160MHZ,
|
||||
IWL_TLC_MNG_CH_WIDTH_LAST = IWL_TLC_MNG_CH_WIDTH_160MHZ,
|
||||
};
|
||||
|
||||
/**
|
||||
* enum iwl_tlc_mng_cfg_chains - possible chains
|
||||
* @IWL_TLC_MNG_CHAIN_A_MSK: chain A
|
||||
* @IWL_TLC_MNG_CHAIN_B_MSK: chain B
|
||||
* @IWL_TLC_MNG_CHAIN_C_MSK: chain C
|
||||
*/
|
||||
enum iwl_tlc_mng_cfg_chains {
|
||||
IWL_TLC_MNG_CHAIN_A_MSK = BIT(0),
|
||||
IWL_TLC_MNG_CHAIN_B_MSK = BIT(1),
|
||||
IWL_TLC_MNG_CHAIN_C_MSK = BIT(2),
|
||||
};
|
||||
|
||||
/**
|
||||
* enum iwl_tlc_mng_cfg_gi - guard interval options
|
||||
* @IWL_TLC_MNG_SGI_20MHZ_MSK: enable short GI for 20MHZ
|
||||
* @IWL_TLC_MNG_SGI_40MHZ_MSK: enable short GI for 40MHZ
|
||||
* @IWL_TLC_MNG_SGI_80MHZ_MSK: enable short GI for 80MHZ
|
||||
* @IWL_TLC_MNG_SGI_160MHZ_MSK: enable short GI for 160MHZ
|
||||
*/
|
||||
enum iwl_tlc_mng_cfg_gi {
|
||||
IWL_TLC_MNG_SGI_20MHZ_MSK = BIT(0),
|
||||
IWL_TLC_MNG_SGI_40MHZ_MSK = BIT(1),
|
||||
IWL_TLC_MNG_SGI_80MHZ_MSK = BIT(2),
|
||||
IWL_TLC_MNG_SGI_160MHZ_MSK = BIT(3),
|
||||
};
|
||||
|
||||
/**
|
||||
|
@ -145,25 +123,7 @@ enum iwl_tlc_mng_cfg_mode {
|
|||
};
|
||||
|
||||
/**
|
||||
* enum iwl_tlc_mng_vht_he_types - VHT HE types
|
||||
* @IWL_TLC_MNG_VALID_VHT_HE_TYPES_SU: VHT HT single user
|
||||
* @IWL_TLC_MNG_VALID_VHT_HE_TYPES_SU_EXT: VHT HT single user extended
|
||||
* @IWL_TLC_MNG_VALID_VHT_HE_TYPES_MU: VHT HT multiple users
|
||||
* @IWL_TLC_MNG_VALID_VHT_HE_TYPES_TRIG_BASED: trigger based
|
||||
* @IWL_TLC_MNG_VALID_VHT_HE_TYPES_NUM: a count of possible types
|
||||
*/
|
||||
enum iwl_tlc_mng_vht_he_types {
|
||||
IWL_TLC_MNG_VALID_VHT_HE_TYPES_SU = 0,
|
||||
IWL_TLC_MNG_VALID_VHT_HE_TYPES_SU_EXT,
|
||||
IWL_TLC_MNG_VALID_VHT_HE_TYPES_MU,
|
||||
IWL_TLC_MNG_VALID_VHT_HE_TYPES_TRIG_BASED,
|
||||
IWL_TLC_MNG_VALID_VHT_HE_TYPES_NUM =
|
||||
IWL_TLC_MNG_VALID_VHT_HE_TYPES_TRIG_BASED,
|
||||
|
||||
};
|
||||
|
||||
/**
|
||||
* enum iwl_tlc_mng_ht_rates - HT/VHT rates
|
||||
* enum iwl_tlc_mng_ht_rates - HT/VHT/HE rates
|
||||
* @IWL_TLC_MNG_HT_RATE_MCS0: index of MCS0
|
||||
* @IWL_TLC_MNG_HT_RATE_MCS1: index of MCS1
|
||||
* @IWL_TLC_MNG_HT_RATE_MCS2: index of MCS2
|
||||
|
@ -174,6 +134,8 @@ enum iwl_tlc_mng_vht_he_types {
|
|||
* @IWL_TLC_MNG_HT_RATE_MCS7: index of MCS7
|
||||
* @IWL_TLC_MNG_HT_RATE_MCS8: index of MCS8
|
||||
* @IWL_TLC_MNG_HT_RATE_MCS9: index of MCS9
|
||||
* @IWL_TLC_MNG_HT_RATE_MCS10: index of MCS10
|
||||
* @IWL_TLC_MNG_HT_RATE_MCS11: index of MCS11
|
||||
* @IWL_TLC_MNG_HT_RATE_MAX: maximal rate for HT/VHT
|
||||
*/
|
||||
enum iwl_tlc_mng_ht_rates {
|
||||
|
@ -187,81 +149,73 @@ enum iwl_tlc_mng_ht_rates {
|
|||
IWL_TLC_MNG_HT_RATE_MCS7,
|
||||
IWL_TLC_MNG_HT_RATE_MCS8,
|
||||
IWL_TLC_MNG_HT_RATE_MCS9,
|
||||
IWL_TLC_MNG_HT_RATE_MAX = IWL_TLC_MNG_HT_RATE_MCS9,
|
||||
IWL_TLC_MNG_HT_RATE_MCS10,
|
||||
IWL_TLC_MNG_HT_RATE_MCS11,
|
||||
IWL_TLC_MNG_HT_RATE_MAX = IWL_TLC_MNG_HT_RATE_MCS11,
|
||||
};
|
||||
|
||||
/* Maximum supported tx antennas number */
|
||||
#define MAX_RS_ANT_NUM 3
|
||||
#define MAX_NSS 2
|
||||
|
||||
/**
|
||||
* struct tlc_config_cmd - TLC configuration
|
||||
* @sta_id: station id
|
||||
* @reserved1: reserved
|
||||
* @max_supp_ch_width: channel width
|
||||
* @flags: bitmask of &enum iwl_tlc_mng_cfg_flags
|
||||
* @chains: bitmask of &enum iwl_tlc_mng_cfg_chains
|
||||
* @max_supp_ss: valid values are 0-3, 0 - spatial streams are not supported
|
||||
* @valid_vht_he_types: bitmap of &enum iwl_tlc_mng_vht_he_types
|
||||
* @non_ht_supp_rates: bitmap of supported legacy rates
|
||||
* @ht_supp_rates: bitmap of supported HT/VHT rates, valid bits are 0-9
|
||||
* @max_ch_width: max supported channel width from @enum iwl_tlc_mng_cfg_cw
|
||||
* @mode: &enum iwl_tlc_mng_cfg_mode
|
||||
* @reserved2: reserved
|
||||
* @he_supp_rates: bitmap of supported HE rates
|
||||
* @chains: bitmask of &enum iwl_tlc_mng_cfg_chains
|
||||
* @amsdu: TX amsdu is supported
|
||||
* @flags: bitmask of &enum iwl_tlc_mng_cfg_flags
|
||||
* @non_ht_rates: bitmap of supported legacy rates
|
||||
* @ht_rates: bitmap of &enum iwl_tlc_mng_ht_rates, per <nss, channel-width>
|
||||
* pair (0 - 80mhz width and below, 1 - 160mhz).
|
||||
* @max_mpdu_len: max MPDU length, in bytes
|
||||
* @sgi_ch_width_supp: bitmap of SGI support per channel width
|
||||
* @he_gi_support: 11ax HE guard interval
|
||||
* @max_ampdu_cnt: max AMPDU size (frames count)
|
||||
* use BIT(@enum iwl_tlc_mng_cfg_cw)
|
||||
* @reserved2: reserved
|
||||
*/
|
||||
struct iwl_tlc_config_cmd {
|
||||
u8 sta_id;
|
||||
u8 reserved1[3];
|
||||
u8 max_supp_ch_width;
|
||||
u8 chains;
|
||||
u8 max_supp_ss;
|
||||
u8 valid_vht_he_types;
|
||||
__le16 flags;
|
||||
__le16 non_ht_supp_rates;
|
||||
__le16 ht_supp_rates[MAX_RS_ANT_NUM];
|
||||
u8 max_ch_width;
|
||||
u8 mode;
|
||||
u8 reserved2;
|
||||
__le16 he_supp_rates;
|
||||
u8 chains;
|
||||
u8 amsdu;
|
||||
__le16 flags;
|
||||
__le16 non_ht_rates;
|
||||
__le16 ht_rates[MAX_NSS][2];
|
||||
__le16 max_mpdu_len;
|
||||
u8 sgi_ch_width_supp;
|
||||
u8 he_gi_support;
|
||||
__le32 max_ampdu_cnt;
|
||||
} __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_1 */
|
||||
|
||||
#define IWL_TLC_NOTIF_INIT_RATE_POS 0
|
||||
#define IWL_TLC_NOTIF_INIT_RATE_MSK BIT(IWL_TLC_NOTIF_INIT_RATE_POS)
|
||||
#define IWL_TLC_NOTIF_REQ_INTERVAL (500)
|
||||
u8 reserved2[1];
|
||||
} __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_2 */
|
||||
|
||||
/**
|
||||
* struct iwl_tlc_notif_req_config_cmd - request notif on specific changes
|
||||
* @sta_id: relevant station
|
||||
* @reserved1: reserved
|
||||
* @flags: bitmap of requested notifications %IWL_TLC_NOTIF_INIT_\*
|
||||
* @interval: minimum time between notifications from TLC to the driver (msec)
|
||||
* @reserved2: reserved
|
||||
* enum iwl_tlc_update_flags - updated fields
|
||||
* @IWL_TLC_NOTIF_FLAG_RATE: last initial rate update
|
||||
* @IWL_TLC_NOTIF_FLAG_AMSDU: umsdu parameters update
|
||||
*/
|
||||
struct iwl_tlc_notif_req_config_cmd {
|
||||
u8 sta_id;
|
||||
u8 reserved1;
|
||||
__le16 flags;
|
||||
__le16 interval;
|
||||
__le16 reserved2;
|
||||
} __packed; /* TLC_MNG_NOTIF_REQ_CMD_API_S_VER_1 */
|
||||
enum iwl_tlc_update_flags {
|
||||
IWL_TLC_NOTIF_FLAG_RATE = BIT(0),
|
||||
IWL_TLC_NOTIF_FLAG_AMSDU = BIT(1),
|
||||
};
|
||||
|
||||
/**
|
||||
* struct iwl_tlc_update_notif - TLC notification from FW
|
||||
* @sta_id: station id
|
||||
* @reserved: reserved
|
||||
* @flags: bitmap of notifications reported
|
||||
* @values: field per flag in struct iwl_tlc_notif_req_config_cmd
|
||||
* @rate: current initial rate
|
||||
* @amsdu_size: Max AMSDU size, in bytes
|
||||
* @amsdu_enabled: bitmap for per-TID AMSDU enablement
|
||||
*/
|
||||
struct iwl_tlc_update_notif {
|
||||
u8 sta_id;
|
||||
u8 reserved;
|
||||
__le16 flags;
|
||||
__le32 values[16];
|
||||
} __packed; /* TLC_MNG_UPDATE_NTFY_API_S_VER_1 */
|
||||
u8 reserved[3];
|
||||
__le32 flags;
|
||||
__le32 rate;
|
||||
__le32 amsdu_size;
|
||||
__le32 amsdu_enabled;
|
||||
} __packed; /* TLC_MNG_UPDATE_NTFY_API_S_VER_2 */
|
||||
|
||||
/**
|
||||
* enum iwl_tlc_debug_flags - debug options
|
||||
|
|
|
@ -131,6 +131,8 @@ enum iwl_tx_queue_cfg_actions {
|
|||
TX_QUEUE_CFG_TFD_SHORT_FORMAT = BIT(1),
|
||||
};
|
||||
|
||||
#define IWL_DEFAULT_QUEUE_SIZE 256
|
||||
#define IWL_MGMT_QUEUE_SIZE 16
|
||||
/**
|
||||
* struct iwl_tx_queue_cfg_cmd - txq hw scheduler config command
|
||||
* @sta_id: station id
|
||||
|
|
|
@ -227,4 +227,40 @@ static inline void iwl_fw_cancel_dump(struct iwl_fw_runtime *fwrt)
|
|||
cancel_delayed_work_sync(&fwrt->dump.wk);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_IWLWIFI_DEBUGFS
|
||||
static inline void iwl_fw_cancel_timestamp(struct iwl_fw_runtime *fwrt)
|
||||
{
|
||||
fwrt->timestamp.delay = 0;
|
||||
cancel_delayed_work_sync(&fwrt->timestamp.wk);
|
||||
}
|
||||
|
||||
void iwl_fw_trigger_timestamp(struct iwl_fw_runtime *fwrt, u32 delay);
|
||||
|
||||
static inline void iwl_fw_suspend_timestamp(struct iwl_fw_runtime *fwrt)
|
||||
{
|
||||
cancel_delayed_work_sync(&fwrt->timestamp.wk);
|
||||
}
|
||||
|
||||
static inline void iwl_fw_resume_timestamp(struct iwl_fw_runtime *fwrt)
|
||||
{
|
||||
if (!fwrt->timestamp.delay)
|
||||
return;
|
||||
|
||||
schedule_delayed_work(&fwrt->timestamp.wk,
|
||||
round_jiffies_relative(fwrt->timestamp.delay));
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static inline void iwl_fw_cancel_timestamp(struct iwl_fw_runtime *fwrt) {}
|
||||
|
||||
static inline void iwl_fw_trigger_timestamp(struct iwl_fw_runtime *fwrt,
|
||||
u32 delay) {}
|
||||
|
||||
static inline void iwl_fw_suspend_timestamp(struct iwl_fw_runtime *fwrt) {}
|
||||
|
||||
static inline void iwl_fw_resume_timestamp(struct iwl_fw_runtime *fwrt) {}
|
||||
|
||||
#endif /* CONFIG_IWLWIFI_DEBUGFS */
|
||||
|
||||
#endif /* __iwl_fw_dbg_h__ */
|
||||
|
|
|
@ -64,6 +64,7 @@
|
|||
*****************************************************************************/
|
||||
#include "api/commands.h"
|
||||
#include "debugfs.h"
|
||||
#include "dbg.h"
|
||||
|
||||
#define FWRT_DEBUGFS_READ_FILE_OPS(name) \
|
||||
static ssize_t iwl_dbgfs_##name##_read(struct iwl_fw_runtime *fwrt, \
|
||||
|
|
|
@ -69,28 +69,6 @@
|
|||
int iwl_fwrt_dbgfs_register(struct iwl_fw_runtime *fwrt,
|
||||
struct dentry *dbgfs_dir);
|
||||
|
||||
static inline void iwl_fw_cancel_timestamp(struct iwl_fw_runtime *fwrt)
|
||||
{
|
||||
fwrt->timestamp.delay = 0;
|
||||
cancel_delayed_work_sync(&fwrt->timestamp.wk);
|
||||
}
|
||||
|
||||
static inline void iwl_fw_suspend_timestamp(struct iwl_fw_runtime *fwrt)
|
||||
{
|
||||
cancel_delayed_work_sync(&fwrt->timestamp.wk);
|
||||
}
|
||||
|
||||
static inline void iwl_fw_resume_timestamp(struct iwl_fw_runtime *fwrt)
|
||||
{
|
||||
if (!fwrt->timestamp.delay)
|
||||
return;
|
||||
|
||||
schedule_delayed_work(&fwrt->timestamp.wk,
|
||||
round_jiffies_relative(fwrt->timestamp.delay));
|
||||
}
|
||||
|
||||
void iwl_fw_trigger_timestamp(struct iwl_fw_runtime *fwrt, u32 delay);
|
||||
|
||||
#else
|
||||
static inline int iwl_fwrt_dbgfs_register(struct iwl_fw_runtime *fwrt,
|
||||
struct dentry *dbgfs_dir)
|
||||
|
@ -98,13 +76,4 @@ static inline int iwl_fwrt_dbgfs_register(struct iwl_fw_runtime *fwrt,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static inline void iwl_fw_cancel_timestamp(struct iwl_fw_runtime *fwrt) {}
|
||||
|
||||
static inline void iwl_fw_suspend_timestamp(struct iwl_fw_runtime *fwrt) {}
|
||||
|
||||
static inline void iwl_fw_resume_timestamp(struct iwl_fw_runtime *fwrt) {}
|
||||
|
||||
static inline void iwl_fw_trigger_timestamp(struct iwl_fw_runtime *fwrt,
|
||||
u32 delay) {}
|
||||
|
||||
#endif /* CONFIG_IWLWIFI_DEBUGFS */
|
||||
|
|
|
@ -8,6 +8,7 @@
|
|||
* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
|
@ -35,6 +36,7 @@
|
|||
* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
@ -143,6 +145,7 @@ enum iwl_ucode_tlv_type {
|
|||
IWL_UCODE_TLV_FW_DBG_TRIGGER = 40,
|
||||
IWL_UCODE_TLV_FW_GSCAN_CAPA = 50,
|
||||
IWL_UCODE_TLV_FW_MEM_SEG = 51,
|
||||
IWL_UCODE_TLV_IML = 52,
|
||||
};
|
||||
|
||||
struct iwl_ucode_tlv {
|
||||
|
|
|
@ -8,6 +8,7 @@
|
|||
* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2016 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
|
@ -35,6 +36,7 @@
|
|||
* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2016 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
@ -241,6 +243,8 @@ enum iwl_fw_type {
|
|||
* @ucode_ver: ucode version from the ucode file
|
||||
* @fw_version: firmware version string
|
||||
* @img: ucode image like ucode_rt, ucode_init, ucode_wowlan.
|
||||
* @iml_len: length of the image loader image
|
||||
* @iml: image loader fw image
|
||||
* @ucode_capa: capabilities parsed from the ucode file.
|
||||
* @enhance_sensitivity_table: device can do enhanced sensitivity.
|
||||
* @init_evtlog_ptr: event log offset for init ucode.
|
||||
|
@ -267,6 +271,8 @@ struct iwl_fw {
|
|||
|
||||
/* ucode images */
|
||||
struct fw_img img[IWL_UCODE_TYPE_MAX];
|
||||
size_t iml_len;
|
||||
u8 *iml;
|
||||
|
||||
struct iwl_ucode_capabilities ucode_capa;
|
||||
bool enhance_sensitivity_table;
|
||||
|
|
|
@ -1,162 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
* redistributing this file, you may do so under either license.
|
||||
*
|
||||
* GPL LICENSE SUMMARY
|
||||
*
|
||||
* Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
|
||||
* USA
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called COPYING.
|
||||
*
|
||||
* Contact Information:
|
||||
* Intel Linux Wireless <linuxwifi@intel.com>
|
||||
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name Intel Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#include "iwl-drv.h"
|
||||
#include "runtime.h"
|
||||
#include "fw/api/nvm-reg.h"
|
||||
#include "fw/api/commands.h"
|
||||
#include "iwl-nvm-parse.h"
|
||||
|
||||
struct iwl_nvm_data *iwl_fw_get_nvm(struct iwl_fw_runtime *fwrt)
|
||||
{
|
||||
struct iwl_nvm_get_info cmd = {};
|
||||
struct iwl_nvm_get_info_rsp *rsp;
|
||||
struct iwl_trans *trans = fwrt->trans;
|
||||
struct iwl_nvm_data *nvm;
|
||||
struct iwl_host_cmd hcmd = {
|
||||
.flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
|
||||
.data = { &cmd, },
|
||||
.len = { sizeof(cmd) },
|
||||
.id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO)
|
||||
};
|
||||
int ret;
|
||||
bool lar_fw_supported = !iwlwifi_mod_params.lar_disable &&
|
||||
fw_has_capa(&fwrt->fw->ucode_capa,
|
||||
IWL_UCODE_TLV_CAPA_LAR_SUPPORT);
|
||||
|
||||
ret = iwl_trans_send_cmd(trans, &hcmd);
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != sizeof(*rsp),
|
||||
"Invalid payload len in NVM response from FW %d",
|
||||
iwl_rx_packet_payload_len(hcmd.resp_pkt))) {
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
rsp = (void *)hcmd.resp_pkt->data;
|
||||
if (le32_to_cpu(rsp->general.flags) & NVM_GENERAL_FLAGS_EMPTY_OTP)
|
||||
IWL_INFO(fwrt, "OTP is empty\n");
|
||||
|
||||
nvm = kzalloc(sizeof(*nvm) +
|
||||
sizeof(struct ieee80211_channel) * IWL_NUM_CHANNELS,
|
||||
GFP_KERNEL);
|
||||
if (!nvm) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
iwl_set_hw_address_from_csr(trans, nvm);
|
||||
/* TODO: if platform NVM has MAC address - override it here */
|
||||
|
||||
if (!is_valid_ether_addr(nvm->hw_addr)) {
|
||||
IWL_ERR(fwrt, "no valid mac address was found\n");
|
||||
ret = -EINVAL;
|
||||
goto err_free;
|
||||
}
|
||||
|
||||
IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr);
|
||||
|
||||
/* Initialize general data */
|
||||
nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version);
|
||||
|
||||
/* Initialize MAC sku data */
|
||||
nvm->sku_cap_11ac_enable =
|
||||
le32_to_cpu(rsp->mac_sku.enable_11ac);
|
||||
nvm->sku_cap_11n_enable =
|
||||
le32_to_cpu(rsp->mac_sku.enable_11n);
|
||||
nvm->sku_cap_band_24GHz_enable =
|
||||
le32_to_cpu(rsp->mac_sku.enable_24g);
|
||||
nvm->sku_cap_band_52GHz_enable =
|
||||
le32_to_cpu(rsp->mac_sku.enable_5g);
|
||||
nvm->sku_cap_mimo_disabled =
|
||||
le32_to_cpu(rsp->mac_sku.mimo_disable);
|
||||
|
||||
/* Initialize PHY sku data */
|
||||
nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains);
|
||||
nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains);
|
||||
|
||||
/* Initialize regulatory data */
|
||||
nvm->lar_enabled =
|
||||
le32_to_cpu(rsp->regulatory.lar_enabled) && lar_fw_supported;
|
||||
|
||||
iwl_init_sbands(trans->dev, trans->cfg, nvm,
|
||||
rsp->regulatory.channel_profile,
|
||||
nvm->valid_tx_ant & fwrt->fw->valid_tx_ant,
|
||||
nvm->valid_rx_ant & fwrt->fw->valid_rx_ant,
|
||||
nvm->lar_enabled, false);
|
||||
|
||||
iwl_free_resp(&hcmd);
|
||||
return nvm;
|
||||
|
||||
err_free:
|
||||
kfree(nvm);
|
||||
out:
|
||||
iwl_free_resp(&hcmd);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
IWL_EXPORT_SYMBOL(iwl_fw_get_nvm);
|
|
@ -8,6 +8,7 @@
|
|||
* Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
|
@ -30,6 +31,7 @@
|
|||
* Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
@ -163,7 +165,7 @@ static int iwl_alloc_fw_paging_mem(struct iwl_fw_runtime *fwrt,
|
|||
static int iwl_fill_paging_mem(struct iwl_fw_runtime *fwrt,
|
||||
const struct fw_img *image)
|
||||
{
|
||||
int sec_idx, idx;
|
||||
int sec_idx, idx, ret;
|
||||
u32 offset = 0;
|
||||
|
||||
/*
|
||||
|
@ -190,17 +192,23 @@ static int iwl_fill_paging_mem(struct iwl_fw_runtime *fwrt,
|
|||
*/
|
||||
if (sec_idx >= image->num_sec - 1) {
|
||||
IWL_ERR(fwrt, "Paging: Missing CSS and/or paging sections\n");
|
||||
iwl_free_fw_paging(fwrt);
|
||||
return -EINVAL;
|
||||
ret = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* copy the CSS block to the dram */
|
||||
IWL_DEBUG_FW(fwrt, "Paging: load paging CSS to FW, sec = %d\n",
|
||||
sec_idx);
|
||||
|
||||
if (image->sec[sec_idx].len > fwrt->fw_paging_db[0].fw_paging_size) {
|
||||
IWL_ERR(fwrt, "CSS block is larger than paging size\n");
|
||||
ret = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
memcpy(page_address(fwrt->fw_paging_db[0].fw_paging_block),
|
||||
image->sec[sec_idx].data,
|
||||
fwrt->fw_paging_db[0].fw_paging_size);
|
||||
image->sec[sec_idx].len);
|
||||
dma_sync_single_for_device(fwrt->trans->dev,
|
||||
fwrt->fw_paging_db[0].fw_paging_phys,
|
||||
fwrt->fw_paging_db[0].fw_paging_size,
|
||||
|
@ -213,17 +221,39 @@ static int iwl_fill_paging_mem(struct iwl_fw_runtime *fwrt,
|
|||
sec_idx++;
|
||||
|
||||
/*
|
||||
* copy the paging blocks to the dram
|
||||
* loop index start from 1 since that CSS block already copied to dram
|
||||
* and CSS index is 0.
|
||||
* loop stop at num_of_paging_blk since that last block is not full.
|
||||
* Copy the paging blocks to the dram. The loop index starts
|
||||
* from 1 since the CSS block (index 0) was already copied to
|
||||
* dram. We use num_of_paging_blk + 1 to account for that.
|
||||
*/
|
||||
for (idx = 1; idx < fwrt->num_of_paging_blk; idx++) {
|
||||
for (idx = 1; idx < fwrt->num_of_paging_blk + 1; idx++) {
|
||||
struct iwl_fw_paging *block = &fwrt->fw_paging_db[idx];
|
||||
int remaining = image->sec[sec_idx].len - offset;
|
||||
int len = block->fw_paging_size;
|
||||
|
||||
/*
|
||||
* For the last block, we copy all that is remaining,
|
||||
* for all other blocks, we copy fw_paging_size at a
|
||||
* time. */
|
||||
if (idx == fwrt->num_of_paging_blk) {
|
||||
len = remaining;
|
||||
if (remaining !=
|
||||
fwrt->num_of_pages_in_last_blk * FW_PAGING_SIZE) {
|
||||
IWL_ERR(fwrt,
|
||||
"Paging: last block contains more data than expected %d\n",
|
||||
remaining);
|
||||
ret = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
} else if (block->fw_paging_size > remaining) {
|
||||
IWL_ERR(fwrt,
|
||||
"Paging: not enough data in other in block %d (%d)\n",
|
||||
idx, remaining);
|
||||
ret = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
memcpy(page_address(block->fw_paging_block),
|
||||
image->sec[sec_idx].data + offset,
|
||||
block->fw_paging_size);
|
||||
image->sec[sec_idx].data + offset, len);
|
||||
dma_sync_single_for_device(fwrt->trans->dev,
|
||||
block->fw_paging_phys,
|
||||
block->fw_paging_size,
|
||||
|
@ -231,30 +261,16 @@ static int iwl_fill_paging_mem(struct iwl_fw_runtime *fwrt,
|
|||
|
||||
IWL_DEBUG_FW(fwrt,
|
||||
"Paging: copied %d paging bytes to block %d\n",
|
||||
fwrt->fw_paging_db[idx].fw_paging_size,
|
||||
idx);
|
||||
len, idx);
|
||||
|
||||
offset += fwrt->fw_paging_db[idx].fw_paging_size;
|
||||
}
|
||||
|
||||
/* copy the last paging block */
|
||||
if (fwrt->num_of_pages_in_last_blk > 0) {
|
||||
struct iwl_fw_paging *block = &fwrt->fw_paging_db[idx];
|
||||
|
||||
memcpy(page_address(block->fw_paging_block),
|
||||
image->sec[sec_idx].data + offset,
|
||||
FW_PAGING_SIZE * fwrt->num_of_pages_in_last_blk);
|
||||
dma_sync_single_for_device(fwrt->trans->dev,
|
||||
block->fw_paging_phys,
|
||||
block->fw_paging_size,
|
||||
DMA_BIDIRECTIONAL);
|
||||
|
||||
IWL_DEBUG_FW(fwrt,
|
||||
"Paging: copied %d pages in the last block %d\n",
|
||||
fwrt->num_of_pages_in_last_blk, idx);
|
||||
offset += block->fw_paging_size;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
iwl_free_fw_paging(fwrt);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int iwl_save_fw_paging(struct iwl_fw_runtime *fwrt,
|
||||
|
|
|
@ -170,6 +170,5 @@ void iwl_get_shared_mem_conf(struct iwl_fw_runtime *fwrt);
|
|||
|
||||
void iwl_fwrt_handle_notification(struct iwl_fw_runtime *fwrt,
|
||||
struct iwl_rx_cmd_buffer *rxb);
|
||||
struct iwl_nvm_data *iwl_fw_get_nvm(struct iwl_fw_runtime *fwrt);
|
||||
|
||||
#endif /* __iwl_fw_runtime_h__ */
|
||||
|
|
|
@ -7,6 +7,7 @@
|
|||
*
|
||||
* Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright (C) 2016 - 2017 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
|
@ -33,6 +34,7 @@
|
|||
*
|
||||
* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright (C) 2016 - 2017 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
@ -69,6 +71,7 @@
|
|||
#include <linux/netdevice.h>
|
||||
#include <linux/ieee80211.h>
|
||||
#include <linux/nl80211.h>
|
||||
#include "iwl-csr.h"
|
||||
|
||||
enum iwl_device_family {
|
||||
IWL_DEVICE_FAMILY_UNDEFINED,
|
||||
|
@ -151,6 +154,8 @@ enum iwl_nvm_type {
|
|||
#define ANT_AC (ANT_A | ANT_C)
|
||||
#define ANT_BC (ANT_B | ANT_C)
|
||||
#define ANT_ABC (ANT_A | ANT_B | ANT_C)
|
||||
#define MAX_ANT_NUM 3
|
||||
|
||||
|
||||
static inline u8 num_of_ant(u8 mask)
|
||||
{
|
||||
|
@ -282,6 +287,52 @@ struct iwl_pwr_tx_backoff {
|
|||
u32 backoff;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct iwl_csr_params
|
||||
*
|
||||
* @flag_sw_reset: reset the device
|
||||
* @flag_mac_clock_ready:
|
||||
* Indicates MAC (ucode processor, etc.) is powered up and can run.
|
||||
* Internal resources are accessible.
|
||||
* NOTE: This does not indicate that the processor is actually running.
|
||||
* NOTE: This does not indicate that device has completed
|
||||
* init or post-power-down restore of internal SRAM memory.
|
||||
* Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
|
||||
* SRAM is restored and uCode is in normal operation mode.
|
||||
* This note is relevant only for pre 5xxx devices.
|
||||
* NOTE: After device reset, this bit remains "0" until host sets
|
||||
* INIT_DONE
|
||||
* @flag_init_done: Host sets this to put device into fully operational
|
||||
* D0 power mode. Host resets this after SW_RESET to put device into
|
||||
* low power mode.
|
||||
* @flag_mac_access_req: Host sets this to request and maintain MAC wakeup,
|
||||
* to allow host access to device-internal resources. Host must wait for
|
||||
* mac_clock_ready (and !GOING_TO_SLEEP) before accessing non-CSR device
|
||||
* registers.
|
||||
* @flag_val_mac_access_en: mac access is enabled
|
||||
* @flag_master_dis: disable master
|
||||
* @flag_stop_master: stop master
|
||||
* @addr_sw_reset: address for resetting the device
|
||||
* @mac_addr0_otp: first part of MAC address from OTP
|
||||
* @mac_addr1_otp: second part of MAC address from OTP
|
||||
* @mac_addr0_strap: first part of MAC address from strap
|
||||
* @mac_addr1_strap: second part of MAC address from strap
|
||||
*/
|
||||
struct iwl_csr_params {
|
||||
u8 flag_sw_reset;
|
||||
u8 flag_mac_clock_ready;
|
||||
u8 flag_init_done;
|
||||
u8 flag_mac_access_req;
|
||||
u8 flag_val_mac_access_en;
|
||||
u8 flag_master_dis;
|
||||
u8 flag_stop_master;
|
||||
u8 addr_sw_reset;
|
||||
u32 mac_addr0_otp;
|
||||
u32 mac_addr1_otp;
|
||||
u32 mac_addr0_strap;
|
||||
u32 mac_addr1_strap;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct iwl_cfg
|
||||
* @name: Official name of the device
|
||||
|
@ -294,8 +345,8 @@ struct iwl_pwr_tx_backoff {
|
|||
* next step. Supported only in integrated solutions.
|
||||
* @ucode_api_max: Highest version of uCode API supported by driver.
|
||||
* @ucode_api_min: Lowest version of uCode API supported by driver.
|
||||
* @max_inst_size: The maximal length of the fw inst section
|
||||
* @max_data_size: The maximal length of the fw data section
|
||||
* @max_inst_size: The maximal length of the fw inst section (only DVM)
|
||||
* @max_data_size: The maximal length of the fw data section (only DVM)
|
||||
* @valid_tx_ant: valid transmit antenna
|
||||
* @valid_rx_ant: valid receive antenna
|
||||
* @non_shared_ant: the antenna that is for WiFi only
|
||||
|
@ -314,6 +365,7 @@ struct iwl_pwr_tx_backoff {
|
|||
* @mac_addr_from_csr: read HW address from CSR registers
|
||||
* @features: hw features, any combination of feature_whitelist
|
||||
* @pwr_tx_backoffs: translation table between power limits and backoffs
|
||||
* @csr: csr flags and addresses that are different across devices
|
||||
* @max_rx_agg_size: max RX aggregation size of the ADDBA request/response
|
||||
* @max_tx_agg_size: max TX aggregation size of the ADDBA request/response
|
||||
* @max_ht_ampdu_factor: the exponent of the max length of A-MPDU that the
|
||||
|
@ -333,8 +385,6 @@ struct iwl_pwr_tx_backoff {
|
|||
* @gen2: 22000 and on transport operation
|
||||
* @cdb: CDB support
|
||||
* @nvm_type: see &enum iwl_nvm_type
|
||||
* @tx_cmd_queue_size: size of the cmd queue. If zero, use the same value as
|
||||
* the regular queues
|
||||
*
|
||||
* We enable the driver to be backward compatible wrt. hardware features.
|
||||
* API differences in uCode shouldn't be handled here but through TLVs
|
||||
|
@ -354,6 +404,7 @@ struct iwl_cfg {
|
|||
const struct iwl_pwr_tx_backoff *pwr_tx_backoffs;
|
||||
const char *default_nvm_file_C_step;
|
||||
const struct iwl_tt_params *thermal_params;
|
||||
const struct iwl_csr_params *csr;
|
||||
enum iwl_device_family device_family;
|
||||
enum iwl_led_mode led_mode;
|
||||
enum iwl_nvm_type nvm_type;
|
||||
|
@ -369,7 +420,7 @@ struct iwl_cfg {
|
|||
u32 soc_latency;
|
||||
u16 nvm_ver;
|
||||
u16 nvm_calib_ver;
|
||||
u16 rx_with_siso_diversity:1,
|
||||
u32 rx_with_siso_diversity:1,
|
||||
bt_shared_single_ant:1,
|
||||
internal_wimax_coex:1,
|
||||
host_interrupt_operation_mode:1,
|
||||
|
@ -386,7 +437,6 @@ struct iwl_cfg {
|
|||
gen2:1,
|
||||
cdb:1,
|
||||
dbgc_supported:1;
|
||||
u16 tx_cmd_queue_size;
|
||||
u8 valid_tx_ant;
|
||||
u8 valid_rx_ant;
|
||||
u8 non_shared_ant;
|
||||
|
@ -401,6 +451,36 @@ struct iwl_cfg {
|
|||
u32 extra_phy_cfg_flags;
|
||||
};
|
||||
|
||||
static const struct iwl_csr_params iwl_csr_v1 = {
|
||||
.flag_mac_clock_ready = 0,
|
||||
.flag_val_mac_access_en = 0,
|
||||
.flag_init_done = 2,
|
||||
.flag_mac_access_req = 3,
|
||||
.flag_sw_reset = 7,
|
||||
.flag_master_dis = 8,
|
||||
.flag_stop_master = 9,
|
||||
.addr_sw_reset = (CSR_BASE + 0x020),
|
||||
.mac_addr0_otp = 0x380,
|
||||
.mac_addr1_otp = 0x384,
|
||||
.mac_addr0_strap = 0x388,
|
||||
.mac_addr1_strap = 0x38C
|
||||
};
|
||||
|
||||
static const struct iwl_csr_params iwl_csr_v2 = {
|
||||
.flag_init_done = 6,
|
||||
.flag_mac_clock_ready = 20,
|
||||
.flag_val_mac_access_en = 20,
|
||||
.flag_mac_access_req = 21,
|
||||
.flag_master_dis = 28,
|
||||
.flag_stop_master = 29,
|
||||
.flag_sw_reset = 31,
|
||||
.addr_sw_reset = (CSR_BASE + 0x024),
|
||||
.mac_addr0_otp = 0x30,
|
||||
.mac_addr1_otp = 0x34,
|
||||
.mac_addr0_strap = 0x38,
|
||||
.mac_addr1_strap = 0x3C
|
||||
};
|
||||
|
||||
/*
|
||||
* This list declares the config structures for all devices.
|
||||
*/
|
||||
|
|
|
@ -8,6 +8,7 @@
|
|||
* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2016 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
|
@ -34,6 +35,7 @@
|
|||
*
|
||||
* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
@ -257,7 +259,6 @@
|
|||
/* RESET */
|
||||
#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
|
||||
#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
|
||||
#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
|
||||
#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
|
||||
#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
|
||||
#define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
|
||||
|
@ -280,35 +281,10 @@
|
|||
* 4: GOING_TO_SLEEP
|
||||
* Indicates MAC is entering a power-saving sleep power-down.
|
||||
* Not a good time to access device-internal resources.
|
||||
* 3: MAC_ACCESS_REQ
|
||||
* Host sets this to request and maintain MAC wakeup, to allow host
|
||||
* access to device-internal resources. Host must wait for
|
||||
* MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
|
||||
* device registers.
|
||||
* 2: INIT_DONE
|
||||
* Host sets this to put device into fully operational D0 power mode.
|
||||
* Host resets this after SW_RESET to put device into low power mode.
|
||||
* 0: MAC_CLOCK_READY
|
||||
* Indicates MAC (ucode processor, etc.) is powered up and can run.
|
||||
* Internal resources are accessible.
|
||||
* NOTE: This does not indicate that the processor is actually running.
|
||||
* NOTE: This does not indicate that device has completed
|
||||
* init or post-power-down restore of internal SRAM memory.
|
||||
* Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
|
||||
* SRAM is restored and uCode is in normal operation mode.
|
||||
* Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
|
||||
* do not need to save/restore it.
|
||||
* NOTE: After device reset, this bit remains "0" until host sets
|
||||
* INIT_DONE
|
||||
*/
|
||||
#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
|
||||
#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
|
||||
#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
|
||||
#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
|
||||
#define CSR_GP_CNTRL_REG_FLAG_XTAL_ON (0x00000400)
|
||||
|
||||
#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
|
||||
|
||||
#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
|
||||
#define CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000)
|
||||
#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
|
||||
|
|
|
@ -179,6 +179,7 @@ static void iwl_dealloc_ucode(struct iwl_drv *drv)
|
|||
for (i = 0; i < ARRAY_SIZE(drv->fw.dbg_trigger_tlv); i++)
|
||||
kfree(drv->fw.dbg_trigger_tlv[i]);
|
||||
kfree(drv->fw.dbg_mem_tlv);
|
||||
kfree(drv->fw.iml);
|
||||
|
||||
for (i = 0; i < IWL_UCODE_TYPE_MAX; i++)
|
||||
iwl_free_fw_img(drv, drv->fw.img + i);
|
||||
|
@ -1126,6 +1127,13 @@ static int iwl_parse_tlv_firmware(struct iwl_drv *drv,
|
|||
pieces->n_dbg_mem_tlv++;
|
||||
break;
|
||||
}
|
||||
case IWL_UCODE_TLV_IML: {
|
||||
drv->fw.iml_len = tlv_len;
|
||||
drv->fw.iml = kmemdup(tlv_data, tlv_len, GFP_KERNEL);
|
||||
if (!drv->fw.iml)
|
||||
return -ENOMEM;
|
||||
break;
|
||||
}
|
||||
default:
|
||||
IWL_DEBUG_INFO(drv, "unknown TLV: %d\n", tlv_type);
|
||||
break;
|
||||
|
@ -1842,3 +1850,9 @@ MODULE_PARM_DESC(d0i3_timeout, "Timeout to D0i3 entry when idle (ms)");
|
|||
|
||||
module_param_named(disable_11ac, iwlwifi_mod_params.disable_11ac, bool, 0444);
|
||||
MODULE_PARM_DESC(disable_11ac, "Disable VHT capabilities (default: false)");
|
||||
|
||||
module_param_named(remove_when_gone,
|
||||
iwlwifi_mod_params.remove_when_gone, bool,
|
||||
0444);
|
||||
MODULE_PARM_DESC(remove_when_gone,
|
||||
"Remove dev from PCIe bus if it is deemed inaccessible (default: false)");
|
||||
|
|
|
@ -899,8 +899,8 @@ iwl_parse_eeprom_data(struct device *dev, const struct iwl_cfg *cfg,
|
|||
EEPROM_SKU_CAP);
|
||||
data->sku_cap_11n_enable = sku & EEPROM_SKU_CAP_11N_ENABLE;
|
||||
data->sku_cap_amt_enable = sku & EEPROM_SKU_CAP_AMT_ENABLE;
|
||||
data->sku_cap_band_24GHz_enable = sku & EEPROM_SKU_CAP_BAND_24GHZ;
|
||||
data->sku_cap_band_52GHz_enable = sku & EEPROM_SKU_CAP_BAND_52GHZ;
|
||||
data->sku_cap_band_24ghz_enable = sku & EEPROM_SKU_CAP_BAND_24GHZ;
|
||||
data->sku_cap_band_52ghz_enable = sku & EEPROM_SKU_CAP_BAND_52GHZ;
|
||||
data->sku_cap_ipan_enable = sku & EEPROM_SKU_CAP_IPAN_ENABLE;
|
||||
if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
|
||||
data->sku_cap_11n_enable = false;
|
||||
|
|
|
@ -81,10 +81,11 @@ struct iwl_nvm_data {
|
|||
__le16 kelvin_voltage;
|
||||
__le16 xtal_calib[2];
|
||||
|
||||
bool sku_cap_band_24GHz_enable;
|
||||
bool sku_cap_band_52GHz_enable;
|
||||
bool sku_cap_band_24ghz_enable;
|
||||
bool sku_cap_band_52ghz_enable;
|
||||
bool sku_cap_11n_enable;
|
||||
bool sku_cap_11ac_enable;
|
||||
bool sku_cap_11ax_enable;
|
||||
bool sku_cap_amt_enable;
|
||||
bool sku_cap_ipan_enable;
|
||||
bool sku_cap_mimo_disabled;
|
||||
|
|
|
@ -6,6 +6,7 @@
|
|||
* GPL LICENSE SUMMARY
|
||||
*
|
||||
* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
|
@ -31,6 +32,7 @@
|
|||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
@ -199,12 +201,12 @@ static int iwl_init_otp_access(struct iwl_trans *trans)
|
|||
/* Enable 40MHz radio clock */
|
||||
iwl_write32(trans, CSR_GP_CNTRL,
|
||||
iwl_read32(trans, CSR_GP_CNTRL) |
|
||||
CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
|
||||
BIT(trans->cfg->csr->flag_init_done));
|
||||
|
||||
/* wait for clock to be ready */
|
||||
ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
|
||||
CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
|
||||
CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
|
||||
BIT(trans->cfg->csr->flag_mac_clock_ready),
|
||||
BIT(trans->cfg->csr->flag_mac_clock_ready),
|
||||
25000);
|
||||
if (ret < 0) {
|
||||
IWL_ERR(trans, "Time out access OTP\n");
|
||||
|
|
|
@ -122,6 +122,7 @@ enum iwl_uapsd_disable {
|
|||
* @lar_disable: disable LAR (regulatory), default = 0
|
||||
* @fw_monitor: allow to use firmware monitor
|
||||
* @disable_11ac: disable VHT capabilities, default = false.
|
||||
* @remove_when_gone: remove an inaccessible device from the PCIe bus.
|
||||
*/
|
||||
struct iwl_mod_params {
|
||||
int swcrypto;
|
||||
|
@ -143,6 +144,7 @@ struct iwl_mod_params {
|
|||
bool lar_disable;
|
||||
bool fw_monitor;
|
||||
bool disable_11ac;
|
||||
bool remove_when_gone;
|
||||
};
|
||||
|
||||
#endif /* #__iwl_modparams_h__ */
|
||||
|
|
|
@ -8,6 +8,7 @@
|
|||
* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
|
@ -35,6 +36,7 @@
|
|||
* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
@ -68,6 +70,7 @@
|
|||
#include <linux/export.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/firmware.h>
|
||||
|
||||
#include "iwl-drv.h"
|
||||
#include "iwl-modparams.h"
|
||||
|
@ -77,6 +80,9 @@
|
|||
#include "iwl-csr.h"
|
||||
#include "fw/acpi.h"
|
||||
#include "fw/api/nvm-reg.h"
|
||||
#include "fw/api/commands.h"
|
||||
#include "fw/api/cmdhdr.h"
|
||||
#include "fw/img.h"
|
||||
|
||||
/* NVM offsets (in words) definitions */
|
||||
enum nvm_offsets {
|
||||
|
@ -292,7 +298,7 @@ static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, bool is_5ghz,
|
|||
static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
|
||||
struct iwl_nvm_data *data,
|
||||
const __le16 * const nvm_ch_flags,
|
||||
bool lar_supported, bool no_wide_in_5ghz)
|
||||
u32 sbands_flags)
|
||||
{
|
||||
int ch_idx;
|
||||
int n_channels = 0;
|
||||
|
@ -316,11 +322,12 @@ static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
|
|||
|
||||
ch_flags = __le16_to_cpup(nvm_ch_flags + ch_idx);
|
||||
|
||||
if (is_5ghz && !data->sku_cap_band_52GHz_enable)
|
||||
if (is_5ghz && !data->sku_cap_band_52ghz_enable)
|
||||
continue;
|
||||
|
||||
/* workaround to disable wide channels in 5GHz */
|
||||
if (no_wide_in_5ghz && is_5ghz) {
|
||||
if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) &&
|
||||
is_5ghz) {
|
||||
ch_flags &= ~(NVM_CHANNEL_40MHZ |
|
||||
NVM_CHANNEL_80MHZ |
|
||||
NVM_CHANNEL_160MHZ);
|
||||
|
@ -329,7 +336,8 @@ static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
|
|||
if (ch_flags & NVM_CHANNEL_160MHZ)
|
||||
data->vht160_supported = true;
|
||||
|
||||
if (!lar_supported && !(ch_flags & NVM_CHANNEL_VALID)) {
|
||||
if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) &&
|
||||
!(ch_flags & NVM_CHANNEL_VALID)) {
|
||||
/*
|
||||
* Channels might become valid later if lar is
|
||||
* supported, hence we still want to add them to
|
||||
|
@ -359,7 +367,7 @@ static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
|
|||
channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
|
||||
|
||||
/* don't put limitations in case we're using LAR */
|
||||
if (!lar_supported)
|
||||
if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR))
|
||||
channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx],
|
||||
ch_idx, is_5ghz,
|
||||
ch_flags, cfg);
|
||||
|
@ -455,17 +463,17 @@ static void iwl_init_vht_hw_capab(const struct iwl_cfg *cfg,
|
|||
vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
|
||||
}
|
||||
|
||||
void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg,
|
||||
struct iwl_nvm_data *data, const __le16 *nvm_ch_flags,
|
||||
u8 tx_chains, u8 rx_chains, bool lar_supported,
|
||||
bool no_wide_in_5ghz)
|
||||
static void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg,
|
||||
struct iwl_nvm_data *data,
|
||||
const __le16 *nvm_ch_flags, u8 tx_chains,
|
||||
u8 rx_chains, u32 sbands_flags)
|
||||
{
|
||||
int n_channels;
|
||||
int n_used = 0;
|
||||
struct ieee80211_supported_band *sband;
|
||||
|
||||
n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags,
|
||||
lar_supported, no_wide_in_5ghz);
|
||||
sbands_flags);
|
||||
sband = &data->bands[NL80211_BAND_2GHZ];
|
||||
sband->band = NL80211_BAND_2GHZ;
|
||||
sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
|
||||
|
@ -491,7 +499,6 @@ void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg,
|
|||
IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
|
||||
n_used, n_channels);
|
||||
}
|
||||
IWL_EXPORT_SYMBOL(iwl_init_sbands);
|
||||
|
||||
static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
|
||||
const __le16 *phy_sku)
|
||||
|
@ -569,11 +576,15 @@ static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest)
|
|||
dest[5] = hw_addr[0];
|
||||
}
|
||||
|
||||
void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
|
||||
struct iwl_nvm_data *data)
|
||||
static void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
|
||||
struct iwl_nvm_data *data)
|
||||
{
|
||||
__le32 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_STRAP));
|
||||
__le32 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_STRAP));
|
||||
__le32 mac_addr0 =
|
||||
cpu_to_le32(iwl_read32(trans,
|
||||
trans->cfg->csr->mac_addr0_strap));
|
||||
__le32 mac_addr1 =
|
||||
cpu_to_le32(iwl_read32(trans,
|
||||
trans->cfg->csr->mac_addr1_strap));
|
||||
|
||||
iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
|
||||
/*
|
||||
|
@ -583,12 +594,13 @@ void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
|
|||
if (is_valid_ether_addr(data->hw_addr))
|
||||
return;
|
||||
|
||||
mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP));
|
||||
mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP));
|
||||
mac_addr0 = cpu_to_le32(iwl_read32(trans,
|
||||
trans->cfg->csr->mac_addr0_otp));
|
||||
mac_addr1 = cpu_to_le32(iwl_read32(trans,
|
||||
trans->cfg->csr->mac_addr1_otp));
|
||||
|
||||
iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
|
||||
}
|
||||
IWL_EXPORT_SYMBOL(iwl_set_hw_address_from_csr);
|
||||
|
||||
static void iwl_set_hw_address_family_8000(struct iwl_trans *trans,
|
||||
const struct iwl_cfg *cfg,
|
||||
|
@ -713,8 +725,8 @@ iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
|
|||
struct device *dev = trans->dev;
|
||||
struct iwl_nvm_data *data;
|
||||
bool lar_enabled;
|
||||
bool no_wide_in_5ghz = iwl_nvm_no_wide_in_5ghz(dev, cfg, nvm_hw);
|
||||
u32 sku, radio_cfg;
|
||||
u32 sbands_flags = 0;
|
||||
u16 lar_config;
|
||||
const __le16 *ch_section;
|
||||
|
||||
|
@ -741,8 +753,8 @@ iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
|
|||
rx_chains &= data->valid_rx_ant;
|
||||
|
||||
sku = iwl_get_sku(cfg, nvm_sw, phy_sku);
|
||||
data->sku_cap_band_24GHz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
|
||||
data->sku_cap_band_52GHz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
|
||||
data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
|
||||
data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
|
||||
data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
|
||||
if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
|
||||
data->sku_cap_11n_enable = false;
|
||||
|
@ -787,8 +799,14 @@ iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
|
|||
return NULL;
|
||||
}
|
||||
|
||||
if (lar_fw_supported && lar_enabled)
|
||||
sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
|
||||
|
||||
if (iwl_nvm_no_wide_in_5ghz(dev, cfg, nvm_hw))
|
||||
sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ;
|
||||
|
||||
iwl_init_sbands(dev, cfg, data, ch_section, tx_chains, rx_chains,
|
||||
lar_fw_supported && lar_enabled, no_wide_in_5ghz);
|
||||
sbands_flags);
|
||||
data->calib_version = 255;
|
||||
|
||||
return data;
|
||||
|
@ -1017,3 +1035,294 @@ out:
|
|||
return copy_rd;
|
||||
}
|
||||
IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info);
|
||||
|
||||
#define IWL_MAX_NVM_SECTION_SIZE 0x1b58
|
||||
#define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc
|
||||
#define MAX_NVM_FILE_LEN 16384
|
||||
|
||||
void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data,
|
||||
unsigned int len)
|
||||
{
|
||||
#define IWL_4165_DEVICE_ID 0x5501
|
||||
#define NVM_SKU_CAP_MIMO_DISABLE BIT(5)
|
||||
|
||||
if (section == NVM_SECTION_TYPE_PHY_SKU &&
|
||||
hw_id == IWL_4165_DEVICE_ID && data && len >= 5 &&
|
||||
(data[4] & NVM_SKU_CAP_MIMO_DISABLE))
|
||||
/* OTP 0x52 bug work around: it's a 1x1 device */
|
||||
data[3] = ANT_B | (ANT_B << 4);
|
||||
}
|
||||
IWL_EXPORT_SYMBOL(iwl_nvm_fixups);
|
||||
|
||||
/*
|
||||
* Reads external NVM from a file into mvm->nvm_sections
|
||||
*
|
||||
* HOW TO CREATE THE NVM FILE FORMAT:
|
||||
* ------------------------------
|
||||
* 1. create hex file, format:
|
||||
* 3800 -> header
|
||||
* 0000 -> header
|
||||
* 5a40 -> data
|
||||
*
|
||||
* rev - 6 bit (word1)
|
||||
* len - 10 bit (word1)
|
||||
* id - 4 bit (word2)
|
||||
* rsv - 12 bit (word2)
|
||||
*
|
||||
* 2. flip 8bits with 8 bits per line to get the right NVM file format
|
||||
*
|
||||
* 3. create binary file from the hex file
|
||||
*
|
||||
* 4. save as "iNVM_xxx.bin" under /lib/firmware
|
||||
*/
|
||||
int iwl_read_external_nvm(struct iwl_trans *trans,
|
||||
const char *nvm_file_name,
|
||||
struct iwl_nvm_section *nvm_sections)
|
||||
{
|
||||
int ret, section_size;
|
||||
u16 section_id;
|
||||
const struct firmware *fw_entry;
|
||||
const struct {
|
||||
__le16 word1;
|
||||
__le16 word2;
|
||||
u8 data[];
|
||||
} *file_sec;
|
||||
const u8 *eof;
|
||||
u8 *temp;
|
||||
int max_section_size;
|
||||
const __le32 *dword_buff;
|
||||
|
||||
#define NVM_WORD1_LEN(x) (8 * (x & 0x03FF))
|
||||
#define NVM_WORD2_ID(x) (x >> 12)
|
||||
#define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8))
|
||||
#define EXT_NVM_WORD1_ID(x) ((x) >> 4)
|
||||
#define NVM_HEADER_0 (0x2A504C54)
|
||||
#define NVM_HEADER_1 (0x4E564D2A)
|
||||
#define NVM_HEADER_SIZE (4 * sizeof(u32))
|
||||
|
||||
IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n");
|
||||
|
||||
/* Maximal size depends on NVM version */
|
||||
if (trans->cfg->nvm_type != IWL_NVM_EXT)
|
||||
max_section_size = IWL_MAX_NVM_SECTION_SIZE;
|
||||
else
|
||||
max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE;
|
||||
|
||||
/*
|
||||
* Obtain NVM image via request_firmware. Since we already used
|
||||
* request_firmware_nowait() for the firmware binary load and only
|
||||
* get here after that we assume the NVM request can be satisfied
|
||||
* synchronously.
|
||||
*/
|
||||
ret = request_firmware(&fw_entry, nvm_file_name, trans->dev);
|
||||
if (ret) {
|
||||
IWL_ERR(trans, "ERROR: %s isn't available %d\n",
|
||||
nvm_file_name, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n",
|
||||
nvm_file_name, fw_entry->size);
|
||||
|
||||
if (fw_entry->size > MAX_NVM_FILE_LEN) {
|
||||
IWL_ERR(trans, "NVM file too large\n");
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
eof = fw_entry->data + fw_entry->size;
|
||||
dword_buff = (__le32 *)fw_entry->data;
|
||||
|
||||
/* some NVM file will contain a header.
|
||||
* The header is identified by 2 dwords header as follow:
|
||||
* dword[0] = 0x2A504C54
|
||||
* dword[1] = 0x4E564D2A
|
||||
*
|
||||
* This header must be skipped when providing the NVM data to the FW.
|
||||
*/
|
||||
if (fw_entry->size > NVM_HEADER_SIZE &&
|
||||
dword_buff[0] == cpu_to_le32(NVM_HEADER_0) &&
|
||||
dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) {
|
||||
file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE);
|
||||
IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2]));
|
||||
IWL_INFO(trans, "NVM Manufacturing date %08X\n",
|
||||
le32_to_cpu(dword_buff[3]));
|
||||
|
||||
/* nvm file validation, dword_buff[2] holds the file version */
|
||||
if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
|
||||
CSR_HW_REV_STEP(trans->hw_rev) == SILICON_C_STEP &&
|
||||
le32_to_cpu(dword_buff[2]) < 0xE4A) {
|
||||
ret = -EFAULT;
|
||||
goto out;
|
||||
}
|
||||
} else {
|
||||
file_sec = (void *)fw_entry->data;
|
||||
}
|
||||
|
||||
while (true) {
|
||||
if (file_sec->data > eof) {
|
||||
IWL_ERR(trans,
|
||||
"ERROR - NVM file too short for section header\n");
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
/* check for EOF marker */
|
||||
if (!file_sec->word1 && !file_sec->word2) {
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
if (trans->cfg->nvm_type != IWL_NVM_EXT) {
|
||||
section_size =
|
||||
2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1));
|
||||
section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2));
|
||||
} else {
|
||||
section_size = 2 * EXT_NVM_WORD2_LEN(
|
||||
le16_to_cpu(file_sec->word2));
|
||||
section_id = EXT_NVM_WORD1_ID(
|
||||
le16_to_cpu(file_sec->word1));
|
||||
}
|
||||
|
||||
if (section_size > max_section_size) {
|
||||
IWL_ERR(trans, "ERROR - section too large (%d)\n",
|
||||
section_size);
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
if (!section_size) {
|
||||
IWL_ERR(trans, "ERROR - section empty\n");
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
if (file_sec->data + section_size > eof) {
|
||||
IWL_ERR(trans,
|
||||
"ERROR - NVM file too short for section (%d bytes)\n",
|
||||
section_size);
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
if (WARN(section_id >= NVM_MAX_NUM_SECTIONS,
|
||||
"Invalid NVM section ID %d\n", section_id)) {
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
temp = kmemdup(file_sec->data, section_size, GFP_KERNEL);
|
||||
if (!temp) {
|
||||
ret = -ENOMEM;
|
||||
break;
|
||||
}
|
||||
|
||||
iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size);
|
||||
|
||||
kfree(nvm_sections[section_id].data);
|
||||
nvm_sections[section_id].data = temp;
|
||||
nvm_sections[section_id].length = section_size;
|
||||
|
||||
/* advance to the next section */
|
||||
file_sec = (void *)(file_sec->data + section_size);
|
||||
}
|
||||
out:
|
||||
release_firmware(fw_entry);
|
||||
return ret;
|
||||
}
|
||||
IWL_EXPORT_SYMBOL(iwl_read_external_nvm);
|
||||
|
||||
struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans,
|
||||
const struct iwl_fw *fw)
|
||||
{
|
||||
struct iwl_nvm_get_info cmd = {};
|
||||
struct iwl_nvm_get_info_rsp *rsp;
|
||||
struct iwl_nvm_data *nvm;
|
||||
struct iwl_host_cmd hcmd = {
|
||||
.flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
|
||||
.data = { &cmd, },
|
||||
.len = { sizeof(cmd) },
|
||||
.id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO)
|
||||
};
|
||||
int ret;
|
||||
bool lar_fw_supported = !iwlwifi_mod_params.lar_disable &&
|
||||
fw_has_capa(&fw->ucode_capa,
|
||||
IWL_UCODE_TLV_CAPA_LAR_SUPPORT);
|
||||
u32 mac_flags;
|
||||
u32 sbands_flags = 0;
|
||||
|
||||
ret = iwl_trans_send_cmd(trans, &hcmd);
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != sizeof(*rsp),
|
||||
"Invalid payload len in NVM response from FW %d",
|
||||
iwl_rx_packet_payload_len(hcmd.resp_pkt))) {
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
rsp = (void *)hcmd.resp_pkt->data;
|
||||
if (le32_to_cpu(rsp->general.flags) & NVM_GENERAL_FLAGS_EMPTY_OTP)
|
||||
IWL_INFO(trans, "OTP is empty\n");
|
||||
|
||||
nvm = kzalloc(sizeof(*nvm) +
|
||||
sizeof(struct ieee80211_channel) * IWL_NUM_CHANNELS,
|
||||
GFP_KERNEL);
|
||||
if (!nvm) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
iwl_set_hw_address_from_csr(trans, nvm);
|
||||
/* TODO: if platform NVM has MAC address - override it here */
|
||||
|
||||
if (!is_valid_ether_addr(nvm->hw_addr)) {
|
||||
IWL_ERR(trans, "no valid mac address was found\n");
|
||||
ret = -EINVAL;
|
||||
goto err_free;
|
||||
}
|
||||
|
||||
IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr);
|
||||
|
||||
/* Initialize general data */
|
||||
nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version);
|
||||
|
||||
/* Initialize MAC sku data */
|
||||
mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags);
|
||||
nvm->sku_cap_11ac_enable =
|
||||
!!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED);
|
||||
nvm->sku_cap_11n_enable =
|
||||
!!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED);
|
||||
nvm->sku_cap_band_24ghz_enable =
|
||||
!!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED);
|
||||
nvm->sku_cap_band_52ghz_enable =
|
||||
!!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED);
|
||||
nvm->sku_cap_mimo_disabled =
|
||||
!!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED);
|
||||
|
||||
/* Initialize PHY sku data */
|
||||
nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains);
|
||||
nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains);
|
||||
|
||||
if (le32_to_cpu(rsp->regulatory.lar_enabled) && lar_fw_supported) {
|
||||
nvm->lar_enabled = true;
|
||||
sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
|
||||
}
|
||||
|
||||
iwl_init_sbands(trans->dev, trans->cfg, nvm,
|
||||
rsp->regulatory.channel_profile,
|
||||
nvm->valid_tx_ant & fw->valid_tx_ant,
|
||||
nvm->valid_rx_ant & fw->valid_rx_ant,
|
||||
sbands_flags);
|
||||
|
||||
iwl_free_resp(&hcmd);
|
||||
return nvm;
|
||||
|
||||
err_free:
|
||||
kfree(nvm);
|
||||
out:
|
||||
iwl_free_resp(&hcmd);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
IWL_EXPORT_SYMBOL(iwl_get_nvm);
|
||||
|
|
|
@ -7,6 +7,7 @@
|
|||
*
|
||||
* Copyright(c) 2008 - 2015 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
|
@ -33,6 +34,7 @@
|
|||
*
|
||||
* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
@ -67,6 +69,17 @@
|
|||
#include <net/cfg80211.h>
|
||||
#include "iwl-eeprom-parse.h"
|
||||
|
||||
/**
|
||||
* enum iwl_nvm_sbands_flags - modification flags for the channel profiles
|
||||
*
|
||||
* @IWL_NVM_SBANDS_FLAGS_LAR: LAR is enabled
|
||||
* @IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ: disallow 40, 80 and 160MHz on 5GHz
|
||||
*/
|
||||
enum iwl_nvm_sbands_flags {
|
||||
IWL_NVM_SBANDS_FLAGS_LAR = BIT(0),
|
||||
IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ = BIT(1),
|
||||
};
|
||||
|
||||
/**
|
||||
* iwl_parse_nvm_data - parse NVM data and return values
|
||||
*
|
||||
|
@ -82,20 +95,6 @@ iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
|
|||
const __le16 *mac_override, const __le16 *phy_sku,
|
||||
u8 tx_chains, u8 rx_chains, bool lar_fw_supported);
|
||||
|
||||
/**
|
||||
* iwl_set_hw_address_from_csr - sets HW address for 9000 devices and on
|
||||
*/
|
||||
void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
|
||||
struct iwl_nvm_data *data);
|
||||
|
||||
/**
|
||||
* iwl_init_sbands - parse and set all channel profiles
|
||||
*/
|
||||
void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg,
|
||||
struct iwl_nvm_data *data, const __le16 *nvm_ch_flags,
|
||||
u8 tx_chains, u8 rx_chains, bool lar_supported,
|
||||
bool no_wide_in_5ghz);
|
||||
|
||||
/**
|
||||
* iwl_parse_mcc_info - parse MCC (mobile country code) info coming from FW
|
||||
*
|
||||
|
@ -111,4 +110,33 @@ iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg,
|
|||
int num_of_ch, __le32 *channels, u16 fw_mcc,
|
||||
u16 geo_info);
|
||||
|
||||
/**
|
||||
* struct iwl_nvm_section - describes an NVM section in memory.
|
||||
*
|
||||
* This struct holds an NVM section read from the NIC using NVM_ACCESS_CMD,
|
||||
* and saved for later use by the driver. Not all NVM sections are saved
|
||||
* this way, only the needed ones.
|
||||
*/
|
||||
struct iwl_nvm_section {
|
||||
u16 length;
|
||||
const u8 *data;
|
||||
};
|
||||
|
||||
/**
|
||||
* iwl_read_external_nvm - Reads external NVM from a file into nvm_sections
|
||||
*/
|
||||
int iwl_read_external_nvm(struct iwl_trans *trans,
|
||||
const char *nvm_file_name,
|
||||
struct iwl_nvm_section *nvm_sections);
|
||||
void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data,
|
||||
unsigned int len);
|
||||
|
||||
/**
|
||||
* iwl_get_nvm - retrieve NVM data from firmware
|
||||
*
|
||||
* Allocates a new iwl_nvm_data structure, fills it with
|
||||
* NVM data, and returns it to caller.
|
||||
*/
|
||||
struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans,
|
||||
const struct iwl_fw *fw);
|
||||
#endif /* __iwl_nvm_parse_h__ */
|
||||
|
|
|
@ -554,7 +554,7 @@ struct iwl_trans_ops {
|
|||
/* 22000 functions */
|
||||
int (*txq_alloc)(struct iwl_trans *trans,
|
||||
struct iwl_tx_queue_cfg_cmd *cmd,
|
||||
int cmd_id,
|
||||
int cmd_id, int size,
|
||||
unsigned int queue_wdg_timeout);
|
||||
void (*txq_free)(struct iwl_trans *trans, int queue);
|
||||
|
||||
|
@ -691,6 +691,8 @@ enum iwl_plat_pm_mode {
|
|||
* @wide_cmd_header: true when ucode supports wide command header format
|
||||
* @num_rx_queues: number of RX queues allocated by the transport;
|
||||
* the transport must set this before calling iwl_drv_start()
|
||||
* @iml_len: the length of the image loader
|
||||
* @iml: a pointer to the image loader itself
|
||||
* @dev_cmd_pool: pool for Tx cmd allocation - for internal use only.
|
||||
* The user should use iwl_trans_{alloc,free}_tx_cmd.
|
||||
* @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before
|
||||
|
@ -735,6 +737,9 @@ struct iwl_trans {
|
|||
|
||||
u8 num_rx_queues;
|
||||
|
||||
size_t iml_len;
|
||||
u8 *iml;
|
||||
|
||||
/* The following fields are internal only */
|
||||
struct kmem_cache *dev_cmd_pool;
|
||||
char dev_cmd_pool_name[50];
|
||||
|
@ -952,8 +957,8 @@ iwl_trans_txq_free(struct iwl_trans *trans, int queue)
|
|||
static inline int
|
||||
iwl_trans_txq_alloc(struct iwl_trans *trans,
|
||||
struct iwl_tx_queue_cfg_cmd *cmd,
|
||||
int cmd_id,
|
||||
unsigned int queue_wdg_timeout)
|
||||
int cmd_id, int size,
|
||||
unsigned int wdg_timeout)
|
||||
{
|
||||
might_sleep();
|
||||
|
||||
|
@ -965,7 +970,7 @@ iwl_trans_txq_alloc(struct iwl_trans *trans,
|
|||
return -EIO;
|
||||
}
|
||||
|
||||
return trans->ops->txq_alloc(trans, cmd, cmd_id, queue_wdg_timeout);
|
||||
return trans->ops->txq_alloc(trans, cmd, cmd_id, size, wdg_timeout);
|
||||
}
|
||||
|
||||
static inline void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans,
|
||||
|
|
|
@ -279,6 +279,8 @@ struct iwl_bt_iterator_data {
|
|||
struct ieee80211_chanctx_conf *primary;
|
||||
struct ieee80211_chanctx_conf *secondary;
|
||||
bool primary_ll;
|
||||
u8 primary_load;
|
||||
u8 secondary_load;
|
||||
};
|
||||
|
||||
static inline
|
||||
|
@ -295,6 +297,30 @@ void iwl_mvm_bt_coex_enable_rssi_event(struct iwl_mvm *mvm,
|
|||
enable ? -IWL_MVM_BT_COEX_DIS_RED_TXP_THRESH : 0;
|
||||
}
|
||||
|
||||
#define MVM_COEX_TCM_PERIOD (HZ * 10)
|
||||
|
||||
static void iwl_mvm_bt_coex_tcm_based_ci(struct iwl_mvm *mvm,
|
||||
struct iwl_bt_iterator_data *data)
|
||||
{
|
||||
unsigned long now = jiffies;
|
||||
|
||||
if (!time_after(now, mvm->bt_coex_last_tcm_ts + MVM_COEX_TCM_PERIOD))
|
||||
return;
|
||||
|
||||
mvm->bt_coex_last_tcm_ts = now;
|
||||
|
||||
/* We assume here that we don't have more than 2 vifs on 2.4GHz */
|
||||
|
||||
/* if the primary is low latency, it will stay primary */
|
||||
if (data->primary_ll)
|
||||
return;
|
||||
|
||||
if (data->primary_load >= data->secondary_load)
|
||||
return;
|
||||
|
||||
swap(data->primary, data->secondary);
|
||||
}
|
||||
|
||||
/* must be called under rcu_read_lock */
|
||||
static void iwl_mvm_bt_notif_iterator(void *_data, u8 *mac,
|
||||
struct ieee80211_vif *vif)
|
||||
|
@ -385,6 +411,11 @@ static void iwl_mvm_bt_notif_iterator(void *_data, u8 *mac,
|
|||
/* there is low latency vif - we will be secondary */
|
||||
data->secondary = chanctx_conf;
|
||||
}
|
||||
|
||||
if (data->primary == chanctx_conf)
|
||||
data->primary_load = mvm->tcm.result.load[mvmvif->id];
|
||||
else if (data->secondary == chanctx_conf)
|
||||
data->secondary_load = mvm->tcm.result.load[mvmvif->id];
|
||||
return;
|
||||
}
|
||||
|
||||
|
@ -398,6 +429,10 @@ static void iwl_mvm_bt_notif_iterator(void *_data, u8 *mac,
|
|||
/* if secondary is not NULL, it might be a GO */
|
||||
data->secondary = chanctx_conf;
|
||||
|
||||
if (data->primary == chanctx_conf)
|
||||
data->primary_load = mvm->tcm.result.load[mvmvif->id];
|
||||
else if (data->secondary == chanctx_conf)
|
||||
data->secondary_load = mvm->tcm.result.load[mvmvif->id];
|
||||
/*
|
||||
* don't reduce the Tx power if one of these is true:
|
||||
* we are in LOOSE
|
||||
|
@ -449,6 +484,8 @@ static void iwl_mvm_bt_coex_notif_handle(struct iwl_mvm *mvm)
|
|||
mvm->hw, IEEE80211_IFACE_ITER_NORMAL,
|
||||
iwl_mvm_bt_notif_iterator, &data);
|
||||
|
||||
iwl_mvm_bt_coex_tcm_based_ci(mvm, &data);
|
||||
|
||||
if (data.primary) {
|
||||
struct ieee80211_chanctx_conf *chan = data.primary;
|
||||
if (WARN_ON(!chan->def.chan)) {
|
||||
|
|
|
@ -69,6 +69,8 @@
|
|||
|
||||
#include <linux/ieee80211.h>
|
||||
|
||||
#define IWL_MVM_UAPSD_NOAGG_BSSIDS_NUM 20
|
||||
|
||||
#define IWL_MVM_DEFAULT_PS_TX_DATA_TIMEOUT (100 * USEC_PER_MSEC)
|
||||
#define IWL_MVM_DEFAULT_PS_RX_DATA_TIMEOUT (100 * USEC_PER_MSEC)
|
||||
#define IWL_MVM_WOWLAN_PS_TX_DATA_TIMEOUT (10 * USEC_PER_MSEC)
|
||||
|
@ -112,6 +114,11 @@
|
|||
#define IWL_MVM_PARSE_NVM 0
|
||||
#define IWL_MVM_ADWELL_ENABLE 1
|
||||
#define IWL_MVM_ADWELL_MAX_BUDGET 0
|
||||
#define IWL_MVM_TCM_LOAD_MEDIUM_THRESH 10 /* percentage */
|
||||
#define IWL_MVM_TCM_LOAD_HIGH_THRESH 50 /* percentage */
|
||||
#define IWL_MVM_TCM_LOWLAT_ENABLE_THRESH 100 /* packets/10 seconds */
|
||||
#define IWL_MVM_UAPSD_NONAGG_PERIOD 5000 /* msecs */
|
||||
#define IWL_MVM_UAPSD_NOAGG_LIST_LEN IWL_MVM_UAPSD_NOAGG_BSSIDS_NUM
|
||||
#define IWL_MVM_RS_NUM_TRY_BEFORE_ANT_TOGGLE 1
|
||||
#define IWL_MVM_RS_HT_VHT_RETRIES_PER_RATE 2
|
||||
#define IWL_MVM_RS_HT_VHT_RETRIES_PER_RATE_TW 1
|
||||
|
|
|
@ -8,6 +8,7 @@
|
|||
* Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
|
@ -18,11 +19,6 @@
|
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
|
||||
* USA
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called COPYING.
|
||||
*
|
||||
|
@ -35,6 +31,7 @@
|
|||
* Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
@ -693,6 +690,14 @@ iwl_mvm_get_wowlan_config(struct iwl_mvm *mvm,
|
|||
IWL_WOWLAN_WAKEUP_LINK_CHANGE);
|
||||
}
|
||||
|
||||
if (wowlan->any) {
|
||||
wowlan_config_cmd->wakeup_filter |=
|
||||
cpu_to_le32(IWL_WOWLAN_WAKEUP_BEACON_MISS |
|
||||
IWL_WOWLAN_WAKEUP_LINK_CHANGE |
|
||||
IWL_WOWLAN_WAKEUP_RX_FRAME |
|
||||
IWL_WOWLAN_WAKEUP_BCN_FILTERING);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -1097,6 +1102,7 @@ int iwl_mvm_suspend(struct ieee80211_hw *hw, struct cfg80211_wowlan *wowlan)
|
|||
|
||||
/* make sure the d0i3 exit work is not pending */
|
||||
flush_work(&mvm->d0i3_exit_work);
|
||||
iwl_mvm_pause_tcm(mvm, true);
|
||||
|
||||
iwl_fw_runtime_suspend(&mvm->fwrt);
|
||||
|
||||
|
@ -2014,6 +2020,8 @@ int iwl_mvm_resume(struct ieee80211_hw *hw)
|
|||
|
||||
mvm->trans->system_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
|
||||
|
||||
iwl_mvm_resume_tcm(mvm);
|
||||
|
||||
iwl_fw_runtime_resume(&mvm->fwrt);
|
||||
|
||||
return ret;
|
||||
|
@ -2042,6 +2050,8 @@ static int iwl_mvm_d3_test_open(struct inode *inode, struct file *file)
|
|||
|
||||
mvm->trans->system_pm_mode = IWL_PLAT_PM_MODE_D3;
|
||||
|
||||
iwl_mvm_pause_tcm(mvm, true);
|
||||
|
||||
iwl_fw_runtime_suspend(&mvm->fwrt);
|
||||
|
||||
/* start pseudo D3 */
|
||||
|
@ -2104,6 +2114,8 @@ static int iwl_mvm_d3_test_release(struct inode *inode, struct file *file)
|
|||
__iwl_mvm_resume(mvm, true);
|
||||
rtnl_unlock();
|
||||
|
||||
iwl_mvm_resume_tcm(mvm);
|
||||
|
||||
iwl_fw_runtime_resume(&mvm->fwrt);
|
||||
|
||||
mvm->trans->system_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
|
||||
|
|
|
@ -269,6 +269,8 @@ static ssize_t iwl_dbgfs_mac_params_read(struct file *file,
|
|||
mvmvif->id, mvmvif->color);
|
||||
pos += scnprintf(buf+pos, bufsz-pos, "bssid: %pM\n",
|
||||
vif->bss_conf.bssid);
|
||||
pos += scnprintf(buf+pos, bufsz-pos, "Load: %d\n",
|
||||
mvm->tcm.result.load[mvmvif->id]);
|
||||
pos += scnprintf(buf+pos, bufsz-pos, "QoS:\n");
|
||||
for (i = 0; i < ARRAY_SIZE(mvmvif->queue_params); i++)
|
||||
pos += scnprintf(buf+pos, bufsz-pos,
|
||||
|
|
|
@ -1728,6 +1728,27 @@ iwl_dbgfs_send_echo_cmd_write(struct iwl_mvm *mvm, char *buf,
|
|||
return ret ?: count;
|
||||
}
|
||||
|
||||
static ssize_t
|
||||
iwl_dbgfs_uapsd_noagg_bssids_read(struct file *file, char __user *user_buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct iwl_mvm *mvm = file->private_data;
|
||||
u8 buf[IWL_MVM_UAPSD_NOAGG_BSSIDS_NUM * ETH_ALEN * 3 + 1];
|
||||
unsigned int pos = 0;
|
||||
size_t bufsz = sizeof(buf);
|
||||
int i;
|
||||
|
||||
mutex_lock(&mvm->mutex);
|
||||
|
||||
for (i = 0; i < IWL_MVM_UAPSD_NOAGG_LIST_LEN; i++)
|
||||
pos += scnprintf(buf + pos, bufsz - pos, "%pM\n",
|
||||
mvm->uapsd_noagg_bssids[i].addr);
|
||||
|
||||
mutex_unlock(&mvm->mutex);
|
||||
|
||||
return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
|
||||
}
|
||||
|
||||
MVM_DEBUGFS_READ_WRITE_FILE_OPS(prph_reg, 64);
|
||||
|
||||
/* Device wide debugfs entries */
|
||||
|
@ -1762,6 +1783,8 @@ MVM_DEBUGFS_WRITE_FILE_OPS(indirection_tbl,
|
|||
(IWL_RSS_INDIRECTION_TABLE_SIZE * 2));
|
||||
MVM_DEBUGFS_WRITE_FILE_OPS(inject_packet, 512);
|
||||
|
||||
MVM_DEBUGFS_READ_FILE_OPS(uapsd_noagg_bssids);
|
||||
|
||||
#ifdef CONFIG_IWLWIFI_BCAST_FILTERING
|
||||
MVM_DEBUGFS_READ_WRITE_FILE_OPS(bcast_filters, 256);
|
||||
MVM_DEBUGFS_READ_WRITE_FILE_OPS(bcast_filters_macs, 256);
|
||||
|
@ -1972,6 +1995,8 @@ int iwl_mvm_dbgfs_register(struct iwl_mvm *mvm, struct dentry *dbgfs_dir)
|
|||
mvm->debugfs_dir, &mvm->drop_bcn_ap_mode))
|
||||
goto err;
|
||||
|
||||
MVM_DEBUGFS_ADD_FILE(uapsd_noagg_bssids, mvm->debugfs_dir, S_IRUSR);
|
||||
|
||||
#ifdef CONFIG_IWLWIFI_BCAST_FILTERING
|
||||
if (mvm->fw->ucode_capa.flags & IWL_UCODE_TLV_FLAGS_BCAST_FILTERING) {
|
||||
bcast_dir = debugfs_create_dir("bcast_filtering",
|
||||
|
|
|
@ -8,6 +8,7 @@
|
|||
* Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
|
@ -35,6 +36,7 @@
|
|||
* Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
@ -79,6 +81,8 @@
|
|||
#include "mvm.h"
|
||||
#include "fw/dbg.h"
|
||||
#include "iwl-phy-db.h"
|
||||
#include "iwl-modparams.h"
|
||||
#include "iwl-nvm-parse.h"
|
||||
|
||||
#define MVM_UCODE_ALIVE_TIMEOUT HZ
|
||||
#define MVM_UCODE_CALIB_TIMEOUT (2*HZ)
|
||||
|
@ -381,7 +385,8 @@ static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm)
|
|||
|
||||
/* Load NVM to NIC if needed */
|
||||
if (mvm->nvm_file_name) {
|
||||
iwl_mvm_read_external_nvm(mvm);
|
||||
iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name,
|
||||
mvm->nvm_sections);
|
||||
iwl_mvm_load_nvm_to_nic(mvm);
|
||||
}
|
||||
|
||||
|
@ -410,7 +415,7 @@ static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm)
|
|||
|
||||
/* Read the NVM only at driver load time, no need to do this twice */
|
||||
if (!IWL_MVM_PARSE_NVM && read_nvm) {
|
||||
mvm->nvm_data = iwl_fw_get_nvm(&mvm->fwrt);
|
||||
mvm->nvm_data = iwl_get_nvm(mvm->trans, mvm->fw);
|
||||
if (IS_ERR(mvm->nvm_data)) {
|
||||
ret = PTR_ERR(mvm->nvm_data);
|
||||
mvm->nvm_data = NULL;
|
||||
|
@ -1093,6 +1098,7 @@ int iwl_mvm_up(struct iwl_mvm *mvm)
|
|||
|
||||
if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) {
|
||||
mvm->scan_type = IWL_SCAN_TYPE_NOT_SET;
|
||||
mvm->hb_scan_type = IWL_SCAN_TYPE_NOT_SET;
|
||||
ret = iwl_mvm_config_scan(mvm);
|
||||
if (ret)
|
||||
goto error;
|
||||
|
|
|
@ -953,6 +953,16 @@ static int iwl_mvm_mac_ampdu_action(struct ieee80211_hw *hw,
|
|||
|
||||
switch (action) {
|
||||
case IEEE80211_AMPDU_RX_START:
|
||||
if (iwl_mvm_vif_from_mac80211(vif)->ap_sta_id ==
|
||||
iwl_mvm_sta_from_mac80211(sta)->sta_id) {
|
||||
struct iwl_mvm_vif *mvmvif;
|
||||
u16 macid = iwl_mvm_vif_from_mac80211(vif)->id;
|
||||
struct iwl_mvm_tcm_mac *mdata = &mvm->tcm.data[macid];
|
||||
|
||||
mdata->opened_rx_ba_sessions = true;
|
||||
mvmvif = iwl_mvm_vif_from_mac80211(vif);
|
||||
cancel_delayed_work(&mvmvif->uapsd_nonagg_detected_wk);
|
||||
}
|
||||
if (!iwl_enable_rx_ampdu(mvm->cfg)) {
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
|
@ -1436,6 +1446,8 @@ static int iwl_mvm_mac_add_interface(struct ieee80211_hw *hw,
|
|||
mvm->p2p_device_vif = vif;
|
||||
}
|
||||
|
||||
iwl_mvm_tcm_add_vif(mvm, vif);
|
||||
|
||||
if (vif->type == NL80211_IFTYPE_MONITOR)
|
||||
mvm->monitor_on = true;
|
||||
|
||||
|
@ -1487,6 +1499,10 @@ static void iwl_mvm_mac_remove_interface(struct ieee80211_hw *hw,
|
|||
|
||||
iwl_mvm_prepare_mac_removal(mvm, vif);
|
||||
|
||||
if (!(vif->type == NL80211_IFTYPE_AP ||
|
||||
vif->type == NL80211_IFTYPE_ADHOC))
|
||||
iwl_mvm_tcm_rm_vif(mvm, vif);
|
||||
|
||||
mutex_lock(&mvm->mutex);
|
||||
|
||||
if (mvm->bf_allowed_vif == mvmvif) {
|
||||
|
@ -2536,6 +2552,16 @@ static void iwl_mvm_sta_pre_rcu_remove(struct ieee80211_hw *hw,
|
|||
static void iwl_mvm_check_uapsd(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
|
||||
const u8 *bssid)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (!test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) {
|
||||
struct iwl_mvm_tcm_mac *mdata;
|
||||
|
||||
mdata = &mvm->tcm.data[iwl_mvm_vif_from_mac80211(vif)->id];
|
||||
ewma_rate_init(&mdata->uapsd_nonagg_detect.rate);
|
||||
mdata->opened_rx_ba_sessions = false;
|
||||
}
|
||||
|
||||
if (!(mvm->fw->ucode_capa.flags & IWL_UCODE_TLV_FLAGS_UAPSD_SUPPORT))
|
||||
return;
|
||||
|
||||
|
@ -2550,6 +2576,13 @@ static void iwl_mvm_check_uapsd(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
|
|||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < IWL_MVM_UAPSD_NOAGG_LIST_LEN; i++) {
|
||||
if (ether_addr_equal(mvm->uapsd_noagg_bssids[i].addr, bssid)) {
|
||||
vif->driver_flags &= ~IEEE80211_VIF_SUPPORTS_UAPSD;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
vif->driver_flags |= IEEE80211_VIF_SUPPORTS_UAPSD;
|
||||
}
|
||||
|
||||
|
|
|
@ -8,6 +8,7 @@
|
|||
* Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
|
@ -35,6 +36,7 @@
|
|||
* Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
@ -90,7 +92,9 @@
|
|||
#include "fw/runtime.h"
|
||||
#include "fw/dbg.h"
|
||||
#include "fw/acpi.h"
|
||||
#include "fw/debugfs.h"
|
||||
#include "iwl-nvm-parse.h"
|
||||
|
||||
#include <linux/average.h>
|
||||
|
||||
#define IWL_MVM_MAX_ADDRESSES 5
|
||||
/* RSSI offset for WkP */
|
||||
|
@ -444,6 +448,8 @@ struct iwl_mvm_vif {
|
|||
/* FW identified misbehaving AP */
|
||||
u8 uapsd_misbehaving_bssid[ETH_ALEN];
|
||||
|
||||
struct delayed_work uapsd_nonagg_detected_wk;
|
||||
|
||||
/* Indicates that CSA countdown may be started */
|
||||
bool csa_countdown;
|
||||
bool csa_failed;
|
||||
|
@ -502,18 +508,6 @@ enum iwl_mvm_sched_scan_pass_all_states {
|
|||
SCHED_SCAN_PASS_ALL_FOUND,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct iwl_nvm_section - describes an NVM section in memory.
|
||||
*
|
||||
* This struct holds an NVM section read from the NIC using NVM_ACCESS_CMD,
|
||||
* and saved for later use by the driver. Not all NVM sections are saved
|
||||
* this way, only the needed ones.
|
||||
*/
|
||||
struct iwl_nvm_section {
|
||||
u16 length;
|
||||
const u8 *data;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct iwl_mvm_tt_mgnt - Thermal Throttling Management structure
|
||||
* @ct_kill_exit: worker to exit thermal kill
|
||||
|
@ -595,6 +589,53 @@ enum iwl_mvm_tdls_cs_state {
|
|||
IWL_MVM_TDLS_SW_ACTIVE,
|
||||
};
|
||||
|
||||
enum iwl_mvm_traffic_load {
|
||||
IWL_MVM_TRAFFIC_LOW,
|
||||
IWL_MVM_TRAFFIC_MEDIUM,
|
||||
IWL_MVM_TRAFFIC_HIGH,
|
||||
};
|
||||
|
||||
DECLARE_EWMA(rate, 16, 16)
|
||||
|
||||
struct iwl_mvm_tcm_mac {
|
||||
struct {
|
||||
u32 pkts[IEEE80211_NUM_ACS];
|
||||
u32 airtime;
|
||||
} tx;
|
||||
struct {
|
||||
u32 pkts[IEEE80211_NUM_ACS];
|
||||
u32 airtime;
|
||||
u32 last_ampdu_ref;
|
||||
} rx;
|
||||
struct {
|
||||
/* track AP's transfer in client mode */
|
||||
u64 rx_bytes;
|
||||
struct ewma_rate rate;
|
||||
bool detected;
|
||||
} uapsd_nonagg_detect;
|
||||
bool opened_rx_ba_sessions;
|
||||
};
|
||||
|
||||
struct iwl_mvm_tcm {
|
||||
struct delayed_work work;
|
||||
spinlock_t lock; /* used when time elapsed */
|
||||
unsigned long ts; /* timestamp when period ends */
|
||||
unsigned long ll_ts;
|
||||
unsigned long uapsd_nonagg_ts;
|
||||
bool paused;
|
||||
struct iwl_mvm_tcm_mac data[NUM_MAC_INDEX_DRIVER];
|
||||
struct {
|
||||
u32 elapsed; /* milliseconds for this TCM period */
|
||||
u32 airtime[NUM_MAC_INDEX_DRIVER];
|
||||
enum iwl_mvm_traffic_load load[NUM_MAC_INDEX_DRIVER];
|
||||
enum iwl_mvm_traffic_load band_load[NUM_NL80211_BANDS];
|
||||
enum iwl_mvm_traffic_load global_load;
|
||||
bool low_latency[NUM_MAC_INDEX_DRIVER];
|
||||
bool change[NUM_MAC_INDEX_DRIVER];
|
||||
bool global_change;
|
||||
} result;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct iwl_mvm_reorder_buffer - per ra/tid/queue reorder buffer
|
||||
* @head_sn: reorder window head sn
|
||||
|
@ -829,7 +870,10 @@ struct iwl_mvm {
|
|||
unsigned int scan_status;
|
||||
void *scan_cmd;
|
||||
struct iwl_mcast_filter_cmd *mcast_filter_cmd;
|
||||
/* For CDB this is low band scan type, for non-CDB - type. */
|
||||
enum iwl_mvm_scan_type scan_type;
|
||||
enum iwl_mvm_scan_type hb_scan_type;
|
||||
|
||||
enum iwl_mvm_sched_scan_pass_all_states sched_scan_pass_all;
|
||||
struct delayed_work scan_timeout_dwork;
|
||||
|
||||
|
@ -978,6 +1022,13 @@ struct iwl_mvm {
|
|||
*/
|
||||
bool temperature_test; /* Debug test temperature is enabled */
|
||||
|
||||
unsigned long bt_coex_last_tcm_ts;
|
||||
struct iwl_mvm_tcm tcm;
|
||||
|
||||
u8 uapsd_noagg_bssid_write_idx;
|
||||
struct mac_address uapsd_noagg_bssids[IWL_MVM_UAPSD_NOAGG_BSSIDS_NUM]
|
||||
__aligned(2);
|
||||
|
||||
struct iwl_time_quota_cmd last_quota_cmd;
|
||||
|
||||
#ifdef CONFIG_NL80211_TESTMODE
|
||||
|
@ -1293,6 +1344,16 @@ static inline bool iwl_mvm_is_cdb_supported(struct iwl_mvm *mvm)
|
|||
IWL_UCODE_TLV_CAPA_CDB_SUPPORT);
|
||||
}
|
||||
|
||||
static inline bool iwl_mvm_cdb_scan_api(struct iwl_mvm *mvm)
|
||||
{
|
||||
/*
|
||||
* TODO: should this be the same as iwl_mvm_is_cdb_supported()?
|
||||
* but then there's a little bit of code in scan that won't make
|
||||
* any sense...
|
||||
*/
|
||||
return mvm->trans->cfg->device_family >= IWL_DEVICE_FAMILY_22000;
|
||||
}
|
||||
|
||||
static inline bool iwl_mvm_has_new_rx_stats_api(struct iwl_mvm *mvm)
|
||||
{
|
||||
return fw_has_api(&mvm->fw->ucode_capa,
|
||||
|
@ -1438,7 +1499,6 @@ void iwl_mvm_accu_radio_stats(struct iwl_mvm *mvm);
|
|||
/* NVM */
|
||||
int iwl_nvm_init(struct iwl_mvm *mvm);
|
||||
int iwl_mvm_load_nvm_to_nic(struct iwl_mvm *mvm);
|
||||
int iwl_mvm_read_external_nvm(struct iwl_mvm *mvm);
|
||||
|
||||
static inline u8 iwl_mvm_get_valid_tx_ant(struct iwl_mvm *mvm)
|
||||
{
|
||||
|
@ -1771,6 +1831,8 @@ int iwl_mvm_update_low_latency(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
|
|||
enum iwl_mvm_low_latency_cause cause);
|
||||
/* get SystemLowLatencyMode - only needed for beacon threshold? */
|
||||
bool iwl_mvm_low_latency(struct iwl_mvm *mvm);
|
||||
bool iwl_mvm_low_latency_band(struct iwl_mvm *mvm, enum nl80211_band band);
|
||||
|
||||
/* get VMACLowLatencyMode */
|
||||
static inline bool iwl_mvm_vif_low_latency(struct iwl_mvm_vif *mvmvif)
|
||||
{
|
||||
|
@ -1906,6 +1968,17 @@ bool iwl_mvm_is_vif_assoc(struct iwl_mvm *mvm);
|
|||
|
||||
void iwl_mvm_inactivity_check(struct iwl_mvm *mvm);
|
||||
|
||||
#define MVM_TCM_PERIOD_MSEC 500
|
||||
#define MVM_TCM_PERIOD (HZ * MVM_TCM_PERIOD_MSEC / 1000)
|
||||
#define MVM_LL_PERIOD (10 * HZ)
|
||||
void iwl_mvm_tcm_work(struct work_struct *work);
|
||||
void iwl_mvm_recalc_tcm(struct iwl_mvm *mvm);
|
||||
void iwl_mvm_pause_tcm(struct iwl_mvm *mvm, bool with_cancel);
|
||||
void iwl_mvm_resume_tcm(struct iwl_mvm *mvm);
|
||||
void iwl_mvm_tcm_add_vif(struct iwl_mvm *mvm, struct ieee80211_vif *vif);
|
||||
void iwl_mvm_tcm_rm_vif(struct iwl_mvm *mvm, struct ieee80211_vif *vif);
|
||||
u8 iwl_mvm_tcm_load_percentage(u32 airtime, u32 elapsed);
|
||||
|
||||
void iwl_mvm_nic_restart(struct iwl_mvm *mvm, bool fw_error);
|
||||
unsigned int iwl_mvm_get_wd_timeout(struct iwl_mvm *mvm,
|
||||
struct ieee80211_vif *vif,
|
||||
|
|
|
@ -8,6 +8,7 @@
|
|||
* Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
|
@ -35,6 +36,7 @@
|
|||
* Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
|
||||
* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
|
||||
* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
@ -76,9 +78,7 @@
|
|||
#include "fw/acpi.h"
|
||||
|
||||
/* Default NVM size to read */
|
||||
#define IWL_NVM_DEFAULT_CHUNK_SIZE (2*1024)
|
||||
#define IWL_MAX_NVM_SECTION_SIZE 0x1b58
|
||||
#define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc
|
||||
#define IWL_NVM_DEFAULT_CHUNK_SIZE (2 * 1024)
|
||||
|
||||
#define NVM_WRITE_OPCODE 1
|
||||
#define NVM_READ_OPCODE 0
|
||||
|
@ -229,19 +229,6 @@ static int iwl_nvm_write_section(struct iwl_mvm *mvm, u16 section,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void iwl_mvm_nvm_fixups(struct iwl_mvm *mvm, unsigned int section,
|
||||
u8 *data, unsigned int len)
|
||||
{
|
||||
#define IWL_4165_DEVICE_ID 0x5501
|
||||
#define NVM_SKU_CAP_MIMO_DISABLE BIT(5)
|
||||
|
||||
if (section == NVM_SECTION_TYPE_PHY_SKU &&
|
||||
mvm->trans->hw_id == IWL_4165_DEVICE_ID && data && len >= 5 &&
|
||||
(data[4] & NVM_SKU_CAP_MIMO_DISABLE))
|
||||
/* OTP 0x52 bug work around: it's a 1x1 device */
|
||||
data[3] = ANT_B | (ANT_B << 4);
|
||||
}
|
||||
|
||||
/*
|
||||
* Reads an NVM section completely.
|
||||
* NICs prior to 7000 family doesn't have a real NVM, but just read
|
||||
|
@ -282,7 +269,7 @@ static int iwl_nvm_read_section(struct iwl_mvm *mvm, u16 section,
|
|||
offset += ret;
|
||||
}
|
||||
|
||||
iwl_mvm_nvm_fixups(mvm, section, data, offset);
|
||||
iwl_nvm_fixups(mvm->trans->hw_id, section, data, offset);
|
||||
|
||||
IWL_DEBUG_EEPROM(mvm->trans->dev,
|
||||
"NVM section %d read completed\n", section);
|
||||
|
@ -355,184 +342,6 @@ iwl_parse_nvm_sections(struct iwl_mvm *mvm)
|
|||
lar_enabled);
|
||||
}
|
||||
|
||||
#define MAX_NVM_FILE_LEN 16384
|
||||
|
||||
/*
|
||||
* Reads external NVM from a file into mvm->nvm_sections
|
||||
*
|
||||
* HOW TO CREATE THE NVM FILE FORMAT:
|
||||
* ------------------------------
|
||||
* 1. create hex file, format:
|
||||
* 3800 -> header
|
||||
* 0000 -> header
|
||||
* 5a40 -> data
|
||||
*
|
||||
* rev - 6 bit (word1)
|
||||
* len - 10 bit (word1)
|
||||
* id - 4 bit (word2)
|
||||
* rsv - 12 bit (word2)
|
||||
*
|
||||
* 2. flip 8bits with 8 bits per line to get the right NVM file format
|
||||
*
|
||||
* 3. create binary file from the hex file
|
||||
*
|
||||
* 4. save as "iNVM_xxx.bin" under /lib/firmware
|
||||
*/
|
||||
int iwl_mvm_read_external_nvm(struct iwl_mvm *mvm)
|
||||
{
|
||||
int ret, section_size;
|
||||
u16 section_id;
|
||||
const struct firmware *fw_entry;
|
||||
const struct {
|
||||
__le16 word1;
|
||||
__le16 word2;
|
||||
u8 data[];
|
||||
} *file_sec;
|
||||
const u8 *eof;
|
||||
u8 *temp;
|
||||
int max_section_size;
|
||||
const __le32 *dword_buff;
|
||||
|
||||
#define NVM_WORD1_LEN(x) (8 * (x & 0x03FF))
|
||||
#define NVM_WORD2_ID(x) (x >> 12)
|
||||
#define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8))
|
||||
#define EXT_NVM_WORD1_ID(x) ((x) >> 4)
|
||||
#define NVM_HEADER_0 (0x2A504C54)
|
||||
#define NVM_HEADER_1 (0x4E564D2A)
|
||||
#define NVM_HEADER_SIZE (4 * sizeof(u32))
|
||||
|
||||
IWL_DEBUG_EEPROM(mvm->trans->dev, "Read from external NVM\n");
|
||||
|
||||
/* Maximal size depends on NVM version */
|
||||
if (mvm->trans->cfg->nvm_type != IWL_NVM_EXT)
|
||||
max_section_size = IWL_MAX_NVM_SECTION_SIZE;
|
||||
else
|
||||
max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE;
|
||||
|
||||
/*
|
||||
* Obtain NVM image via request_firmware. Since we already used
|
||||
* request_firmware_nowait() for the firmware binary load and only
|
||||
* get here after that we assume the NVM request can be satisfied
|
||||
* synchronously.
|
||||
*/
|
||||
ret = request_firmware(&fw_entry, mvm->nvm_file_name,
|
||||
mvm->trans->dev);
|
||||
if (ret) {
|
||||
IWL_ERR(mvm, "ERROR: %s isn't available %d\n",
|
||||
mvm->nvm_file_name, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
IWL_INFO(mvm, "Loaded NVM file %s (%zu bytes)\n",
|
||||
mvm->nvm_file_name, fw_entry->size);
|
||||
|
||||
if (fw_entry->size > MAX_NVM_FILE_LEN) {
|
||||
IWL_ERR(mvm, "NVM file too large\n");
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
eof = fw_entry->data + fw_entry->size;
|
||||
dword_buff = (__le32 *)fw_entry->data;
|
||||
|
||||
/* some NVM file will contain a header.
|
||||
* The header is identified by 2 dwords header as follow:
|
||||
* dword[0] = 0x2A504C54
|
||||
* dword[1] = 0x4E564D2A
|
||||
*
|
||||
* This header must be skipped when providing the NVM data to the FW.
|
||||
*/
|
||||
if (fw_entry->size > NVM_HEADER_SIZE &&
|
||||
dword_buff[0] == cpu_to_le32(NVM_HEADER_0) &&
|
||||
dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) {
|
||||
file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE);
|
||||
IWL_INFO(mvm, "NVM Version %08X\n", le32_to_cpu(dword_buff[2]));
|
||||
IWL_INFO(mvm, "NVM Manufacturing date %08X\n",
|
||||
le32_to_cpu(dword_buff[3]));
|
||||
|
||||
/* nvm file validation, dword_buff[2] holds the file version */
|
||||
if (mvm->trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
|
||||
CSR_HW_REV_STEP(mvm->trans->hw_rev) == SILICON_C_STEP &&
|
||||
le32_to_cpu(dword_buff[2]) < 0xE4A) {
|
||||
ret = -EFAULT;
|
||||
goto out;
|
||||
}
|
||||
} else {
|
||||
file_sec = (void *)fw_entry->data;
|
||||
}
|
||||
|
||||
while (true) {
|
||||
if (file_sec->data > eof) {
|
||||
IWL_ERR(mvm,
|
||||
"ERROR - NVM file too short for section header\n");
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
/* check for EOF marker */
|
||||
if (!file_sec->word1 && !file_sec->word2) {
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
if (mvm->trans->cfg->nvm_type != IWL_NVM_EXT) {
|
||||
section_size =
|
||||
2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1));
|
||||
section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2));
|
||||
} else {
|
||||
section_size = 2 * EXT_NVM_WORD2_LEN(
|
||||
le16_to_cpu(file_sec->word2));
|
||||
section_id = EXT_NVM_WORD1_ID(
|
||||
le16_to_cpu(file_sec->word1));
|
||||
}
|
||||
|
||||
if (section_size > max_section_size) {
|
||||
IWL_ERR(mvm, "ERROR - section too large (%d)\n",
|
||||
section_size);
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
if (!section_size) {
|
||||
IWL_ERR(mvm, "ERROR - section empty\n");
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
if (file_sec->data + section_size > eof) {
|
||||
IWL_ERR(mvm,
|
||||
"ERROR - NVM file too short for section (%d bytes)\n",
|
||||
section_size);
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
if (WARN(section_id >= NVM_MAX_NUM_SECTIONS,
|
||||
"Invalid NVM section ID %d\n", section_id)) {
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
temp = kmemdup(file_sec->data, section_size, GFP_KERNEL);
|
||||
if (!temp) {
|
||||
ret = -ENOMEM;
|
||||
break;
|
||||
}
|
||||
|
||||
iwl_mvm_nvm_fixups(mvm, section_id, temp, section_size);
|
||||
|
||||
kfree(mvm->nvm_sections[section_id].data);
|
||||
mvm->nvm_sections[section_id].data = temp;
|
||||
mvm->nvm_sections[section_id].length = section_size;
|
||||
|
||||
/* advance to the next section */
|
||||
file_sec = (void *)(file_sec->data + section_size);
|
||||
}
|
||||
out:
|
||||
release_firmware(fw_entry);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Loads the NVM data stored in mvm->nvm_sections into the NIC */
|
||||
int iwl_mvm_load_nvm_to_nic(struct iwl_mvm *mvm)
|
||||
{
|
||||
|
@ -585,7 +394,7 @@ int iwl_nvm_init(struct iwl_mvm *mvm)
|
|||
break;
|
||||
}
|
||||
|
||||
iwl_mvm_nvm_fixups(mvm, section, temp, ret);
|
||||
iwl_nvm_fixups(mvm->trans->hw_id, section, temp, ret);
|
||||
|
||||
mvm->nvm_sections[section].data = temp;
|
||||
mvm->nvm_sections[section].length = ret;
|
||||
|
@ -624,14 +433,17 @@ int iwl_nvm_init(struct iwl_mvm *mvm)
|
|||
/* Only if PNVM selected in the mod param - load external NVM */
|
||||
if (mvm->nvm_file_name) {
|
||||
/* read External NVM file from the mod param */
|
||||
ret = iwl_mvm_read_external_nvm(mvm);
|
||||
ret = iwl_read_external_nvm(mvm->trans, mvm->nvm_file_name,
|
||||
mvm->nvm_sections);
|
||||
if (ret) {
|
||||
mvm->nvm_file_name = nvm_file_C;
|
||||
|
||||
if ((ret == -EFAULT || ret == -ENOENT) &&
|
||||
mvm->nvm_file_name) {
|
||||
/* in case nvm file was failed try again */
|
||||
ret = iwl_mvm_read_external_nvm(mvm);
|
||||
ret = iwl_read_external_nvm(mvm->trans,
|
||||
mvm->nvm_file_name,
|
||||
mvm->nvm_sections);
|
||||
if (ret)
|
||||
return ret;
|
||||
} else {
|
||||
|
|
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