phy: for 4.6
*) Add driver for rockchip Display Port PHY *) Add driver for the Rockchip SoC internal eMMC PHY *) Add usb-uart functionality in rockchip-usb *) cleanup rcar usb2 PHY driver *) Fix for randconfig error Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJW1oAnAAoJEA5ceFyATYLZo6QP/3gZP5FBMJFNhwKSWiu9o0J3 /GtnpoD/SsgVQ0zGu7KJE3nO2wB0qZS26CrKbKkpF5nP2+ySjMs3X5NXTbgd0Ayo rLY4TeqYbYi5Xrahcl6Zf2HdszpKVZY1hHjp8OZV/PvcOqDMqtVZYUgDjh078c6U 5R4TwokyMfScJuYguBfz6XFX+Aj8Du56Iz846gsAeV05aIRXDolY0kKUyLUN3cDW jCWnoDgPvFCGBpU/n8n0xA9bNX7uf/0fjp8otomznDeMtJTW+VnzT0KwPpJ0wc4M uL/o6zw6a1wuW1iv9XxYZhbmhLlSyrgHKCcD+MMTssAf1xwpwBI7cQ6mEYrMxnFC nBSSDu6iklS7p8x8iRTxFJq6zAqMC7y/hCLXRzlI3A3hKqAglEnth4TWOx/QRVgP Lz4pAk/pdJtU573LsInE7gBnGmZnHQOQMPD2CXfNOt8vczPiRs8o4GRgkMs2VQPU PmMK1IaPIPBHgz+RdGfGxSckIaXILyCwDYMnytR0GodPidarbbfaMZCrBQg/Qo0a eFRZKpYXF21EQSjGEXOLTI4FeGxDTeGAIPW7K/v6Zx9M8BfsEBtwTGS9WaiAqqe4 eD/woa600w/TBOnE7eFcooR6d0uugbJAiUZdlPrCwlGZQqy5gMf87OkVwqxFNcVW pGQujRqVkYNmTNFRtoHW =mp9/ -----END PGP SIGNATURE----- Merge tag 'phy-for-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-testing Kishon writes: phy: for 4.6 *) Add driver for rockchip Display Port PHY *) Add driver for the Rockchip SoC internal eMMC PHY *) Add usb-uart functionality in rockchip-usb *) cleanup rcar usb2 PHY driver *) Fix for randconfig error Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Greg Kroah-Hartman
Коммит
a567500598
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@ -7,33 +7,26 @@ Required properties:
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- compatible: "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795
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SoC.
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- reg: offset and length of the partial USB 2.0 Host register block.
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- reg-names: must be "usb2_host".
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- clocks: clock phandle and specifier pair(s).
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- #phy-cells: see phy-bindings.txt in the same directory, must be <0>.
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Optional properties:
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To use a USB channel where USB 2.0 Host and HSUSB (USB 2.0 Peripheral) are
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combined, the device tree node should set HSUSB properties to reg and reg-names
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properties. This is because HSUSB has registers to select USB 2.0 host or
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peripheral at that channel:
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- reg: offset and length of the partial HSUSB register block.
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- reg-names: must be "hsusb".
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combined, the device tree node should set interrupt properties to use the
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channel as USB OTG:
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- interrupts: interrupt specifier for the PHY.
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Example (R-Car H3):
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usb-phy@ee080200 {
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compatible = "renesas,usb2-phy-r8a7795";
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reg = <0 0xee080200 0 0x700>, <0 0xe6590100 0 0x100>;
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reg-names = "usb2_host", "hsusb";
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reg = <0 0xee080200 0 0x700>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7795_CLK_EHCI0>,
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<&mstp7_clks R8A7795_CLK_HSUSB>;
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clocks = <&mstp7_clks R8A7795_CLK_EHCI0>;
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};
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usb-phy@ee0a0200 {
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compatible = "renesas,usb2-phy-r8a7795";
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reg = <0 0xee0a0200 0 0x700>;
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reg-names = "usb2_host";
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clocks = <&mstp7_clks R8A7795_CLK_EHCI0>;
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};
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@ -0,0 +1,22 @@
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Rockchip specific extensions to the Analogix Display Port PHY
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------------------------------------
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Required properties:
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- compatible : should be one of the following supported values:
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- "rockchip.rk3288-dp-phy"
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- clocks: from common clock binding: handle to dp clock.
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of memory mapped region.
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- clock-names: from common clock binding:
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Required elements: "24m"
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- rockchip,grf: phandle to the syscon managing the "general register files"
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- #phy-cells : from the generic PHY bindings, must be 0;
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Example:
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edp_phy: edp-phy {
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compatible = "rockchip,rk3288-dp-phy";
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rockchip,grf = <&grf>;
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clocks = <&cru SCLK_EDP_24M>;
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clock-names = "24m";
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#phy-cells = <0>;
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};
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@ -0,0 +1,19 @@
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Rockchip EMMC PHY
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-----------------------
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Required properties:
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- compatible: rockchip,rk3399-emmc-phy
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- rockchip,grf : phandle to the syscon managing the "general
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register files"
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- #phy-cells: must be 0
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- reg: PHY configure reg address offset in "general
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register files"
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Example:
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emmcphy: phy {
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compatible = "rockchip,rk3399-emmc-phy";
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rockchip,grf = <&grf>;
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reg = <0xf780>;
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#phy-cells = <0>;
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};
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@ -3491,6 +3491,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
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ro [KNL] Mount root device read-only on boot
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rockchip.usb_uart
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Enable the uart passthrough on the designated usb port
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on Rockchip SoCs. When active, the signals of the
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debug-uart get routed to the D+ and D- pins of the usb
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port and the regular usb controller gets disabled.
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root= [KNL] Root filesystem
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See name_to_dev_t comment in init/do_mounts.c.
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@ -32,7 +32,7 @@ config PHY_BERLIN_SATA
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config ARMADA375_USBCLUSTER_PHY
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def_bool y
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depends on MACH_ARMADA_375 || COMPILE_TEST
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depends on OF
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depends on OF && HAS_IOMEM
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select GENERIC_PHY
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config PHY_DM816X_USB
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@ -337,6 +337,20 @@ config PHY_ROCKCHIP_USB
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help
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Enable this to support the Rockchip USB 2.0 PHY.
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config PHY_ROCKCHIP_EMMC
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tristate "Rockchip EMMC PHY Driver"
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depends on ARCH_ROCKCHIP && OF
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select GENERIC_PHY
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help
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Enable this to support the Rockchip EMMC PHY.
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config PHY_ROCKCHIP_DP
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tristate "Rockchip Display Port PHY Driver"
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depends on ARCH_ROCKCHIP && OF
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select GENERIC_PHY
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help
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Enable this to support the Rockchip Display Port PHY.
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config PHY_ST_SPEAR1310_MIPHY
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tristate "ST SPEAR1310-MIPHY driver"
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select GENERIC_PHY
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|
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@ -37,6 +37,8 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
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obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
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obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
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obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
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obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o
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obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
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obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
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obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
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obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
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@ -74,20 +74,6 @@
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#define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */
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#define USB2_ADPCTRL_DRVVBUS BIT(4)
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/******* HSUSB registers (original offset is +0x100) *******/
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#define HSUSB_LPSTS 0x02
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#define HSUSB_UGCTRL2 0x84
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/* Low Power Status register (LPSTS) */
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#define HSUSB_LPSTS_SUSPM 0x4000
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/* USB General control register 2 (UGCTRL2) */
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#define HSUSB_UGCTRL2_MASK 0x00000031 /* bit[31:6] should be 0 */
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#define HSUSB_UGCTRL2_USB0SEL 0x00000030
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#define HSUSB_UGCTRL2_USB0SEL_HOST 0x00000010
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#define HSUSB_UGCTRL2_USB0SEL_HS_USB 0x00000020
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#define HSUSB_UGCTRL2_USB0SEL_OTG 0x00000030
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struct rcar_gen3_data {
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void __iomem *base;
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struct clk *clk;
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@ -95,8 +81,8 @@ struct rcar_gen3_data {
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struct rcar_gen3_chan {
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struct rcar_gen3_data usb2;
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struct rcar_gen3_data hsusb;
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struct phy *phy;
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bool has_otg;
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};
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static void rcar_gen3_set_host_mode(struct rcar_gen3_chan *ch, int host)
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@ -202,24 +188,15 @@ static int rcar_gen3_phy_usb2_init(struct phy *p)
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{
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struct rcar_gen3_chan *channel = phy_get_drvdata(p);
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void __iomem *usb2_base = channel->usb2.base;
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void __iomem *hsusb_base = channel->hsusb.base;
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u32 val;
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/* Initialize USB2 part */
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writel(USB2_INT_ENABLE_INIT, usb2_base + USB2_INT_ENABLE);
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writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
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writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);
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/* Initialize HSUSB part */
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if (hsusb_base) {
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val = readl(hsusb_base + HSUSB_UGCTRL2);
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val = (val & ~HSUSB_UGCTRL2_USB0SEL) |
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HSUSB_UGCTRL2_USB0SEL_OTG;
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writel(val & HSUSB_UGCTRL2_MASK, hsusb_base + HSUSB_UGCTRL2);
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/* Initialize otg part */
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/* Initialize otg part */
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if (channel->has_otg)
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rcar_gen3_init_otg(channel);
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}
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return 0;
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}
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@ -237,7 +214,6 @@ static int rcar_gen3_phy_usb2_power_on(struct phy *p)
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{
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struct rcar_gen3_chan *channel = phy_get_drvdata(p);
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void __iomem *usb2_base = channel->usb2.base;
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void __iomem *hsusb_base = channel->hsusb.base;
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u32 val;
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val = readl(usb2_base + USB2_USBCTR);
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@ -246,33 +222,6 @@ static int rcar_gen3_phy_usb2_power_on(struct phy *p)
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val &= ~USB2_USBCTR_PLL_RST;
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writel(val, usb2_base + USB2_USBCTR);
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/*
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* TODO: To reduce power consuming, this driver should set the SUSPM
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* after the PHY detects ID pin as peripheral.
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*/
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if (hsusb_base) {
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/* Power on HSUSB PHY */
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val = readw(hsusb_base + HSUSB_LPSTS);
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val |= HSUSB_LPSTS_SUSPM;
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writew(val, hsusb_base + HSUSB_LPSTS);
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}
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return 0;
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}
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static int rcar_gen3_phy_usb2_power_off(struct phy *p)
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{
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struct rcar_gen3_chan *channel = phy_get_drvdata(p);
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void __iomem *hsusb_base = channel->hsusb.base;
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u32 val;
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if (hsusb_base) {
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/* Power off HSUSB PHY */
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val = readw(hsusb_base + HSUSB_LPSTS);
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val &= ~HSUSB_LPSTS_SUSPM;
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writew(val, hsusb_base + HSUSB_LPSTS);
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}
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return 0;
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}
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@ -280,7 +229,6 @@ static struct phy_ops rcar_gen3_phy_usb2_ops = {
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.init = rcar_gen3_phy_usb2_init,
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.exit = rcar_gen3_phy_usb2_exit,
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.power_on = rcar_gen3_phy_usb2_power_on,
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.power_off = rcar_gen3_phy_usb2_power_off,
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.owner = THIS_MODULE,
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};
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@ -313,6 +261,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
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struct rcar_gen3_chan *channel;
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struct phy_provider *provider;
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struct resource *res;
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int irq;
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if (!dev->of_node) {
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dev_err(dev, "This driver needs device tree\n");
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@ -323,29 +272,19 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
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if (!channel)
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return -ENOMEM;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "usb2_host");
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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channel->usb2.base = devm_ioremap_resource(dev, res);
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if (IS_ERR(channel->usb2.base))
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return PTR_ERR(channel->usb2.base);
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|
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/* "hsusb" memory resource is optional */
|
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hsusb");
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|
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/* To avoid error message by devm_ioremap_resource() */
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if (res) {
|
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int irq;
|
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|
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channel->hsusb.base = devm_ioremap_resource(dev, res);
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if (IS_ERR(channel->hsusb.base))
|
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channel->hsusb.base = NULL;
|
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/* call request_irq for OTG */
|
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irq = platform_get_irq(pdev, 0);
|
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if (irq >= 0)
|
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irq = devm_request_irq(dev, irq, rcar_gen3_phy_usb2_irq,
|
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IRQF_SHARED, dev_name(dev),
|
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channel);
|
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/* call request_irq for OTG */
|
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irq = platform_get_irq(pdev, 0);
|
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if (irq >= 0) {
|
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irq = devm_request_irq(dev, irq, rcar_gen3_phy_usb2_irq,
|
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IRQF_SHARED, dev_name(dev), channel);
|
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if (irq < 0)
|
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dev_err(dev, "No irq handler (%d)\n", irq);
|
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channel->has_otg = true;
|
||||
}
|
||||
|
||||
/* devm_phy_create() will call pm_runtime_enable(dev); */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,151 @@
|
|||
/*
|
||||
* Rockchip DP PHY driver
|
||||
*
|
||||
* Copyright (C) 2016 FuZhou Rockchip Co., Ltd.
|
||||
* Author: Yakir Yang <ykk@@rock-chips.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#define GRF_SOC_CON12 0x0274
|
||||
|
||||
#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(20)
|
||||
#define GRF_EDP_REF_CLK_SEL_INTER BIT(4)
|
||||
|
||||
#define GRF_EDP_PHY_SIDDQ_HIWORD_MASK BIT(21)
|
||||
#define GRF_EDP_PHY_SIDDQ_ON 0
|
||||
#define GRF_EDP_PHY_SIDDQ_OFF BIT(5)
|
||||
|
||||
struct rockchip_dp_phy {
|
||||
struct device *dev;
|
||||
struct regmap *grf;
|
||||
struct clk *phy_24m;
|
||||
};
|
||||
|
||||
static int rockchip_set_phy_state(struct phy *phy, bool enable)
|
||||
{
|
||||
struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
|
||||
int ret;
|
||||
|
||||
if (enable) {
|
||||
ret = regmap_write(dp->grf, GRF_SOC_CON12,
|
||||
GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
|
||||
GRF_EDP_PHY_SIDDQ_ON);
|
||||
if (ret < 0) {
|
||||
dev_err(dp->dev, "Can't enable PHY power %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(dp->phy_24m);
|
||||
} else {
|
||||
clk_disable_unprepare(dp->phy_24m);
|
||||
|
||||
ret = regmap_write(dp->grf, GRF_SOC_CON12,
|
||||
GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
|
||||
GRF_EDP_PHY_SIDDQ_OFF);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rockchip_dp_phy_power_on(struct phy *phy)
|
||||
{
|
||||
return rockchip_set_phy_state(phy, true);
|
||||
}
|
||||
|
||||
static int rockchip_dp_phy_power_off(struct phy *phy)
|
||||
{
|
||||
return rockchip_set_phy_state(phy, false);
|
||||
}
|
||||
|
||||
static const struct phy_ops rockchip_dp_phy_ops = {
|
||||
.power_on = rockchip_dp_phy_power_on,
|
||||
.power_off = rockchip_dp_phy_power_off,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static int rockchip_dp_phy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct phy_provider *phy_provider;
|
||||
struct rockchip_dp_phy *dp;
|
||||
struct phy *phy;
|
||||
int ret;
|
||||
|
||||
if (!np)
|
||||
return -ENODEV;
|
||||
|
||||
dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
|
||||
if (IS_ERR(dp))
|
||||
return -ENOMEM;
|
||||
|
||||
dp->dev = dev;
|
||||
|
||||
dp->phy_24m = devm_clk_get(dev, "24m");
|
||||
if (IS_ERR(dp->phy_24m)) {
|
||||
dev_err(dev, "cannot get clock 24m\n");
|
||||
return PTR_ERR(dp->phy_24m);
|
||||
}
|
||||
|
||||
ret = clk_set_rate(dp->phy_24m, 24000000);
|
||||
if (ret < 0) {
|
||||
dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
|
||||
if (IS_ERR(dp->grf)) {
|
||||
dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
|
||||
return PTR_ERR(dp->grf);
|
||||
}
|
||||
|
||||
ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER |
|
||||
GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK);
|
||||
if (ret != 0) {
|
||||
dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);
|
||||
if (IS_ERR(phy)) {
|
||||
dev_err(dev, "failed to create phy\n");
|
||||
return PTR_ERR(phy);
|
||||
}
|
||||
phy_set_drvdata(phy, dp);
|
||||
|
||||
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
|
||||
return PTR_ERR_OR_ZERO(phy_provider);
|
||||
}
|
||||
|
||||
static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
|
||||
{ .compatible = "rockchip,rk3288-dp-phy" },
|
||||
{}
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
|
||||
|
||||
static struct platform_driver rockchip_dp_phy_driver = {
|
||||
.probe = rockchip_dp_phy_probe,
|
||||
.driver = {
|
||||
.name = "rockchip-dp-phy",
|
||||
.of_match_table = rockchip_dp_phy_dt_ids,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(rockchip_dp_phy_driver);
|
||||
|
||||
MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
|
||||
MODULE_DESCRIPTION("Rockchip DP PHY driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -0,0 +1,229 @@
|
|||
/*
|
||||
* Rockchip emmc PHY driver
|
||||
*
|
||||
* Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
|
||||
* Copyright (C) 2016 ROCKCHIP, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
/*
|
||||
* The higher 16-bit of this register is used for write protection
|
||||
* only if BIT(x + 16) set to 1 the BIT(x) can be written.
|
||||
*/
|
||||
#define HIWORD_UPDATE(val, mask, shift) \
|
||||
((val) << (shift) | (mask) << ((shift) + 16))
|
||||
|
||||
/* Register definition */
|
||||
#define GRF_EMMCPHY_CON0 0x0
|
||||
#define GRF_EMMCPHY_CON1 0x4
|
||||
#define GRF_EMMCPHY_CON2 0x8
|
||||
#define GRF_EMMCPHY_CON3 0xc
|
||||
#define GRF_EMMCPHY_CON4 0x10
|
||||
#define GRF_EMMCPHY_CON5 0x14
|
||||
#define GRF_EMMCPHY_CON6 0x18
|
||||
#define GRF_EMMCPHY_STATUS 0x20
|
||||
|
||||
#define PHYCTRL_PDB_MASK 0x1
|
||||
#define PHYCTRL_PDB_SHIFT 0x0
|
||||
#define PHYCTRL_PDB_PWR_ON 0x1
|
||||
#define PHYCTRL_PDB_PWR_OFF 0x0
|
||||
#define PHYCTRL_ENDLL_MASK 0x1
|
||||
#define PHYCTRL_ENDLL_SHIFT 0x1
|
||||
#define PHYCTRL_ENDLL_ENABLE 0x1
|
||||
#define PHYCTRL_ENDLL_DISABLE 0x0
|
||||
#define PHYCTRL_CALDONE_MASK 0x1
|
||||
#define PHYCTRL_CALDONE_SHIFT 0x6
|
||||
#define PHYCTRL_CALDONE_DONE 0x1
|
||||
#define PHYCTRL_CALDONE_GOING 0x0
|
||||
#define PHYCTRL_DLLRDY_MASK 0x1
|
||||
#define PHYCTRL_DLLRDY_SHIFT 0x5
|
||||
#define PHYCTRL_DLLRDY_DONE 0x1
|
||||
#define PHYCTRL_DLLRDY_GOING 0x0
|
||||
|
||||
struct rockchip_emmc_phy {
|
||||
unsigned int reg_offset;
|
||||
struct regmap *reg_base;
|
||||
};
|
||||
|
||||
static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy,
|
||||
bool on_off)
|
||||
{
|
||||
unsigned int caldone;
|
||||
unsigned int dllrdy;
|
||||
|
||||
/*
|
||||
* Keep phyctrl_pdb and phyctrl_endll low to allow
|
||||
* initialization of CALIO state M/C DFFs
|
||||
*/
|
||||
regmap_write(rk_phy->reg_base,
|
||||
rk_phy->reg_offset + GRF_EMMCPHY_CON6,
|
||||
HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF,
|
||||
PHYCTRL_PDB_MASK,
|
||||
PHYCTRL_PDB_SHIFT));
|
||||
regmap_write(rk_phy->reg_base,
|
||||
rk_phy->reg_offset + GRF_EMMCPHY_CON6,
|
||||
HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE,
|
||||
PHYCTRL_ENDLL_MASK,
|
||||
PHYCTRL_ENDLL_SHIFT));
|
||||
|
||||
/* Already finish power_off above */
|
||||
if (on_off == PHYCTRL_PDB_PWR_OFF)
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* According to the user manual, calpad calibration
|
||||
* cycle takes more than 2us without the minimal recommended
|
||||
* value, so we may need a little margin here
|
||||
*/
|
||||
udelay(3);
|
||||
regmap_write(rk_phy->reg_base,
|
||||
rk_phy->reg_offset + GRF_EMMCPHY_CON6,
|
||||
HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON,
|
||||
PHYCTRL_PDB_MASK,
|
||||
PHYCTRL_PDB_SHIFT));
|
||||
|
||||
/*
|
||||
* According to the user manual, it asks driver to
|
||||
* wait 5us for calpad busy trimming
|
||||
*/
|
||||
udelay(5);
|
||||
regmap_read(rk_phy->reg_base,
|
||||
rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
|
||||
&caldone);
|
||||
caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
|
||||
if (caldone != PHYCTRL_CALDONE_DONE) {
|
||||
pr_err("rockchip_emmc_phy_power: caldone timeout.\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
regmap_write(rk_phy->reg_base,
|
||||
rk_phy->reg_offset + GRF_EMMCPHY_CON6,
|
||||
HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
|
||||
PHYCTRL_ENDLL_MASK,
|
||||
PHYCTRL_ENDLL_SHIFT));
|
||||
/*
|
||||
* After enable analog DLL circuits, we need extra 10.2us
|
||||
* for dll to be ready for work.
|
||||
*/
|
||||
udelay(11);
|
||||
regmap_read(rk_phy->reg_base,
|
||||
rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
|
||||
&dllrdy);
|
||||
dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
|
||||
if (dllrdy != PHYCTRL_DLLRDY_DONE) {
|
||||
pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_emmc_phy_power_off(struct phy *phy)
|
||||
{
|
||||
struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
|
||||
int ret = 0;
|
||||
|
||||
/* Power down emmc phy analog blocks */
|
||||
ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_OFF);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_emmc_phy_power_on(struct phy *phy)
|
||||
{
|
||||
struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
|
||||
int ret = 0;
|
||||
|
||||
/* Power up emmc phy analog blocks */
|
||||
ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_ON);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct phy_ops ops = {
|
||||
.power_on = rockchip_emmc_phy_power_on,
|
||||
.power_off = rockchip_emmc_phy_power_off,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static int rockchip_emmc_phy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct rockchip_emmc_phy *rk_phy;
|
||||
struct phy *generic_phy;
|
||||
struct phy_provider *phy_provider;
|
||||
struct regmap *grf;
|
||||
unsigned int reg_offset;
|
||||
|
||||
grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
|
||||
if (IS_ERR(grf)) {
|
||||
dev_err(dev, "Missing rockchip,grf property\n");
|
||||
return PTR_ERR(grf);
|
||||
}
|
||||
|
||||
rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
|
||||
if (!rk_phy)
|
||||
return -ENOMEM;
|
||||
|
||||
if (of_property_read_u32(dev->of_node, "reg", ®_offset)) {
|
||||
dev_err(dev, "missing reg property in node %s\n",
|
||||
dev->of_node->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
rk_phy->reg_offset = reg_offset;
|
||||
rk_phy->reg_base = grf;
|
||||
|
||||
generic_phy = devm_phy_create(dev, dev->of_node, &ops);
|
||||
if (IS_ERR(generic_phy)) {
|
||||
dev_err(dev, "failed to create PHY\n");
|
||||
return PTR_ERR(generic_phy);
|
||||
}
|
||||
|
||||
phy_set_drvdata(generic_phy, rk_phy);
|
||||
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
|
||||
return PTR_ERR_OR_ZERO(phy_provider);
|
||||
}
|
||||
|
||||
static const struct of_device_id rockchip_emmc_phy_dt_ids[] = {
|
||||
{ .compatible = "rockchip,rk3399-emmc-phy" },
|
||||
{}
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids);
|
||||
|
||||
static struct platform_driver rockchip_emmc_driver = {
|
||||
.probe = rockchip_emmc_phy_probe,
|
||||
.driver = {
|
||||
.name = "rockchip-emmc-phy",
|
||||
.of_match_table = rockchip_emmc_phy_dt_ids,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(rockchip_emmc_driver);
|
||||
|
||||
MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
|
||||
MODULE_DESCRIPTION("Rockchip EMMC PHY driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -30,21 +30,23 @@
|
|||
#include <linux/regmap.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
|
||||
/*
|
||||
* The higher 16-bit of this register is used for write protection
|
||||
* only if BIT(13 + 16) set to 1 the BIT(13) can be written.
|
||||
*/
|
||||
#define SIDDQ_WRITE_ENA BIT(29)
|
||||
#define SIDDQ_ON BIT(13)
|
||||
#define SIDDQ_OFF (0 << 13)
|
||||
static int enable_usb_uart;
|
||||
|
||||
#define HIWORD_UPDATE(val, mask) \
|
||||
((val) | (mask) << 16)
|
||||
|
||||
#define UOC_CON0_SIDDQ BIT(13)
|
||||
|
||||
struct rockchip_usb_phys {
|
||||
int reg;
|
||||
const char *pll_name;
|
||||
};
|
||||
|
||||
struct rockchip_usb_phy_base;
|
||||
struct rockchip_usb_phy_pdata {
|
||||
struct rockchip_usb_phys *phys;
|
||||
int (*init_usb_uart)(struct regmap *grf);
|
||||
int usb_uart_phy;
|
||||
};
|
||||
|
||||
struct rockchip_usb_phy_base {
|
||||
|
|
@ -61,13 +63,15 @@ struct rockchip_usb_phy {
|
|||
struct clk *clk480m;
|
||||
struct clk_hw clk480m_hw;
|
||||
struct phy *phy;
|
||||
bool uart_enabled;
|
||||
};
|
||||
|
||||
static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
|
||||
bool siddq)
|
||||
{
|
||||
return regmap_write(phy->base->reg_base, phy->reg_offset,
|
||||
SIDDQ_WRITE_ENA | (siddq ? SIDDQ_ON : SIDDQ_OFF));
|
||||
u32 val = HIWORD_UPDATE(siddq ? UOC_CON0_SIDDQ : 0, UOC_CON0_SIDDQ);
|
||||
|
||||
return regmap_write(phy->base->reg_base, phy->reg_offset, val);
|
||||
}
|
||||
|
||||
static unsigned long rockchip_usb_phy480m_recalc_rate(struct clk_hw *hw,
|
||||
|
|
@ -108,7 +112,7 @@ static int rockchip_usb_phy480m_is_enabled(struct clk_hw *hw)
|
|||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return (val & SIDDQ_ON) ? 0 : 1;
|
||||
return (val & UOC_CON0_SIDDQ) ? 0 : 1;
|
||||
}
|
||||
|
||||
static const struct clk_ops rockchip_usb_phy480m_ops = {
|
||||
|
|
@ -122,6 +126,9 @@ static int rockchip_usb_phy_power_off(struct phy *_phy)
|
|||
{
|
||||
struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
|
||||
|
||||
if (phy->uart_enabled)
|
||||
return -EBUSY;
|
||||
|
||||
clk_disable_unprepare(phy->clk480m);
|
||||
|
||||
return 0;
|
||||
|
|
@ -131,6 +138,9 @@ static int rockchip_usb_phy_power_on(struct phy *_phy)
|
|||
{
|
||||
struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
|
||||
|
||||
if (phy->uart_enabled)
|
||||
return -EBUSY;
|
||||
|
||||
return clk_prepare_enable(phy->clk480m);
|
||||
}
|
||||
|
||||
|
|
@ -144,8 +154,10 @@ static void rockchip_usb_phy_action(void *data)
|
|||
{
|
||||
struct rockchip_usb_phy *rk_phy = data;
|
||||
|
||||
of_clk_del_provider(rk_phy->np);
|
||||
clk_unregister(rk_phy->clk480m);
|
||||
if (!rk_phy->uart_enabled) {
|
||||
of_clk_del_provider(rk_phy->np);
|
||||
clk_unregister(rk_phy->clk480m);
|
||||
}
|
||||
|
||||
if (rk_phy->clk)
|
||||
clk_put(rk_phy->clk);
|
||||
|
|
@ -194,31 +206,36 @@ static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (rk_phy->clk) {
|
||||
clk_name = __clk_get_name(rk_phy->clk);
|
||||
init.flags = 0;
|
||||
init.parent_names = &clk_name;
|
||||
init.num_parents = 1;
|
||||
if (enable_usb_uart && base->pdata->usb_uart_phy == i) {
|
||||
dev_dbg(base->dev, "phy%d used as uart output\n", i);
|
||||
rk_phy->uart_enabled = true;
|
||||
} else {
|
||||
init.flags = CLK_IS_ROOT;
|
||||
init.parent_names = NULL;
|
||||
init.num_parents = 0;
|
||||
if (rk_phy->clk) {
|
||||
clk_name = __clk_get_name(rk_phy->clk);
|
||||
init.flags = 0;
|
||||
init.parent_names = &clk_name;
|
||||
init.num_parents = 1;
|
||||
} else {
|
||||
init.flags = CLK_IS_ROOT;
|
||||
init.parent_names = NULL;
|
||||
init.num_parents = 0;
|
||||
}
|
||||
|
||||
init.ops = &rockchip_usb_phy480m_ops;
|
||||
rk_phy->clk480m_hw.init = &init;
|
||||
|
||||
rk_phy->clk480m = clk_register(base->dev, &rk_phy->clk480m_hw);
|
||||
if (IS_ERR(rk_phy->clk480m)) {
|
||||
err = PTR_ERR(rk_phy->clk480m);
|
||||
goto err_clk;
|
||||
}
|
||||
|
||||
err = of_clk_add_provider(child, of_clk_src_simple_get,
|
||||
rk_phy->clk480m);
|
||||
if (err < 0)
|
||||
goto err_clk_prov;
|
||||
}
|
||||
|
||||
init.ops = &rockchip_usb_phy480m_ops;
|
||||
rk_phy->clk480m_hw.init = &init;
|
||||
|
||||
rk_phy->clk480m = clk_register(base->dev, &rk_phy->clk480m_hw);
|
||||
if (IS_ERR(rk_phy->clk480m)) {
|
||||
err = PTR_ERR(rk_phy->clk480m);
|
||||
goto err_clk;
|
||||
}
|
||||
|
||||
err = of_clk_add_provider(child, of_clk_src_simple_get,
|
||||
rk_phy->clk480m);
|
||||
if (err < 0)
|
||||
goto err_clk_prov;
|
||||
|
||||
err = devm_add_action(base->dev, rockchip_usb_phy_action, rk_phy);
|
||||
if (err)
|
||||
goto err_devm_action;
|
||||
|
|
@ -230,13 +247,21 @@ static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
|
|||
}
|
||||
phy_set_drvdata(rk_phy->phy, rk_phy);
|
||||
|
||||
/* only power up usb phy when it use, so disable it when init*/
|
||||
return rockchip_usb_phy_power(rk_phy, 1);
|
||||
/*
|
||||
* When acting as uart-pipe, just keep clock on otherwise
|
||||
* only power up usb phy when it use, so disable it when init
|
||||
*/
|
||||
if (rk_phy->uart_enabled)
|
||||
return clk_prepare_enable(rk_phy->clk);
|
||||
else
|
||||
return rockchip_usb_phy_power(rk_phy, 1);
|
||||
|
||||
err_devm_action:
|
||||
of_clk_del_provider(child);
|
||||
if (!rk_phy->uart_enabled)
|
||||
of_clk_del_provider(child);
|
||||
err_clk_prov:
|
||||
clk_unregister(rk_phy->clk480m);
|
||||
if (!rk_phy->uart_enabled)
|
||||
clk_unregister(rk_phy->clk480m);
|
||||
err_clk:
|
||||
if (rk_phy->clk)
|
||||
clk_put(rk_phy->clk);
|
||||
|
|
@ -259,6 +284,86 @@ static const struct rockchip_usb_phy_pdata rk3188_pdata = {
|
|||
},
|
||||
};
|
||||
|
||||
#define RK3288_UOC0_CON0 0x320
|
||||
#define RK3288_UOC0_CON0_COMMON_ON_N BIT(0)
|
||||
#define RK3288_UOC0_CON0_DISABLE BIT(4)
|
||||
|
||||
#define RK3288_UOC0_CON2 0x328
|
||||
#define RK3288_UOC0_CON2_SOFT_CON_SEL BIT(2)
|
||||
|
||||
#define RK3288_UOC0_CON3 0x32c
|
||||
#define RK3288_UOC0_CON3_UTMI_SUSPENDN BIT(0)
|
||||
#define RK3288_UOC0_CON3_UTMI_OPMODE_NODRIVING (1 << 1)
|
||||
#define RK3288_UOC0_CON3_UTMI_OPMODE_MASK (3 << 1)
|
||||
#define RK3288_UOC0_CON3_UTMI_XCVRSEELCT_FSTRANSC (1 << 3)
|
||||
#define RK3288_UOC0_CON3_UTMI_XCVRSEELCT_MASK (3 << 3)
|
||||
#define RK3288_UOC0_CON3_UTMI_TERMSEL_FULLSPEED BIT(5)
|
||||
#define RK3288_UOC0_CON3_BYPASSDMEN BIT(6)
|
||||
#define RK3288_UOC0_CON3_BYPASSSEL BIT(7)
|
||||
|
||||
/*
|
||||
* Enable the bypass of uart2 data through the otg usb phy.
|
||||
* Original description in the TRM.
|
||||
* 1. Disable the OTG block by setting OTGDISABLE0 to 1’b1.
|
||||
* 2. Disable the pull-up resistance on the D+ line by setting
|
||||
* OPMODE0[1:0] to 2’b01.
|
||||
* 3. To ensure that the XO, Bias, and PLL blocks are powered down in Suspend
|
||||
* mode, set COMMONONN to 1’b1.
|
||||
* 4. Place the USB PHY in Suspend mode by setting SUSPENDM0 to 1’b0.
|
||||
* 5. Set BYPASSSEL0 to 1’b1.
|
||||
* 6. To transmit data, controls BYPASSDMEN0, and BYPASSDMDATA0.
|
||||
* To receive data, monitor FSVPLUS0.
|
||||
*
|
||||
* The actual code in the vendor kernel does some things differently.
|
||||
*/
|
||||
static int __init rk3288_init_usb_uart(struct regmap *grf)
|
||||
{
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* COMMON_ON and DISABLE settings are described in the TRM,
|
||||
* but were not present in the original code.
|
||||
* Also disable the analog phy components to save power.
|
||||
*/
|
||||
val = HIWORD_UPDATE(RK3288_UOC0_CON0_COMMON_ON_N
|
||||
| RK3288_UOC0_CON0_DISABLE
|
||||
| UOC_CON0_SIDDQ,
|
||||
RK3288_UOC0_CON0_COMMON_ON_N
|
||||
| RK3288_UOC0_CON0_DISABLE
|
||||
| UOC_CON0_SIDDQ);
|
||||
ret = regmap_write(grf, RK3288_UOC0_CON0, val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
val = HIWORD_UPDATE(RK3288_UOC0_CON2_SOFT_CON_SEL,
|
||||
RK3288_UOC0_CON2_SOFT_CON_SEL);
|
||||
ret = regmap_write(grf, RK3288_UOC0_CON2, val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
val = HIWORD_UPDATE(RK3288_UOC0_CON3_UTMI_OPMODE_NODRIVING
|
||||
| RK3288_UOC0_CON3_UTMI_XCVRSEELCT_FSTRANSC
|
||||
| RK3288_UOC0_CON3_UTMI_TERMSEL_FULLSPEED,
|
||||
RK3288_UOC0_CON3_UTMI_SUSPENDN
|
||||
| RK3288_UOC0_CON3_UTMI_OPMODE_MASK
|
||||
| RK3288_UOC0_CON3_UTMI_XCVRSEELCT_MASK
|
||||
| RK3288_UOC0_CON3_UTMI_TERMSEL_FULLSPEED);
|
||||
ret = regmap_write(grf, RK3288_UOC0_CON3, val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
val = HIWORD_UPDATE(RK3288_UOC0_CON3_BYPASSSEL
|
||||
| RK3288_UOC0_CON3_BYPASSDMEN,
|
||||
RK3288_UOC0_CON3_BYPASSSEL
|
||||
| RK3288_UOC0_CON3_BYPASSDMEN);
|
||||
ret = regmap_write(grf, RK3288_UOC0_CON3, val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct rockchip_usb_phy_pdata rk3288_pdata = {
|
||||
.phys = (struct rockchip_usb_phys[]){
|
||||
{ .reg = 0x320, .pll_name = "sclk_otgphy0_480m" },
|
||||
|
|
@ -266,6 +371,8 @@ static const struct rockchip_usb_phy_pdata rk3288_pdata = {
|
|||
{ .reg = 0x348, .pll_name = "sclk_otgphy2_480m" },
|
||||
{ /* sentinel */ }
|
||||
},
|
||||
.init_usb_uart = rk3288_init_usb_uart,
|
||||
.usb_uart_phy = 0,
|
||||
};
|
||||
|
||||
static int rockchip_usb_phy_probe(struct platform_device *pdev)
|
||||
|
|
@ -328,6 +435,60 @@ static struct platform_driver rockchip_usb_driver = {
|
|||
|
||||
module_platform_driver(rockchip_usb_driver);
|
||||
|
||||
#ifndef MODULE
|
||||
static int __init rockchip_init_usb_uart(void)
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
const struct rockchip_usb_phy_pdata *data;
|
||||
struct device_node *np;
|
||||
struct regmap *grf;
|
||||
int ret;
|
||||
|
||||
if (!enable_usb_uart)
|
||||
return 0;
|
||||
|
||||
np = of_find_matching_node_and_match(NULL, rockchip_usb_phy_dt_ids,
|
||||
&match);
|
||||
if (!np) {
|
||||
pr_err("%s: failed to find usbphy node\n", __func__);
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
pr_debug("%s: using settings for %s\n", __func__, match->compatible);
|
||||
data = match->data;
|
||||
|
||||
if (!data->init_usb_uart) {
|
||||
pr_err("%s: usb-uart not available on %s\n",
|
||||
__func__, match->compatible);
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
|
||||
if (IS_ERR(grf)) {
|
||||
pr_err("%s: Missing rockchip,grf property, %lu\n",
|
||||
__func__, PTR_ERR(grf));
|
||||
return PTR_ERR(grf);
|
||||
}
|
||||
|
||||
ret = data->init_usb_uart(grf);
|
||||
if (ret) {
|
||||
pr_err("%s: could not init usb_uart, %d\n", __func__, ret);
|
||||
enable_usb_uart = 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
early_initcall(rockchip_init_usb_uart);
|
||||
|
||||
static int __init rockchip_usb_uart(char *buf)
|
||||
{
|
||||
enable_usb_uart = true;
|
||||
return 0;
|
||||
}
|
||||
early_param("rockchip.usb_uart", rockchip_usb_uart);
|
||||
#endif
|
||||
|
||||
MODULE_AUTHOR("Yunzhi Li <lyz@rock-chips.com>");
|
||||
MODULE_DESCRIPTION("Rockchip USB 2.0 PHY driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
|
|||
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