drm/amdgpu: cleanup init power gating function
Remove gfx_v9_0_enable_sck_slow_down_on_power_up/down and CP power gating enabling functions because they only need to be called on setting power gating behavior. We keep it in set_powergating callback to enable/disable PG in late_init. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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72408a41d0
Коммит
a5acf93026
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@ -2065,6 +2065,9 @@ static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *ad
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static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
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{
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if (!adev->gfx.rlc.is_rlc_v2_1)
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return;
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if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
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AMD_PG_SUPPORT_GFX_SMG |
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AMD_PG_SUPPORT_GFX_DMG |
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@ -2075,24 +2078,9 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
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gfx_v9_0_init_rlc_save_restore_list(adev);
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gfx_v9_0_enable_save_restore_machine(adev);
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if (adev->asic_type == CHIP_RAVEN) {
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WREG32(mmRLC_JUMP_TABLE_RESTORE,
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adev->gfx.rlc.cp_table_gpu_addr >> 8);
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gfx_v9_0_init_gfx_power_gating(adev);
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if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
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gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
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gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
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} else {
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gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
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gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
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}
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if (adev->pg_flags & AMD_PG_SUPPORT_CP)
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gfx_v9_0_enable_cp_power_gating(adev, true);
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else
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gfx_v9_0_enable_cp_power_gating(adev, false);
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}
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WREG32(mmRLC_JUMP_TABLE_RESTORE,
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adev->gfx.rlc.cp_table_gpu_addr >> 8);
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gfx_v9_0_init_gfx_power_gating(adev);
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}
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}
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