MIPS: Octeon: Get rid of a bunch of MSI IRQ number definitions.
MSI IRQ numbers are allocated dynamically, so there is no reason to have all these static definitions. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1487/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -172,71 +172,9 @@
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#ifdef CONFIG_PCI_MSI
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/* 152 - 215 represent the MSI interrupts 0-63 */
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#define OCTEON_IRQ_MSI_BIT0 152
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#define OCTEON_IRQ_MSI_BIT1 153
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#define OCTEON_IRQ_MSI_BIT2 154
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#define OCTEON_IRQ_MSI_BIT3 155
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#define OCTEON_IRQ_MSI_BIT4 156
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#define OCTEON_IRQ_MSI_BIT5 157
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#define OCTEON_IRQ_MSI_BIT6 158
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#define OCTEON_IRQ_MSI_BIT7 159
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#define OCTEON_IRQ_MSI_BIT8 160
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#define OCTEON_IRQ_MSI_BIT9 161
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#define OCTEON_IRQ_MSI_BIT10 162
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#define OCTEON_IRQ_MSI_BIT11 163
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#define OCTEON_IRQ_MSI_BIT12 164
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#define OCTEON_IRQ_MSI_BIT13 165
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#define OCTEON_IRQ_MSI_BIT14 166
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#define OCTEON_IRQ_MSI_BIT15 167
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#define OCTEON_IRQ_MSI_BIT16 168
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#define OCTEON_IRQ_MSI_BIT17 169
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#define OCTEON_IRQ_MSI_BIT18 170
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#define OCTEON_IRQ_MSI_BIT19 171
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#define OCTEON_IRQ_MSI_BIT20 172
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#define OCTEON_IRQ_MSI_BIT21 173
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#define OCTEON_IRQ_MSI_BIT22 174
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#define OCTEON_IRQ_MSI_BIT23 175
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#define OCTEON_IRQ_MSI_BIT24 176
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#define OCTEON_IRQ_MSI_BIT25 177
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#define OCTEON_IRQ_MSI_BIT26 178
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#define OCTEON_IRQ_MSI_BIT27 179
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#define OCTEON_IRQ_MSI_BIT28 180
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#define OCTEON_IRQ_MSI_BIT29 181
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#define OCTEON_IRQ_MSI_BIT30 182
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#define OCTEON_IRQ_MSI_BIT31 183
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#define OCTEON_IRQ_MSI_BIT32 184
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#define OCTEON_IRQ_MSI_BIT33 185
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#define OCTEON_IRQ_MSI_BIT34 186
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#define OCTEON_IRQ_MSI_BIT35 187
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#define OCTEON_IRQ_MSI_BIT36 188
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#define OCTEON_IRQ_MSI_BIT37 189
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#define OCTEON_IRQ_MSI_BIT38 190
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#define OCTEON_IRQ_MSI_BIT39 191
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#define OCTEON_IRQ_MSI_BIT40 192
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#define OCTEON_IRQ_MSI_BIT41 193
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#define OCTEON_IRQ_MSI_BIT42 194
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#define OCTEON_IRQ_MSI_BIT43 195
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#define OCTEON_IRQ_MSI_BIT44 196
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#define OCTEON_IRQ_MSI_BIT45 197
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#define OCTEON_IRQ_MSI_BIT46 198
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#define OCTEON_IRQ_MSI_BIT47 199
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#define OCTEON_IRQ_MSI_BIT48 200
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#define OCTEON_IRQ_MSI_BIT49 201
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#define OCTEON_IRQ_MSI_BIT50 202
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#define OCTEON_IRQ_MSI_BIT51 203
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#define OCTEON_IRQ_MSI_BIT52 204
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#define OCTEON_IRQ_MSI_BIT53 205
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#define OCTEON_IRQ_MSI_BIT54 206
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#define OCTEON_IRQ_MSI_BIT55 207
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#define OCTEON_IRQ_MSI_BIT56 208
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#define OCTEON_IRQ_MSI_BIT57 209
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#define OCTEON_IRQ_MSI_BIT58 210
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#define OCTEON_IRQ_MSI_BIT59 211
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#define OCTEON_IRQ_MSI_BIT60 212
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#define OCTEON_IRQ_MSI_BIT61 213
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#define OCTEON_IRQ_MSI_BIT62 214
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#define OCTEON_IRQ_MSI_BIT63 215
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#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 63)
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#define OCTEON_IRQ_LAST 216
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#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1)
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#else
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#define OCTEON_IRQ_LAST 152
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#endif
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@ -181,7 +181,7 @@ void arch_teardown_msi_irq(unsigned int irq)
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int number_irqs;
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uint64_t bitmask;
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if ((irq < OCTEON_IRQ_MSI_BIT0) || (irq > OCTEON_IRQ_MSI_BIT63))
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if ((irq < OCTEON_IRQ_MSI_BIT0) || (irq > OCTEON_IRQ_MSI_LAST))
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panic("arch_teardown_msi_irq: Attempted to teardown illegal "
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"MSI interrupt (%d)", irq);
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irq -= OCTEON_IRQ_MSI_BIT0;
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@ -337,7 +337,7 @@ static int __init octeon_msi_initialize(void)
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{
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int irq;
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for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_BIT63; irq++) {
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for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++) {
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set_irq_chip_and_handler(irq, &octeon_irq_chip_msi,
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handle_percpu_irq);
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}
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