OMAP4: powerdomains: add PRCM partition data; use OMAP4 PRM functions
OMAP4 powerdomain control registers are split between the PRM hardware module and the PRCM_MPU local PRCM. Add this PRCM partition information to each OMAP4 powerdomain record, and convert the OMAP4 powerdomain function implementations to use the OMAP4 PRM instance functions. Also fixes a potential null pointer dereference of pwrdm->name. The autogeneration scripts have been updated. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Benoît Cousson <b-cousson@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Rajendra Nayak <rnayak@ti.com>
This commit is contained in:
Paul Walmsley
Родитель
c4d7e58fb5
Коммит
a64bb9cda8
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@ -20,6 +20,7 @@
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#include <linux/errno.h>
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#include <linux/string.h>
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#include "cm2xxx_3xxx.h"
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#include "prcm44xx.h"
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#include "cm44xx.h"
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#include "prm2xxx_3xxx.h"
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#include "prm44xx.h"
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@ -72,12 +73,19 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
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{
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int i;
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if (!pwrdm)
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if (!pwrdm || !pwrdm->name)
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return -EINVAL;
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if (!omap_chip_is(pwrdm->omap_chip))
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return -EINVAL;
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if (cpu_is_omap44xx() &&
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pwrdm->prcm_partition == OMAP4430_INVALID_PRCM_PARTITION) {
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pr_err("powerdomain: %s: missing OMAP4 PRCM partition ID\n",
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pwrdm->name);
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return -EINVAL;
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}
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if (_pwrdm_lookup(pwrdm->name))
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return -EEXIST;
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@ -20,48 +20,70 @@
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#include <plat/prcm.h>
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#include "prm2xxx_3xxx.h"
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#include "prm44xx.h"
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#include "prminst44xx.h"
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#include "prm-regbits-44xx.h"
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#include "powerdomains.h"
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static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
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{
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omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
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(pwrst << OMAP_POWERSTATE_SHIFT),
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pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
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omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
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(pwrst << OMAP_POWERSTATE_SHIFT),
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pwrdm->prcm_partition,
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pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
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return 0;
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}
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static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
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{
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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OMAP4_PM_PWSTCTRL, OMAP_POWERSTATE_MASK);
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u32 v;
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v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
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OMAP4_PM_PWSTCTRL);
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v &= OMAP_POWERSTATE_MASK;
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v >>= OMAP_POWERSTATE_SHIFT;
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return v;
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}
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static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
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{
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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OMAP4_PM_PWSTST, OMAP_POWERSTATEST_MASK);
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u32 v;
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v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
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OMAP4_PM_PWSTST);
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v &= OMAP_POWERSTATEST_MASK;
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v >>= OMAP_POWERSTATEST_SHIFT;
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return v;
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}
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static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
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{
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST,
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OMAP4430_LASTPOWERSTATEENTERED_MASK);
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u32 v;
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v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
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OMAP4_PM_PWSTST);
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v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
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v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
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return v;
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}
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static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
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{
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omap2_prm_rmw_mod_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
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(1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
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pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
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omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
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(1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
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pwrdm->prcm_partition,
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pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
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return 0;
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}
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static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
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{
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omap2_prm_rmw_mod_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
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OMAP4430_LASTPOWERSTATEENTERED_MASK,
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pwrdm->prcm_offs, OMAP4_PM_PWSTST);
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omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
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OMAP4430_LASTPOWERSTATEENTERED_MASK,
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pwrdm->prcm_partition,
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pwrdm->prcm_offs, OMAP4_PM_PWSTST);
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return 0;
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}
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@ -70,69 +92,91 @@ static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
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u32 v;
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v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
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omap2_prm_rmw_mod_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
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pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
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omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
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pwrdm->prcm_partition, pwrdm->prcm_offs,
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OMAP4_PM_PWSTCTRL);
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return 0;
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}
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static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
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u8 pwrst)
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u8 pwrst)
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{
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u32 m;
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m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
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omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
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OMAP4_PM_PWSTCTRL);
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omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
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pwrdm->prcm_partition, pwrdm->prcm_offs,
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OMAP4_PM_PWSTCTRL);
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return 0;
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}
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static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
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u8 pwrst)
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u8 pwrst)
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{
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u32 m;
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m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
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omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
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OMAP4_PM_PWSTCTRL);
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omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
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pwrdm->prcm_partition, pwrdm->prcm_offs,
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OMAP4_PM_PWSTCTRL);
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return 0;
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}
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static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
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{
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST,
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OMAP4430_LOGICSTATEST_MASK);
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u32 v;
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v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
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OMAP4_PM_PWSTST);
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v &= OMAP4430_LOGICSTATEST_MASK;
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v >>= OMAP4430_LOGICSTATEST_SHIFT;
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return v;
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}
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static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
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{
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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OMAP4_PM_PWSTCTRL,
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OMAP4430_LOGICRETSTATE_MASK);
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u32 v;
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v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
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OMAP4_PM_PWSTCTRL);
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v &= OMAP4430_LOGICRETSTATE_MASK;
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v >>= OMAP4430_LOGICRETSTATE_SHIFT;
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return v;
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}
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static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
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{
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u32 m;
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u32 m, v;
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m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST,
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m);
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v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
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OMAP4_PM_PWSTST);
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v &= m;
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v >>= __ffs(m);
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return v;
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}
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static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
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{
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u32 m;
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u32 m, v;
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m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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OMAP4_PM_PWSTCTRL, m);
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v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
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OMAP4_PM_PWSTCTRL);
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v &= m;
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v >>= __ffs(m);
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return v;
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}
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static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
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@ -146,14 +190,16 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
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*/
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/* XXX Is this udelay() value meaningful? */
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while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP4_PM_PWSTST) &
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while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
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pwrdm->prcm_offs,
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OMAP4_PM_PWSTST) &
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OMAP_INTRANSITION_MASK) &&
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(c++ < PWRDM_TRANSITION_BAILOUT))
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udelay(1);
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(c++ < PWRDM_TRANSITION_BAILOUT))
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udelay(1);
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if (c > PWRDM_TRANSITION_BAILOUT) {
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printk(KERN_ERR "powerdomain: waited too long for "
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"powerdomain %s to complete transition\n", pwrdm->name);
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"powerdomain %s to complete transition\n", pwrdm->name);
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return -EAGAIN;
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}
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@ -26,6 +26,7 @@
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#include "powerdomains.h"
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#include "prcm-common.h"
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#include "prcm44xx.h"
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#include "prm-regbits-44xx.h"
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#include "prm44xx.h"
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#include "prcm_mpu44xx.h"
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@ -34,6 +35,7 @@
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static struct powerdomain core_44xx_pwrdm = {
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.name = "core_pwrdm",
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.prcm_offs = OMAP4430_PRM_CORE_INST,
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.prcm_partition = OMAP4430_PRM_PARTITION,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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@ -59,6 +61,7 @@ static struct powerdomain core_44xx_pwrdm = {
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static struct powerdomain gfx_44xx_pwrdm = {
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.name = "gfx_pwrdm",
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.prcm_offs = OMAP4430_PRM_GFX_INST,
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.prcm_partition = OMAP4430_PRM_PARTITION,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_ON,
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.banks = 1,
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@ -75,6 +78,7 @@ static struct powerdomain gfx_44xx_pwrdm = {
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static struct powerdomain abe_44xx_pwrdm = {
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.name = "abe_pwrdm",
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.prcm_offs = OMAP4430_PRM_ABE_INST,
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.prcm_partition = OMAP4430_PRM_PARTITION,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRDM_POWER_OFF,
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@ -94,6 +98,7 @@ static struct powerdomain abe_44xx_pwrdm = {
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static struct powerdomain dss_44xx_pwrdm = {
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.name = "dss_pwrdm",
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.prcm_offs = OMAP4430_PRM_DSS_INST,
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.prcm_partition = OMAP4430_PRM_PARTITION,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF,
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@ -111,6 +116,7 @@ static struct powerdomain dss_44xx_pwrdm = {
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static struct powerdomain tesla_44xx_pwrdm = {
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.name = "tesla_pwrdm",
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.prcm_offs = OMAP4430_PRM_TESLA_INST,
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.prcm_partition = OMAP4430_PRM_PARTITION,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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@ -132,6 +138,7 @@ static struct powerdomain tesla_44xx_pwrdm = {
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static struct powerdomain wkup_44xx_pwrdm = {
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.name = "wkup_pwrdm",
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.prcm_offs = OMAP4430_PRM_WKUP_INST,
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.prcm_partition = OMAP4430_PRM_PARTITION,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_ON,
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.banks = 1,
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@ -147,6 +154,7 @@ static struct powerdomain wkup_44xx_pwrdm = {
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static struct powerdomain cpu0_44xx_pwrdm = {
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.name = "cpu0_pwrdm",
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.prcm_offs = OMAP4430_PRCM_MPU_CPU0_INST,
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.prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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@ -163,6 +171,7 @@ static struct powerdomain cpu0_44xx_pwrdm = {
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static struct powerdomain cpu1_44xx_pwrdm = {
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.name = "cpu1_pwrdm",
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.prcm_offs = OMAP4430_PRCM_MPU_CPU1_INST,
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.prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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@ -179,6 +188,7 @@ static struct powerdomain cpu1_44xx_pwrdm = {
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static struct powerdomain emu_44xx_pwrdm = {
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.name = "emu_pwrdm",
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.prcm_offs = OMAP4430_PRM_EMU_INST,
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.prcm_partition = OMAP4430_PRM_PARTITION,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_ON,
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.banks = 1,
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@ -194,6 +204,7 @@ static struct powerdomain emu_44xx_pwrdm = {
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static struct powerdomain mpu_44xx_pwrdm = {
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.name = "mpu_pwrdm",
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.prcm_offs = OMAP4430_PRM_MPU_INST,
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.prcm_partition = OMAP4430_PRM_PARTITION,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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@ -214,6 +225,7 @@ static struct powerdomain mpu_44xx_pwrdm = {
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static struct powerdomain ivahd_44xx_pwrdm = {
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.name = "ivahd_pwrdm",
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.prcm_offs = OMAP4430_PRM_IVAHD_INST,
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.prcm_partition = OMAP4430_PRM_PARTITION,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRDM_POWER_OFF,
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@ -237,6 +249,7 @@ static struct powerdomain ivahd_44xx_pwrdm = {
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static struct powerdomain cam_44xx_pwrdm = {
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.name = "cam_pwrdm",
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.prcm_offs = OMAP4430_PRM_CAM_INST,
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.prcm_partition = OMAP4430_PRM_PARTITION,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_ON,
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.banks = 1,
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@ -253,6 +266,7 @@ static struct powerdomain cam_44xx_pwrdm = {
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static struct powerdomain l3init_44xx_pwrdm = {
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.name = "l3init_pwrdm",
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.prcm_offs = OMAP4430_PRM_L3INIT_INST,
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.prcm_partition = OMAP4430_PRM_PARTITION,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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@ -270,6 +284,7 @@ static struct powerdomain l3init_44xx_pwrdm = {
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|||
static struct powerdomain l4per_44xx_pwrdm = {
|
||||
.name = "l4per_pwrdm",
|
||||
.prcm_offs = OMAP4430_PRM_L4PER_INST,
|
||||
.prcm_partition = OMAP4430_PRM_PARTITION,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
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||||
|
|
@ -292,6 +307,7 @@ static struct powerdomain l4per_44xx_pwrdm = {
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|||
static struct powerdomain always_on_core_44xx_pwrdm = {
|
||||
.name = "always_on_core_pwrdm",
|
||||
.prcm_offs = OMAP4430_PRM_ALWAYS_ON_INST,
|
||||
.prcm_partition = OMAP4430_PRM_PARTITION,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
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.pwrsts = PWRSTS_ON,
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||||
};
|
||||
|
|
@ -300,6 +316,7 @@ static struct powerdomain always_on_core_44xx_pwrdm = {
|
|||
static struct powerdomain cefuse_44xx_pwrdm = {
|
||||
.name = "cefuse_pwrdm",
|
||||
.prcm_offs = OMAP4430_PRM_CEFUSE_INST,
|
||||
.prcm_partition = OMAP4430_PRM_PARTITION,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
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|||
/*
|
||||
* OMAP2/3 powerdomain control
|
||||
* OMAP2/3/4 powerdomain control
|
||||
*
|
||||
* Copyright (C) 2007-2008 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007-2010 Nokia Corporation
|
||||
|
|
@ -24,7 +24,6 @@
|
|||
|
||||
#include <plat/cpu.h>
|
||||
|
||||
|
||||
/* Powerdomain basic power states */
|
||||
#define PWRDM_POWER_OFF 0x0
|
||||
#define PWRDM_POWER_RET 0x1
|
||||
|
|
@ -84,6 +83,7 @@ struct powerdomain;
|
|||
* @name: Powerdomain name
|
||||
* @omap_chip: represents the OMAP chip types containing this pwrdm
|
||||
* @prcm_offs: the address offset from CM_BASE/PRM_BASE
|
||||
* @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
|
||||
* @pwrsts: Possible powerdomain power states
|
||||
* @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
|
||||
* @flags: Powerdomain flags
|
||||
|
|
@ -96,6 +96,8 @@ struct powerdomain;
|
|||
* @state_counter:
|
||||
* @timer:
|
||||
* @state_timer:
|
||||
*
|
||||
* @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
|
||||
*/
|
||||
struct powerdomain {
|
||||
const char *name;
|
||||
|
|
@ -107,6 +109,7 @@ struct powerdomain {
|
|||
const u8 banks;
|
||||
const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
|
||||
const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
|
||||
const u8 prcm_partition;
|
||||
struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
|
||||
struct list_head node;
|
||||
int state;
|
||||
|
|
|
|||
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