drm/i915: Move VIDEO_DIP_CTL definitions to their right place.
The bits weren't defined in descending order. v2: Move definitions in a separate patch (Manasi) Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181005185643.31660-2-dhinakaran.pandiyan@intel.com
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@ -4564,6 +4564,15 @@ enum {
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#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
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#define VIDEO_DIP_FREQ_MASK (3 << 16)
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/* HSW and later: */
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#define DRM_DIP_ENABLE (1 << 28)
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#define PSR_VSC_BIT_7_SET (1 << 27)
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#define VSC_SELECT_MASK (0x3 << 25)
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#define VSC_SELECT_SHIFT 25
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#define VSC_DIP_HW_HEA_DATA (0 << 25)
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#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
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#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
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#define VSC_DIP_SW_HEA_DATA (3 << 25)
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#define VDIP_ENABLE_PPS (1 << 24)
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#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
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#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
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#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
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@ -4571,16 +4580,6 @@ enum {
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#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
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#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
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#define DRM_DIP_ENABLE (1 << 28)
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#define PSR_VSC_BIT_7_SET (1 << 27)
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#define VSC_SELECT_MASK (0x3 << 25)
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#define VSC_SELECT_SHIFT 25
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#define VSC_DIP_HW_HEA_DATA (0 << 25)
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#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
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#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
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#define VSC_DIP_SW_HEA_DATA (3 << 25)
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#define VDIP_ENABLE_PPS (1 << 24)
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/* Panel power sequencing */
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#define PPS_BASE 0x61200
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#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
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