ARM: OMAP2+: Drop i2c platform data for dra7
We can now drop legacy platform data one interconnect target module at a time in favor of the device tree based data that has been added earlier. Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren
Родитель
ede0ac6422
Коммит
a688939a97
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@ -19,7 +19,6 @@
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#include <linux/io.h>
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#include <linux/power/smartreflex.h>
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#include <linux/platform_data/i2c-omap.h>
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#include <linux/omap-dma.h>
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@ -28,7 +27,6 @@
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#include "cm1_7xx.h"
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#include "cm2_7xx.h"
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#include "prm7xx.h"
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#include "i2c.h"
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#include "wd_timer.h"
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#include "soc.h"
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@ -1060,109 +1058,6 @@ static struct omap_hwmod dra7xx_hdq1w_hwmod = {
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},
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};
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/*
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* 'i2c' class
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*
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*/
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static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
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.rev_offs = 0,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0090,
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.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
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SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
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SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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SIDLE_SMART_WKUP),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
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.name = "i2c",
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.sysc = &dra7xx_i2c_sysc,
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.reset = &omap_i2c_reset,
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};
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/* i2c1 */
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static struct omap_hwmod dra7xx_i2c1_hwmod = {
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.name = "i2c1",
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.class = &dra7xx_i2c_hwmod_class,
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.clkdm_name = "l4per_clkdm",
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.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
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.main_clk = "func_96m_fclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
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.context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* i2c2 */
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static struct omap_hwmod dra7xx_i2c2_hwmod = {
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.name = "i2c2",
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.class = &dra7xx_i2c_hwmod_class,
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.clkdm_name = "l4per_clkdm",
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.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
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.main_clk = "func_96m_fclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
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.context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* i2c3 */
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static struct omap_hwmod dra7xx_i2c3_hwmod = {
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.name = "i2c3",
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.class = &dra7xx_i2c_hwmod_class,
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.clkdm_name = "l4per_clkdm",
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.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
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.main_clk = "func_96m_fclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
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.context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* i2c4 */
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static struct omap_hwmod dra7xx_i2c4_hwmod = {
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.name = "i2c4",
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.class = &dra7xx_i2c_hwmod_class,
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.clkdm_name = "l4per_clkdm",
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.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
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.main_clk = "func_96m_fclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
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.context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* i2c5 */
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static struct omap_hwmod dra7xx_i2c5_hwmod = {
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.name = "i2c5",
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.class = &dra7xx_i2c_hwmod_class,
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.clkdm_name = "ipu_clkdm",
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.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
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.main_clk = "func_96m_fclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
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.context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/*
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* 'mailbox' class
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*
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@ -3075,46 +2970,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_per1 -> i2c1 */
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static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
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.master = &dra7xx_l4_per1_hwmod,
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.slave = &dra7xx_i2c1_hwmod,
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.clk = "l3_iclk_div",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_per1 -> i2c2 */
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static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
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.master = &dra7xx_l4_per1_hwmod,
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.slave = &dra7xx_i2c2_hwmod,
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.clk = "l3_iclk_div",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_per1 -> i2c3 */
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static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
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.master = &dra7xx_l4_per1_hwmod,
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.slave = &dra7xx_i2c3_hwmod,
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.clk = "l3_iclk_div",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_per1 -> i2c4 */
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static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
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.master = &dra7xx_l4_per1_hwmod,
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.slave = &dra7xx_i2c4_hwmod,
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.clk = "l3_iclk_div",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_per1 -> i2c5 */
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static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
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.master = &dra7xx_l4_per1_hwmod,
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.slave = &dra7xx_i2c5_hwmod,
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.clk = "l3_iclk_div",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_cfg -> mailbox1 */
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static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
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.master = &dra7xx_l4_cfg_hwmod,
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@ -3726,11 +3581,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
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&dra7xx_l4_per1__gpio8,
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&dra7xx_l3_main_1__gpmc,
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&dra7xx_l4_per1__hdq1w,
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&dra7xx_l4_per1__i2c1,
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&dra7xx_l4_per1__i2c2,
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&dra7xx_l4_per1__i2c3,
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&dra7xx_l4_per1__i2c4,
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&dra7xx_l4_per1__i2c5,
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&dra7xx_l4_cfg__mailbox1,
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&dra7xx_l4_per3__mailbox2,
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&dra7xx_l4_per3__mailbox3,
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