[SCSI] bfa: Flash controller IOC pll init fixes.
Made changes to resume the flash controller if it is halted before going ahead with flash controller pause/resume logic. Made changes to avoid clearing off the interrupts during the initial pll initialization. Signed-off-by: Krishna Gudipati <kgudipat@brocade.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
This commit is contained in:
Krishna Gudipati
James Bottomley
Родитель
8919678eaa
Коммит
a6b963db0d
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@ -786,17 +786,73 @@ bfa_ioc_ct2_mac_reset(void __iomem *rb)
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}
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#define CT2_NFC_MAX_DELAY 1000
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#define CT2_NFC_VER_VALID 0x143
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#define BFA_IOC_PLL_POLL 1000000
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static bfa_boolean_t
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bfa_ioc_ct2_nfc_halted(void __iomem *rb)
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{
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u32 r32;
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r32 = readl(rb + CT2_NFC_CSR_SET_REG);
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if (r32 & __NFC_CONTROLLER_HALTED)
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return BFA_TRUE;
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return BFA_FALSE;
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}
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static void
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bfa_ioc_ct2_nfc_resume(void __iomem *rb)
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{
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u32 r32;
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int i;
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writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_CLR_REG);
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for (i = 0; i < CT2_NFC_MAX_DELAY; i++) {
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r32 = readl(rb + CT2_NFC_CSR_SET_REG);
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if (!(r32 & __NFC_CONTROLLER_HALTED))
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return;
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udelay(1000);
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}
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WARN_ON(1);
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}
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bfa_status_t
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bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode mode)
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{
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u32 wgn, r32;
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int i;
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u32 wgn, r32, nfc_ver, i;
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/*
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* Initialize PLL if not already done by NFC
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*/
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wgn = readl(rb + CT2_WGN_STATUS);
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if (!(wgn & __GLBL_PF_VF_CFG_RDY)) {
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nfc_ver = readl(rb + CT2_RSC_GPR15_REG);
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if ((wgn == (__A2T_AHB_LOAD | __WGN_READY)) &&
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(nfc_ver >= CT2_NFC_VER_VALID)) {
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if (bfa_ioc_ct2_nfc_halted(rb))
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bfa_ioc_ct2_nfc_resume(rb);
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writel(__RESET_AND_START_SCLK_LCLK_PLLS,
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rb + CT2_CSI_FW_CTL_SET_REG);
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for (i = 0; i < BFA_IOC_PLL_POLL; i++) {
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r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);
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if (r32 & __RESET_AND_START_SCLK_LCLK_PLLS)
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break;
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}
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WARN_ON(!(r32 & __RESET_AND_START_SCLK_LCLK_PLLS));
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for (i = 0; i < BFA_IOC_PLL_POLL; i++) {
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r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);
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if (!(r32 & __RESET_AND_START_SCLK_LCLK_PLLS))
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break;
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}
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WARN_ON(r32 & __RESET_AND_START_SCLK_LCLK_PLLS);
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udelay(1000);
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r32 = readl(rb + CT2_CSI_FW_CTL_REG);
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WARN_ON(r32 & __RESET_AND_START_SCLK_LCLK_PLLS);
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} else {
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writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_SET_REG);
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for (i = 0; i < CT2_NFC_MAX_DELAY; i++) {
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r32 = readl(rb + CT2_NFC_CSR_SET_REG);
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@ -804,6 +860,34 @@ bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode mode)
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break;
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udelay(1000);
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}
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bfa_ioc_ct2_mac_reset(rb);
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bfa_ioc_ct2_sclk_init(rb);
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bfa_ioc_ct2_lclk_init(rb);
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/*
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* release soft reset on s_clk & l_clk
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*/
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r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG);
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writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET,
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(rb + CT2_APP_PLL_SCLK_CTL_REG));
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/*
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* release soft reset on s_clk & l_clk
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*/
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r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);
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writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET,
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(rb + CT2_APP_PLL_LCLK_CTL_REG));
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}
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/*
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* Announce flash device presence, if flash was corrupted.
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*/
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if (wgn == (__WGN_READY | __GLBL_PF_VF_CFG_RDY)) {
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r32 = readl(rb + PSS_GPIO_OUT_REG);
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writel(r32 & ~1, (rb + PSS_GPIO_OUT_REG));
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r32 = readl(rb + PSS_GPIO_OE_REG);
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writel(r32 | 1, (rb + PSS_GPIO_OE_REG));
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}
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/*
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@ -813,48 +897,25 @@ bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode mode)
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writel(1, (rb + CT2_LPU0_HOSTFN_MBOX0_MSK));
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writel(1, (rb + CT2_LPU1_HOSTFN_MBOX0_MSK));
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r32 = readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));
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if (r32 == 1) {
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writel(1, (rb + CT2_LPU0_HOSTFN_CMD_STAT));
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readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));
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}
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r32 = readl((rb + CT2_LPU1_HOSTFN_CMD_STAT));
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if (r32 == 1) {
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writel(1, (rb + CT2_LPU1_HOSTFN_CMD_STAT));
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readl((rb + CT2_LPU1_HOSTFN_CMD_STAT));
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}
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bfa_ioc_ct2_mac_reset(rb);
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bfa_ioc_ct2_sclk_init(rb);
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bfa_ioc_ct2_lclk_init(rb);
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/*
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* release soft reset on s_clk & l_clk
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*/
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r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
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writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET,
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(rb + CT2_APP_PLL_SCLK_CTL_REG));
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/*
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* release soft reset on s_clk & l_clk
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*/
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r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
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writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET,
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(rb + CT2_APP_PLL_LCLK_CTL_REG));
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/*
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* Announce flash device presence, if flash was corrupted.
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*/
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if (wgn == (__WGN_READY | __GLBL_PF_VF_CFG_RDY)) {
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r32 = readl((rb + PSS_GPIO_OUT_REG));
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writel(r32 & ~1, (rb + PSS_GPIO_OUT_REG));
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r32 = readl((rb + PSS_GPIO_OE_REG));
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writel(r32 | 1, (rb + PSS_GPIO_OE_REG));
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/* For first time initialization, no need to clear interrupts */
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r32 = readl(rb + HOST_SEM5_REG);
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if (r32 & 0x1) {
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r32 = readl(rb + CT2_LPU0_HOSTFN_CMD_STAT);
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if (r32 == 1) {
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writel(1, rb + CT2_LPU0_HOSTFN_CMD_STAT);
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readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));
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}
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r32 = readl(rb + CT2_LPU1_HOSTFN_CMD_STAT);
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if (r32 == 1) {
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writel(1, rb + CT2_LPU1_HOSTFN_CMD_STAT);
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readl(rb + CT2_LPU1_HOSTFN_CMD_STAT);
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}
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}
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bfa_ioc_ct2_mem_init(rb);
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writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC0_STATE_REG));
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writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC1_STATE_REG));
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writel(BFI_IOC_UNINIT, rb + CT2_BFA_IOC0_STATE_REG);
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writel(BFI_IOC_UNINIT, rb + CT2_BFA_IOC1_STATE_REG);
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return BFA_STATUS_OK;
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}
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@ -335,11 +335,17 @@ enum {
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#define __PMM_1T_PNDB_P 0x00000002
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#define CT2_PMM_1T_CONTROL_REG_P1 0x00023c1c
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#define CT2_WGN_STATUS 0x00014990
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#define __A2T_AHB_LOAD 0x00000800
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#define __WGN_READY 0x00000400
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#define __GLBL_PF_VF_CFG_RDY 0x00000200
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#define CT2_NFC_CSR_CLR_REG 0x00027420
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#define CT2_NFC_CSR_SET_REG 0x00027424
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#define __HALT_NFC_CONTROLLER 0x00000002
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#define __NFC_CONTROLLER_HALTED 0x00001000
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#define CT2_RSC_GPR15_REG 0x0002765c
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#define CT2_CSI_FW_CTL_REG 0x00027080
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#define CT2_CSI_FW_CTL_SET_REG 0x00027088
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#define __RESET_AND_START_SCLK_LCLK_PLLS 0x00010000
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#define CT2_CSI_MAC0_CONTROL_REG 0x000270d0
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#define __CSI_MAC_RESET 0x00000010
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