dmaengine: milbeaut-xdmac: Add XDMAC driver for Milbeaut platforms
Driver for Socionext Milbeaut XDMAC controller. The controller only supports Mem-To-Mem transfers over upto 8 configurable channels. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Link: https://lore.kernel.org/r/20191015033219.14713-1-jassisinghbrar@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Jassi Brar
Vinod Koul
Родитель
3708f89b33
Коммит
a6e9be055d
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@ -352,6 +352,16 @@ config MILBEAUT_HDMAC
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Say yes here to support the Socionext Milbeaut
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HDMAC device.
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config MILBEAUT_XDMAC
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tristate "Milbeaut AXI DMA support"
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depends on ARCH_MILBEAUT || COMPILE_TEST
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depends on OF
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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Say yes here to support the Socionext Milbeaut
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XDMAC device.
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config MMP_PDMA
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bool "MMP PDMA support"
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depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST
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@ -46,6 +46,7 @@ obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o
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obj-$(CONFIG_K3_DMA) += k3dma.o
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obj-$(CONFIG_LPC18XX_DMAMUX) += lpc18xx-dmamux.o
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obj-$(CONFIG_MILBEAUT_HDMAC) += milbeaut-hdmac.o
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obj-$(CONFIG_MILBEAUT_XDMAC) += milbeaut-xdmac.o
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obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
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obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
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obj-$(CONFIG_MOXART_DMA) += moxart-dma.o
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@ -0,0 +1,418 @@
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// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (C) 2019 Linaro Ltd.
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// Copyright (C) 2019 Socionext Inc.
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#include <linux/bits.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/of_dma.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/bitfield.h>
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#include "virt-dma.h"
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/* global register */
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#define M10V_XDACS 0x00
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/* channel local register */
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#define M10V_XDTBC 0x10
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#define M10V_XDSSA 0x14
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#define M10V_XDDSA 0x18
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#define M10V_XDSAC 0x1C
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#define M10V_XDDAC 0x20
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#define M10V_XDDCC 0x24
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#define M10V_XDDES 0x28
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#define M10V_XDDPC 0x2C
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#define M10V_XDDSD 0x30
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#define M10V_XDACS_XE BIT(28)
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#define M10V_DEFBS 0x3
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#define M10V_DEFBL 0xf
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#define M10V_XDSAC_SBS GENMASK(17, 16)
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#define M10V_XDSAC_SBL GENMASK(11, 8)
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#define M10V_XDDAC_DBS GENMASK(17, 16)
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#define M10V_XDDAC_DBL GENMASK(11, 8)
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#define M10V_XDDES_CE BIT(28)
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#define M10V_XDDES_SE BIT(24)
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#define M10V_XDDES_SA BIT(15)
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#define M10V_XDDES_TF GENMASK(23, 20)
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#define M10V_XDDES_EI BIT(1)
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#define M10V_XDDES_TI BIT(0)
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#define M10V_XDDSD_IS_MASK GENMASK(3, 0)
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#define M10V_XDDSD_IS_NORMAL 0x8
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#define MLB_XDMAC_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
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BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
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struct milbeaut_xdmac_desc {
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struct virt_dma_desc vd;
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size_t len;
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dma_addr_t src;
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dma_addr_t dst;
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};
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struct milbeaut_xdmac_chan {
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struct virt_dma_chan vc;
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struct milbeaut_xdmac_desc *md;
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void __iomem *reg_ch_base;
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};
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struct milbeaut_xdmac_device {
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struct dma_device ddev;
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void __iomem *reg_base;
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struct milbeaut_xdmac_chan channels[0];
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};
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static struct milbeaut_xdmac_chan *
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to_milbeaut_xdmac_chan(struct virt_dma_chan *vc)
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{
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return container_of(vc, struct milbeaut_xdmac_chan, vc);
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}
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static struct milbeaut_xdmac_desc *
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to_milbeaut_xdmac_desc(struct virt_dma_desc *vd)
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{
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return container_of(vd, struct milbeaut_xdmac_desc, vd);
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}
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/* mc->vc.lock must be held by caller */
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static struct milbeaut_xdmac_desc *
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milbeaut_xdmac_next_desc(struct milbeaut_xdmac_chan *mc)
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{
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struct virt_dma_desc *vd;
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vd = vchan_next_desc(&mc->vc);
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if (!vd) {
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mc->md = NULL;
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return NULL;
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}
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list_del(&vd->node);
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mc->md = to_milbeaut_xdmac_desc(vd);
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return mc->md;
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}
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/* mc->vc.lock must be held by caller */
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static void milbeaut_chan_start(struct milbeaut_xdmac_chan *mc,
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struct milbeaut_xdmac_desc *md)
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{
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u32 val;
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/* Setup the channel */
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val = md->len - 1;
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writel_relaxed(val, mc->reg_ch_base + M10V_XDTBC);
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val = md->src;
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writel_relaxed(val, mc->reg_ch_base + M10V_XDSSA);
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val = md->dst;
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writel_relaxed(val, mc->reg_ch_base + M10V_XDDSA);
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val = readl_relaxed(mc->reg_ch_base + M10V_XDSAC);
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val &= ~(M10V_XDSAC_SBS | M10V_XDSAC_SBL);
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val |= FIELD_PREP(M10V_XDSAC_SBS, M10V_DEFBS) |
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FIELD_PREP(M10V_XDSAC_SBL, M10V_DEFBL);
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writel_relaxed(val, mc->reg_ch_base + M10V_XDSAC);
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val = readl_relaxed(mc->reg_ch_base + M10V_XDDAC);
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val &= ~(M10V_XDDAC_DBS | M10V_XDDAC_DBL);
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val |= FIELD_PREP(M10V_XDDAC_DBS, M10V_DEFBS) |
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FIELD_PREP(M10V_XDDAC_DBL, M10V_DEFBL);
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writel_relaxed(val, mc->reg_ch_base + M10V_XDDAC);
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/* Start the channel */
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val = readl_relaxed(mc->reg_ch_base + M10V_XDDES);
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val &= ~(M10V_XDDES_CE | M10V_XDDES_SE | M10V_XDDES_TF |
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M10V_XDDES_EI | M10V_XDDES_TI);
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val |= FIELD_PREP(M10V_XDDES_CE, 1) | FIELD_PREP(M10V_XDDES_SE, 1) |
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FIELD_PREP(M10V_XDDES_TF, 1) | FIELD_PREP(M10V_XDDES_EI, 1) |
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FIELD_PREP(M10V_XDDES_TI, 1);
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writel_relaxed(val, mc->reg_ch_base + M10V_XDDES);
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}
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/* mc->vc.lock must be held by caller */
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static void milbeaut_xdmac_start(struct milbeaut_xdmac_chan *mc)
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{
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struct milbeaut_xdmac_desc *md;
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md = milbeaut_xdmac_next_desc(mc);
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if (md)
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milbeaut_chan_start(mc, md);
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}
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static irqreturn_t milbeaut_xdmac_interrupt(int irq, void *dev_id)
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{
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struct milbeaut_xdmac_chan *mc = dev_id;
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struct milbeaut_xdmac_desc *md;
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&mc->vc.lock, flags);
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/* Ack and Stop */
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val = FIELD_PREP(M10V_XDDSD_IS_MASK, 0x0);
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writel_relaxed(val, mc->reg_ch_base + M10V_XDDSD);
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md = mc->md;
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if (!md)
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goto out;
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vchan_cookie_complete(&md->vd);
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milbeaut_xdmac_start(mc);
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out:
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spin_unlock_irqrestore(&mc->vc.lock, flags);
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return IRQ_HANDLED;
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}
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static void milbeaut_xdmac_free_chan_resources(struct dma_chan *chan)
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{
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vchan_free_chan_resources(to_virt_chan(chan));
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}
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static struct dma_async_tx_descriptor *
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milbeaut_xdmac_prep_memcpy(struct dma_chan *chan, dma_addr_t dst,
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dma_addr_t src, size_t len, unsigned long flags)
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{
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struct virt_dma_chan *vc = to_virt_chan(chan);
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struct milbeaut_xdmac_desc *md;
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md = kzalloc(sizeof(*md), GFP_NOWAIT);
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if (!md)
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return NULL;
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md->len = len;
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md->src = src;
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md->dst = dst;
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return vchan_tx_prep(vc, &md->vd, flags);
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}
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static int milbeaut_xdmac_terminate_all(struct dma_chan *chan)
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{
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struct virt_dma_chan *vc = to_virt_chan(chan);
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struct milbeaut_xdmac_chan *mc = to_milbeaut_xdmac_chan(vc);
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unsigned long flags;
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u32 val;
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LIST_HEAD(head);
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spin_lock_irqsave(&vc->lock, flags);
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/* Halt the channel */
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val = readl(mc->reg_ch_base + M10V_XDDES);
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val &= ~M10V_XDDES_CE;
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val |= FIELD_PREP(M10V_XDDES_CE, 0);
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writel(val, mc->reg_ch_base + M10V_XDDES);
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if (mc->md) {
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vchan_terminate_vdesc(&mc->md->vd);
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mc->md = NULL;
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}
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vchan_get_all_descriptors(vc, &head);
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spin_unlock_irqrestore(&vc->lock, flags);
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vchan_dma_desc_free_list(vc, &head);
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return 0;
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}
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static void milbeaut_xdmac_synchronize(struct dma_chan *chan)
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{
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vchan_synchronize(to_virt_chan(chan));
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}
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static void milbeaut_xdmac_issue_pending(struct dma_chan *chan)
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{
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struct virt_dma_chan *vc = to_virt_chan(chan);
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struct milbeaut_xdmac_chan *mc = to_milbeaut_xdmac_chan(vc);
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unsigned long flags;
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spin_lock_irqsave(&vc->lock, flags);
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if (vchan_issue_pending(vc) && !mc->md)
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milbeaut_xdmac_start(mc);
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spin_unlock_irqrestore(&vc->lock, flags);
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}
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static void milbeaut_xdmac_desc_free(struct virt_dma_desc *vd)
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{
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kfree(to_milbeaut_xdmac_desc(vd));
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}
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static int milbeaut_xdmac_chan_init(struct platform_device *pdev,
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struct milbeaut_xdmac_device *mdev,
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int chan_id)
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{
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struct device *dev = &pdev->dev;
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struct milbeaut_xdmac_chan *mc = &mdev->channels[chan_id];
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char *irq_name;
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int irq, ret;
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irq = platform_get_irq(pdev, chan_id);
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if (irq < 0) {
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dev_err(&pdev->dev, "failed to get IRQ number for ch%d\n",
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chan_id);
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return irq;
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}
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irq_name = devm_kasprintf(dev, GFP_KERNEL, "milbeaut-xdmac-%d",
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chan_id);
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if (!irq_name)
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return -ENOMEM;
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ret = devm_request_irq(dev, irq, milbeaut_xdmac_interrupt,
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IRQF_SHARED, irq_name, mc);
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if (ret)
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return ret;
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mc->reg_ch_base = mdev->reg_base + chan_id * 0x30;
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mc->vc.desc_free = milbeaut_xdmac_desc_free;
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vchan_init(&mc->vc, &mdev->ddev);
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return 0;
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}
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static void enable_xdmac(struct milbeaut_xdmac_device *mdev)
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{
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unsigned int val;
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val = readl(mdev->reg_base + M10V_XDACS);
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val |= M10V_XDACS_XE;
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writel(val, mdev->reg_base + M10V_XDACS);
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}
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static void disable_xdmac(struct milbeaut_xdmac_device *mdev)
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{
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unsigned int val;
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val = readl(mdev->reg_base + M10V_XDACS);
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val &= ~M10V_XDACS_XE;
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writel(val, mdev->reg_base + M10V_XDACS);
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}
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static int milbeaut_xdmac_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct milbeaut_xdmac_device *mdev;
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struct dma_device *ddev;
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int nr_chans, ret, i;
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nr_chans = platform_irq_count(pdev);
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if (nr_chans < 0)
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return nr_chans;
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mdev = devm_kzalloc(dev, struct_size(mdev, channels, nr_chans),
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GFP_KERNEL);
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if (!mdev)
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return -ENOMEM;
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mdev->reg_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(mdev->reg_base))
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return PTR_ERR(mdev->reg_base);
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ddev = &mdev->ddev;
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ddev->dev = dev;
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dma_cap_set(DMA_MEMCPY, ddev->cap_mask);
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ddev->src_addr_widths = MLB_XDMAC_BUSWIDTHS;
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ddev->dst_addr_widths = MLB_XDMAC_BUSWIDTHS;
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ddev->device_free_chan_resources = milbeaut_xdmac_free_chan_resources;
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ddev->device_prep_dma_memcpy = milbeaut_xdmac_prep_memcpy;
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ddev->device_terminate_all = milbeaut_xdmac_terminate_all;
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ddev->device_synchronize = milbeaut_xdmac_synchronize;
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ddev->device_tx_status = dma_cookie_status;
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ddev->device_issue_pending = milbeaut_xdmac_issue_pending;
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INIT_LIST_HEAD(&ddev->channels);
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for (i = 0; i < nr_chans; i++) {
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ret = milbeaut_xdmac_chan_init(pdev, mdev, i);
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if (ret)
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return ret;
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}
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enable_xdmac(mdev);
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ret = dma_async_device_register(ddev);
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if (ret)
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return ret;
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ret = of_dma_controller_register(dev->of_node,
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of_dma_simple_xlate, mdev);
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if (ret)
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goto unregister_dmac;
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platform_set_drvdata(pdev, mdev);
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return 0;
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unregister_dmac:
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dma_async_device_unregister(ddev);
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return ret;
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}
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static int milbeaut_xdmac_remove(struct platform_device *pdev)
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{
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struct milbeaut_xdmac_device *mdev = platform_get_drvdata(pdev);
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struct dma_chan *chan;
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int ret;
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/*
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* Before reaching here, almost all descriptors have been freed by the
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* ->device_free_chan_resources() hook. However, each channel might
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* be still holding one descriptor that was on-flight at that moment.
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* Terminate it to make sure this hardware is no longer running. Then,
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* free the channel resources once again to avoid memory leak.
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*/
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list_for_each_entry(chan, &mdev->ddev.channels, device_node) {
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ret = dmaengine_terminate_sync(chan);
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if (ret)
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return ret;
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milbeaut_xdmac_free_chan_resources(chan);
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}
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of_dma_controller_free(pdev->dev.of_node);
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dma_async_device_unregister(&mdev->ddev);
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disable_xdmac(mdev);
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return 0;
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}
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static const struct of_device_id milbeaut_xdmac_match[] = {
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{ .compatible = "socionext,milbeaut-m10v-xdmac" },
|
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{ /* sentinel */ }
|
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};
|
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MODULE_DEVICE_TABLE(of, milbeaut_xdmac_match);
|
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static struct platform_driver milbeaut_xdmac_driver = {
|
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.probe = milbeaut_xdmac_probe,
|
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.remove = milbeaut_xdmac_remove,
|
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.driver = {
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.name = "milbeaut-m10v-xdmac",
|
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.of_match_table = milbeaut_xdmac_match,
|
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},
|
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};
|
||||
module_platform_driver(milbeaut_xdmac_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Milbeaut XDMAC DmaEngine driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
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