Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux
This series adds some HW bits and definitions for mlx5 driver, to be used by downstream features in both rdma and netdev branches. * 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux: net/mlx5: HW bit for goto chain offload support net/mlx5: Expose link speed directly net/mlx5: Introduce TLS and IPSec objects enums net/mlx5: Introduce egress acl forward-to-vport capability net/mlx5: Expose raw packet pacing APIs net/mlx5e: Replace zero-length array with flexible-array member net/mlx5: fix spelling mistake "reserverd" -> "reserved" Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
This commit is contained in:
Коммит
a70ed9d8ec
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@ -204,7 +204,7 @@ struct mlx5e_tx_wqe {
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struct mlx5e_rx_wqe_ll {
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struct mlx5_wqe_srq_next_seg next;
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struct mlx5_wqe_data_seg data[0];
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struct mlx5_wqe_data_seg data[];
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};
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struct mlx5e_rx_wqe_cyc {
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@ -57,7 +57,7 @@ struct mlx5_fpga_ipsec_cmd_context {
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struct completion complete;
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struct mlx5_fpga_device *dev;
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struct list_head list; /* Item in pending_cmds */
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u8 command[0];
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u8 command[];
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};
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struct mlx5_fpga_esp_xfrm;
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@ -470,7 +470,7 @@ struct mlx5_fc_bulk {
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u32 base_id;
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int bulk_len;
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unsigned long *bitmask;
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struct mlx5_fc fcs[0];
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struct mlx5_fc fcs[];
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};
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static void mlx5_fc_init(struct mlx5_fc *counter, struct mlx5_fc_bulk *bulk,
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@ -56,7 +56,7 @@ struct mlx5i_priv {
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u32 qkey;
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u16 pkey_index;
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struct mlx5i_pkey_qpn_ht *qpn_htbl;
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char *mlx5e_priv[0];
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char *mlx5e_priv[];
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};
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int mlx5i_create_tis(struct mlx5_core_dev *mdev, u32 underlay_qpn, u32 *tisn);
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@ -107,7 +107,7 @@ struct mlx5i_tx_wqe {
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struct mlx5_wqe_datagram_seg datagram;
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struct mlx5_wqe_eth_pad pad;
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struct mlx5_wqe_eth_seg eth;
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struct mlx5_wqe_data_seg data[0];
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struct mlx5_wqe_data_seg data[];
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};
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static inline void mlx5i_sq_fetch_wqe(struct mlx5e_txqsq *sq,
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@ -42,7 +42,7 @@ int mlx5_create_encryption_key(struct mlx5_core_dev *mdev,
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MLX5_SET(encryption_key_obj, obj, key_size, general_obj_key_size);
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MLX5_SET(encryption_key_obj, obj, key_type,
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MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK);
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MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS);
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MLX5_SET(general_obj_in_cmd_hdr, in, opcode,
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MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
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MLX5_SET(general_obj_in_cmd_hdr, in, obj_type,
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@ -101,22 +101,39 @@ int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
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return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
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}
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static bool mlx5_rl_are_equal_raw(struct mlx5_rl_entry *entry, void *rl_in,
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u16 uid)
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{
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return (!memcmp(entry->rl_raw, rl_in, sizeof(entry->rl_raw)) &&
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entry->uid == uid);
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}
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/* Finds an entry where we can register the given rate
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* If the rate already exists, return the entry where it is registered,
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* otherwise return the first available entry.
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* If the table is full, return NULL
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*/
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static struct mlx5_rl_entry *find_rl_entry(struct mlx5_rl_table *table,
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struct mlx5_rate_limit *rl)
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void *rl_in, u16 uid, bool dedicated)
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{
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struct mlx5_rl_entry *ret_entry = NULL;
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bool empty_found = false;
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int i;
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for (i = 0; i < table->max_size; i++) {
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if (mlx5_rl_are_equal(&table->rl_entry[i].rl, rl))
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return &table->rl_entry[i];
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if (!empty_found && !table->rl_entry[i].rl.rate) {
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if (dedicated) {
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if (!table->rl_entry[i].refcount)
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return &table->rl_entry[i];
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continue;
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}
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if (table->rl_entry[i].refcount) {
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if (table->rl_entry[i].dedicated)
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continue;
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if (mlx5_rl_are_equal_raw(&table->rl_entry[i], rl_in,
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uid))
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return &table->rl_entry[i];
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} else if (!empty_found) {
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empty_found = true;
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ret_entry = &table->rl_entry[i];
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}
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@ -126,18 +143,19 @@ static struct mlx5_rl_entry *find_rl_entry(struct mlx5_rl_table *table,
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}
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static int mlx5_set_pp_rate_limit_cmd(struct mlx5_core_dev *dev,
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u16 index,
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struct mlx5_rate_limit *rl)
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struct mlx5_rl_entry *entry, bool set)
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{
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u32 in[MLX5_ST_SZ_DW(set_pp_rate_limit_in)] = {0};
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u32 out[MLX5_ST_SZ_DW(set_pp_rate_limit_out)] = {0};
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u32 in[MLX5_ST_SZ_DW(set_pp_rate_limit_in)] = {};
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u32 out[MLX5_ST_SZ_DW(set_pp_rate_limit_out)] = {};
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void *pp_context;
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pp_context = MLX5_ADDR_OF(set_pp_rate_limit_in, in, ctx);
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MLX5_SET(set_pp_rate_limit_in, in, opcode,
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MLX5_CMD_OP_SET_PP_RATE_LIMIT);
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MLX5_SET(set_pp_rate_limit_in, in, rate_limit_index, index);
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MLX5_SET(set_pp_rate_limit_in, in, rate_limit, rl->rate);
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MLX5_SET(set_pp_rate_limit_in, in, burst_upper_bound, rl->max_burst_sz);
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MLX5_SET(set_pp_rate_limit_in, in, typical_packet_size, rl->typical_pkt_sz);
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MLX5_SET(set_pp_rate_limit_in, in, uid, entry->uid);
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MLX5_SET(set_pp_rate_limit_in, in, rate_limit_index, entry->index);
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if (set)
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memcpy(pp_context, entry->rl_raw, sizeof(entry->rl_raw));
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return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
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}
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@ -158,23 +176,25 @@ bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
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}
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EXPORT_SYMBOL(mlx5_rl_are_equal);
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int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
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struct mlx5_rate_limit *rl)
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int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
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bool dedicated_entry, u16 *index)
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{
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struct mlx5_rl_table *table = &dev->priv.rl_table;
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struct mlx5_rl_entry *entry;
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int err = 0;
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u32 rate;
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rate = MLX5_GET(set_pp_rate_limit_context, rl_in, rate_limit);
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mutex_lock(&table->rl_lock);
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if (!rl->rate || !mlx5_rl_is_in_range(dev, rl->rate)) {
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if (!rate || !mlx5_rl_is_in_range(dev, rate)) {
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mlx5_core_err(dev, "Invalid rate: %u, should be %u to %u\n",
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rl->rate, table->min_rate, table->max_rate);
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rate, table->min_rate, table->max_rate);
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err = -EINVAL;
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goto out;
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}
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entry = find_rl_entry(table, rl);
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entry = find_rl_entry(table, rl_in, uid, dedicated_entry);
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if (!entry) {
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mlx5_core_err(dev, "Max number of %u rates reached\n",
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table->max_size);
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@ -185,16 +205,24 @@ int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
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/* rate already configured */
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entry->refcount++;
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} else {
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memcpy(entry->rl_raw, rl_in, sizeof(entry->rl_raw));
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entry->uid = uid;
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/* new rate limit */
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err = mlx5_set_pp_rate_limit_cmd(dev, entry->index, rl);
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err = mlx5_set_pp_rate_limit_cmd(dev, entry, true);
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if (err) {
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mlx5_core_err(dev, "Failed configuring rate limit(err %d): rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
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err, rl->rate, rl->max_burst_sz,
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rl->typical_pkt_sz);
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mlx5_core_err(
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dev,
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"Failed configuring rate limit(err %d): rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
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err, rate,
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MLX5_GET(set_pp_rate_limit_context, rl_in,
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burst_upper_bound),
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MLX5_GET(set_pp_rate_limit_context, rl_in,
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typical_packet_size));
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goto out;
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}
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entry->rl = *rl;
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entry->refcount = 1;
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entry->dedicated = dedicated_entry;
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}
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*index = entry->index;
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@ -202,20 +230,61 @@ out:
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mutex_unlock(&table->rl_lock);
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return err;
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}
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EXPORT_SYMBOL(mlx5_rl_add_rate_raw);
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void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index)
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{
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struct mlx5_rl_table *table = &dev->priv.rl_table;
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struct mlx5_rl_entry *entry;
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mutex_lock(&table->rl_lock);
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entry = &table->rl_entry[index - 1];
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entry->refcount--;
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if (!entry->refcount)
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/* need to remove rate */
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mlx5_set_pp_rate_limit_cmd(dev, entry, false);
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mutex_unlock(&table->rl_lock);
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}
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EXPORT_SYMBOL(mlx5_rl_remove_rate_raw);
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int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
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struct mlx5_rate_limit *rl)
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{
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u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)] = {};
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MLX5_SET(set_pp_rate_limit_context, rl_raw, rate_limit, rl->rate);
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MLX5_SET(set_pp_rate_limit_context, rl_raw, burst_upper_bound,
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rl->max_burst_sz);
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MLX5_SET(set_pp_rate_limit_context, rl_raw, typical_packet_size,
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rl->typical_pkt_sz);
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return mlx5_rl_add_rate_raw(dev, rl_raw,
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MLX5_CAP_QOS(dev, packet_pacing_uid) ?
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MLX5_SHARED_RESOURCE_UID : 0,
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false, index);
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}
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EXPORT_SYMBOL(mlx5_rl_add_rate);
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void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl)
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{
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u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)] = {};
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struct mlx5_rl_table *table = &dev->priv.rl_table;
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struct mlx5_rl_entry *entry = NULL;
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struct mlx5_rate_limit reset_rl = {0};
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/* 0 is a reserved value for unlimited rate */
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if (rl->rate == 0)
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return;
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MLX5_SET(set_pp_rate_limit_context, rl_raw, rate_limit, rl->rate);
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MLX5_SET(set_pp_rate_limit_context, rl_raw, burst_upper_bound,
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rl->max_burst_sz);
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MLX5_SET(set_pp_rate_limit_context, rl_raw, typical_packet_size,
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rl->typical_pkt_sz);
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mutex_lock(&table->rl_lock);
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entry = find_rl_entry(table, rl);
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entry = find_rl_entry(table, rl_raw,
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MLX5_CAP_QOS(dev, packet_pacing_uid) ?
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MLX5_SHARED_RESOURCE_UID : 0, false);
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if (!entry || !entry->refcount) {
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mlx5_core_warn(dev, "Rate %u, max_burst_sz %u typical_pkt_sz %u are not configured\n",
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rl->rate, rl->max_burst_sz, rl->typical_pkt_sz);
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@ -223,11 +292,9 @@ void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl)
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}
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entry->refcount--;
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if (!entry->refcount) {
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if (!entry->refcount)
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/* need to remove rate */
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mlx5_set_pp_rate_limit_cmd(dev, entry->index, &reset_rl);
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entry->rl = reset_rl;
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}
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mlx5_set_pp_rate_limit_cmd(dev, entry, false);
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out:
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mutex_unlock(&table->rl_lock);
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@ -273,14 +340,13 @@ int mlx5_init_rl_table(struct mlx5_core_dev *dev)
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void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev)
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{
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struct mlx5_rl_table *table = &dev->priv.rl_table;
|
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struct mlx5_rate_limit rl = {0};
|
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int i;
|
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|
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/* Clear all configured rates */
|
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for (i = 0; i < table->max_size; i++)
|
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if (table->rl_entry[i].rl.rate)
|
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mlx5_set_pp_rate_limit_cmd(dev, table->rl_entry[i].index,
|
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&rl);
|
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if (table->rl_entry[i].refcount)
|
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mlx5_set_pp_rate_limit_cmd(dev, &table->rl_entry[i],
|
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false);
|
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|
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kfree(dev->priv.rl_table.rl_entry);
|
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}
|
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|
|
|
@ -518,9 +518,11 @@ struct mlx5_rate_limit {
|
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};
|
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|
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struct mlx5_rl_entry {
|
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struct mlx5_rate_limit rl;
|
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u16 index;
|
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u16 refcount;
|
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u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
|
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u16 index;
|
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u64 refcount;
|
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u16 uid;
|
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u8 dedicated : 1;
|
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};
|
||||
|
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struct mlx5_rl_table {
|
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|
@ -1008,6 +1010,9 @@ int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
|
|||
struct mlx5_rate_limit *rl);
|
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void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
|
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bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
|
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int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
|
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bool dedicated_entry, u16 *index);
|
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void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
|
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bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
|
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struct mlx5_rate_limit *rl_1);
|
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int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
|
||||
|
|
|
@ -414,7 +414,8 @@ struct mlx5_ifc_flow_table_prop_layout_bits {
|
|||
u8 reserved_at_16[0x1];
|
||||
u8 table_miss_action_domain[0x1];
|
||||
u8 termination_table[0x1];
|
||||
u8 reserved_at_19[0x7];
|
||||
u8 reformat_and_fwd_to_table[0x1];
|
||||
u8 reserved_at_1a[0x6];
|
||||
u8 reserved_at_20[0x2];
|
||||
u8 log_max_ft_size[0x6];
|
||||
u8 log_max_modify_header_context[0x8];
|
||||
|
@ -741,7 +742,7 @@ struct mlx5_ifc_flow_table_eswitch_cap_bits {
|
|||
u8 flow_source[0x1];
|
||||
u8 reserved_at_18[0x2];
|
||||
u8 multi_fdb_encap[0x1];
|
||||
u8 reserved_at_1b[0x1];
|
||||
u8 egress_acl_forward_to_vport[0x1];
|
||||
u8 fdb_multi_path_to_table[0x1];
|
||||
u8 reserved_at_1d[0x3];
|
||||
|
||||
|
@ -813,7 +814,9 @@ struct mlx5_ifc_qos_cap_bits {
|
|||
u8 reserved_at_4[0x1];
|
||||
u8 packet_pacing_burst_bound[0x1];
|
||||
u8 packet_pacing_typical_size[0x1];
|
||||
u8 reserved_at_7[0x19];
|
||||
u8 reserved_at_7[0x4];
|
||||
u8 packet_pacing_uid[0x1];
|
||||
u8 reserved_at_c[0x14];
|
||||
|
||||
u8 reserved_at_20[0x20];
|
||||
|
||||
|
@ -8265,9 +8268,20 @@ struct mlx5_ifc_set_pp_rate_limit_out_bits {
|
|||
u8 reserved_at_40[0x40];
|
||||
};
|
||||
|
||||
struct mlx5_ifc_set_pp_rate_limit_context_bits {
|
||||
u8 rate_limit[0x20];
|
||||
|
||||
u8 burst_upper_bound[0x20];
|
||||
|
||||
u8 reserved_at_40[0x10];
|
||||
u8 typical_packet_size[0x10];
|
||||
|
||||
u8 reserved_at_60[0x120];
|
||||
};
|
||||
|
||||
struct mlx5_ifc_set_pp_rate_limit_in_bits {
|
||||
u8 opcode[0x10];
|
||||
u8 reserved_at_10[0x10];
|
||||
u8 uid[0x10];
|
||||
|
||||
u8 reserved_at_20[0x10];
|
||||
u8 op_mod[0x10];
|
||||
|
@ -8277,14 +8291,7 @@ struct mlx5_ifc_set_pp_rate_limit_in_bits {
|
|||
|
||||
u8 reserved_at_60[0x20];
|
||||
|
||||
u8 rate_limit[0x20];
|
||||
|
||||
u8 burst_upper_bound[0x20];
|
||||
|
||||
u8 reserved_at_c0[0x10];
|
||||
u8 typical_packet_size[0x10];
|
||||
|
||||
u8 reserved_at_e0[0x120];
|
||||
struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
|
||||
};
|
||||
|
||||
struct mlx5_ifc_access_register_out_bits {
|
||||
|
@ -8420,7 +8427,8 @@ struct mlx5_ifc_ptys_reg_bits {
|
|||
u8 proto_mask[0x3];
|
||||
|
||||
u8 an_status[0x4];
|
||||
u8 reserved_at_24[0x1c];
|
||||
u8 reserved_at_24[0xc];
|
||||
u8 data_rate_oper[0x10];
|
||||
|
||||
u8 ext_eth_proto_capability[0x20];
|
||||
|
||||
|
@ -10486,7 +10494,8 @@ enum {
|
|||
};
|
||||
|
||||
enum {
|
||||
MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
|
||||
MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
|
||||
MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
|
||||
};
|
||||
|
||||
struct mlx5_ifc_tls_static_params_bits {
|
||||
|
|
|
@ -608,7 +608,7 @@ struct mlx5_ifc_tls_cmd_bits {
|
|||
struct mlx5_ifc_tls_resp_bits {
|
||||
u8 syndrome[0x20];
|
||||
u8 stream_id[0x20];
|
||||
u8 reserverd[0x40];
|
||||
u8 reserved[0x40];
|
||||
};
|
||||
|
||||
#define MLX5_TLS_COMMAND_SIZE (0x100)
|
||||
|
|
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