crypto: cavium/nitrox - Add support for loading asymmetric crypto firmware
This patch adds support to load Asymmetric crypto firmware on AE cores of CNN55XX device. Firmware is stored on UCD block 2 and all available AE cores are tagged to group 0. Signed-off-by: Phani Kiran Hemadri <phemadri@marvell.com> Reviewed-by: Srikanth Jampala <jsrikanth@marvell.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Родитель
a7c2647034
Коммит
a7268c4d42
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@ -40,9 +40,77 @@
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#define EMU_FUSE_MAPX(_i) (0x1402708 + ((_i) * 0x40000))
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/* UCD registers */
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#define UCD_SE_EID_UCODE_BLOCK_NUMX(_i) (0x12C0000 + ((_i) * 0x1000))
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#define UCD_AE_EID_UCODE_BLOCK_NUMX(_i) (0x12C0008 + ((_i) * 0x800))
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#define UCD_UCODE_LOAD_BLOCK_NUM 0x12C0010
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#define UCD_UCODE_LOAD_IDX_DATAX(_i) (0x12C0018 + ((_i) * 0x20))
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#define UCD_SE_EID_UCODE_BLOCK_NUMX(_i) (0x12C0000 + ((_i) * 0x1000))
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#define UCD_SE_CNTX(_i) (0x12C0040 + ((_i) * 0x1000))
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#define UCD_AE_CNTX(_i) (0x12C0048 + ((_i) * 0x800))
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/* AQM registers */
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#define AQM_CTL 0x1300000
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#define AQM_INT 0x1300008
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#define AQM_DBELL_OVF_LO 0x1300010
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#define AQM_DBELL_OVF_HI 0x1300018
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#define AQM_DBELL_OVF_LO_W1S 0x1300020
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#define AQM_DBELL_OVF_LO_ENA_W1C 0x1300028
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#define AQM_DBELL_OVF_LO_ENA_W1S 0x1300030
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#define AQM_DBELL_OVF_HI_W1S 0x1300038
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#define AQM_DBELL_OVF_HI_ENA_W1C 0x1300040
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#define AQM_DBELL_OVF_HI_ENA_W1S 0x1300048
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#define AQM_DMA_RD_ERR_LO 0x1300050
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#define AQM_DMA_RD_ERR_HI 0x1300058
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#define AQM_DMA_RD_ERR_LO_W1S 0x1300060
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#define AQM_DMA_RD_ERR_LO_ENA_W1C 0x1300068
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#define AQM_DMA_RD_ERR_LO_ENA_W1S 0x1300070
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#define AQM_DMA_RD_ERR_HI_W1S 0x1300078
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#define AQM_DMA_RD_ERR_HI_ENA_W1C 0x1300080
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#define AQM_DMA_RD_ERR_HI_ENA_W1S 0x1300088
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#define AQM_EXEC_NA_LO 0x1300090
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#define AQM_EXEC_NA_HI 0x1300098
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#define AQM_EXEC_NA_LO_W1S 0x13000A0
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#define AQM_EXEC_NA_LO_ENA_W1C 0x13000A8
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#define AQM_EXEC_NA_LO_ENA_W1S 0x13000B0
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#define AQM_EXEC_NA_HI_W1S 0x13000B8
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#define AQM_EXEC_NA_HI_ENA_W1C 0x13000C0
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#define AQM_EXEC_NA_HI_ENA_W1S 0x13000C8
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#define AQM_EXEC_ERR_LO 0x13000D0
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#define AQM_EXEC_ERR_HI 0x13000D8
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#define AQM_EXEC_ERR_LO_W1S 0x13000E0
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#define AQM_EXEC_ERR_LO_ENA_W1C 0x13000E8
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#define AQM_EXEC_ERR_LO_ENA_W1S 0x13000F0
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#define AQM_EXEC_ERR_HI_W1S 0x13000F8
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#define AQM_EXEC_ERR_HI_ENA_W1C 0x1300100
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#define AQM_EXEC_ERR_HI_ENA_W1S 0x1300108
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#define AQM_ECC_INT 0x1300110
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#define AQM_ECC_INT_W1S 0x1300118
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#define AQM_ECC_INT_ENA_W1C 0x1300120
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#define AQM_ECC_INT_ENA_W1S 0x1300128
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#define AQM_ECC_CTL 0x1300130
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#define AQM_BIST_STATUS 0x1300138
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#define AQM_CMD_INF_THRX(x) (0x1300400 + ((x) * 0x8))
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#define AQM_CMD_INFX(x) (0x1300800 + ((x) * 0x8))
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#define AQM_GRP_EXECMSK_LOX(x) (0x1300C00 + ((x) * 0x10))
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#define AQM_GRP_EXECMSK_HIX(x) (0x1300C08 + ((x) * 0x10))
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#define AQM_ACTIVITY_STAT_LO 0x1300C80
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#define AQM_ACTIVITY_STAT_HI 0x1300C88
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#define AQM_Q_CMD_PROCX(x) (0x1301000 + ((x) * 0x8))
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#define AQM_PERF_CTL_LO 0x1301400
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#define AQM_PERF_CTL_HI 0x1301408
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#define AQM_PERF_CNT 0x1301410
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#define AQMQ_DRBLX(x) (0x20000 + ((x) * 0x40000))
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#define AQMQ_QSZX(x) (0x20008 + ((x) * 0x40000))
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#define AQMQ_BADRX(x) (0x20010 + ((x) * 0x40000))
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#define AQMQ_NXT_CMDX(x) (0x20018 + ((x) * 0x40000))
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#define AQMQ_CMD_CNTX(x) (0x20020 + ((x) * 0x40000))
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#define AQMQ_CMP_THRX(x) (0x20028 + ((x) * 0x40000))
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#define AQMQ_CMP_CNTX(x) (0x20030 + ((x) * 0x40000))
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#define AQMQ_TIM_LDX(x) (0x20038 + ((x) * 0x40000))
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#define AQMQ_TIMERX(x) (0x20040 + ((x) * 0x40000))
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#define AQMQ_ENX(x) (0x20048 + ((x) * 0x40000))
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#define AQMQ_ACTIVITY_STATX(x) (0x20050 + ((x) * 0x40000))
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#define AQM_VF_CMP_STATX(x) (0x28000 + ((x) * 0x40000))
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/* NPS core registers */
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#define NPS_CORE_GBL_VFCFG 0x1000000
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@ -134,6 +202,60 @@
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/* PEM registers */
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#define PEM0_INT 0x1080428
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/**
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* struct ucd_core_eid_ucode_block_num - Core Eid to Ucode Blk Mapping Registers
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* @ucode_len: Ucode length identifier 32KB or 64KB
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* @ucode_blk: Ucode Block Number
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*/
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union ucd_core_eid_ucode_block_num {
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u64 value;
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struct {
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#if (defined(__BIG_ENDIAN_BITFIELD))
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u64 raz_4_63 : 60;
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u64 ucode_len : 1;
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u64 ucode_blk : 3;
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#else
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u64 ucode_blk : 3;
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u64 ucode_len : 1;
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u64 raz_4_63 : 60;
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#endif
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};
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};
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/**
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* struct aqm_grp_execmsk_lo - Available AE engines for the group
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* @exec_0_to_39: AE engines 0 to 39 status
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*/
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union aqm_grp_execmsk_lo {
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u64 value;
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struct {
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#if (defined(__BIG_ENDIAN_BITFIELD))
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u64 raz_40_63 : 24;
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u64 exec_0_to_39 : 40;
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#else
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u64 exec_0_to_39 : 40;
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u64 raz_40_63 : 24;
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#endif
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};
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};
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/**
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* struct aqm_grp_execmsk_hi - Available AE engines for the group
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* @exec_40_to_79: AE engines 40 to 79 status
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*/
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union aqm_grp_execmsk_hi {
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u64 value;
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struct {
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#if (defined(__BIG_ENDIAN_BITFIELD))
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u64 raz_40_63 : 24;
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u64 exec_40_to_79 : 40;
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#else
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u64 exec_40_to_79 : 40;
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u64 raz_40_63 : 24;
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#endif
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};
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};
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/**
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* struct emu_fuse_map - EMU Fuse Map Registers
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* @ae_fuse: Fuse settings for AE 19..0
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@ -9,7 +9,8 @@ static int firmware_show(struct seq_file *s, void *v)
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{
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struct nitrox_device *ndev = s->private;
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seq_printf(s, "Version: %s\n", ndev->hw.fw_name);
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seq_printf(s, "Version: %s\n", ndev->hw.fw_name[0]);
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seq_printf(s, "Version: %s\n", ndev->hw.fw_name[1]);
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return 0;
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}
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@ -10,6 +10,8 @@
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#define VERSION_LEN 32
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/* Maximum queues in PF mode */
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#define MAX_PF_QUEUES 64
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/* Maximum UCD Blocks */
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#define CNN55XX_MAX_UCD_BLOCKS 8
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/**
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* struct nitrox_cmdq - NITROX command queue
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@ -74,7 +76,7 @@ struct nitrox_cmdq {
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*/
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struct nitrox_hw {
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char partname[IFNAMSIZ * 2];
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char fw_name[VERSION_LEN];
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char fw_name[CNN55XX_MAX_UCD_BLOCKS][VERSION_LEN];
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int freq;
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u16 vendor_id;
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@ -17,12 +17,17 @@
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#define CNN55XX_DEV_ID 0x12
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#define UCODE_HLEN 48
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#define SE_GROUP 0
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#define DEFAULT_SE_GROUP 0
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#define DEFAULT_AE_GROUP 0
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#define DRIVER_VERSION "1.1"
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#define DRIVER_VERSION "1.2"
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#define CNN55XX_UCD_BLOCK_SIZE 32768
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#define CNN55XX_MAX_UCODE_SIZE (CNN55XX_UCD_BLOCK_SIZE * 2)
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#define FW_DIR "cavium/"
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/* SE microcode */
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#define SE_FW FW_DIR "cnn55xx_se.fw"
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/* AE microcode */
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#define AE_FW FW_DIR "cnn55xx_ae.fw"
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static const char nitrox_driver_name[] = "CNN55XX";
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@ -72,10 +77,10 @@ struct ucode {
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/**
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* write_to_ucd_unit - Write Firmware to NITROX UCD unit
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*/
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static void write_to_ucd_unit(struct nitrox_device *ndev,
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struct ucode *ucode)
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static void write_to_ucd_unit(struct nitrox_device *ndev, u32 ucode_size,
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u64 *ucode_data, int block_num)
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{
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u32 code_size = be32_to_cpu(ucode->code_size) * 2;
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u32 code_size;
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u64 offset, data;
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int i = 0;
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@ -96,11 +101,12 @@ static void write_to_ucd_unit(struct nitrox_device *ndev,
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/* set the block number */
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offset = UCD_UCODE_LOAD_BLOCK_NUM;
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nitrox_write_csr(ndev, offset, 0);
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nitrox_write_csr(ndev, offset, block_num);
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code_size = ucode_size;
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code_size = roundup(code_size, 8);
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while (code_size) {
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data = ucode->code[i];
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data = ucode_data[i];
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/* write 8 bytes at a time */
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offset = UCD_UCODE_LOAD_IDX_DATAX(i);
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nitrox_write_csr(ndev, offset, data);
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@ -108,29 +114,23 @@ static void write_to_ucd_unit(struct nitrox_device *ndev,
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i++;
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}
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/* put all SE cores in group 0 */
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offset = POM_GRP_EXECMASKX(SE_GROUP);
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nitrox_write_csr(ndev, offset, (~0ULL));
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for (i = 0; i < ndev->hw.se_cores; i++) {
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/*
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* write block number and firware length
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* bit:<2:0> block number
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* bit:3 is set SE uses 32KB microcode
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* bit:3 is clear SE uses 64KB microcode
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*/
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offset = UCD_SE_EID_UCODE_BLOCK_NUMX(i);
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nitrox_write_csr(ndev, offset, 0x8);
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}
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usleep_range(300, 400);
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}
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static int nitrox_load_fw(struct nitrox_device *ndev, const char *fw_name)
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static int nitrox_load_fw(struct nitrox_device *ndev)
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{
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const struct firmware *fw;
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const char *fw_name;
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struct ucode *ucode;
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int ret;
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u64 *ucode_data;
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u64 offset;
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union ucd_core_eid_ucode_block_num core_2_eid_val;
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union aqm_grp_execmsk_lo aqm_grp_execmask_lo;
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union aqm_grp_execmsk_hi aqm_grp_execmask_hi;
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u32 ucode_size;
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int ret, i = 0;
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fw_name = SE_FW;
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dev_info(DEV(ndev), "Loading firmware \"%s\"\n", fw_name);
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ret = request_firmware(&fw, fw_name, DEV(ndev));
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@ -140,13 +140,101 @@ static int nitrox_load_fw(struct nitrox_device *ndev, const char *fw_name)
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}
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ucode = (struct ucode *)fw->data;
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/* copy the firmware version */
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memcpy(ndev->hw.fw_name, ucode->version, (VERSION_LEN - 2));
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ndev->hw.fw_name[VERSION_LEN - 1] = '\0';
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write_to_ucd_unit(ndev, ucode);
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ucode_size = be32_to_cpu(ucode->code_size) * 2;
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if (!ucode_size || ucode_size > CNN55XX_MAX_UCODE_SIZE) {
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dev_err(DEV(ndev), "Invalid ucode size: %u for firmware %s\n",
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ucode_size, fw_name);
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release_firmware(fw);
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return -EINVAL;
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}
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ucode_data = ucode->code;
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/* copy the firmware version */
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memcpy(&ndev->hw.fw_name[0][0], ucode->version, (VERSION_LEN - 2));
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ndev->hw.fw_name[0][VERSION_LEN - 1] = '\0';
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/* Load SE Firmware on UCD Block 0 */
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write_to_ucd_unit(ndev, ucode_size, ucode_data, 0);
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release_firmware(fw);
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/* put all SE cores in DEFAULT_SE_GROUP */
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offset = POM_GRP_EXECMASKX(DEFAULT_SE_GROUP);
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nitrox_write_csr(ndev, offset, (~0ULL));
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/* write block number and firmware length
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* bit:<2:0> block number
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* bit:3 is set SE uses 32KB microcode
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* bit:3 is clear SE uses 64KB microcode
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*/
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core_2_eid_val.value = 0ULL;
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core_2_eid_val.ucode_blk = 0;
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if (ucode_size <= CNN55XX_UCD_BLOCK_SIZE)
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core_2_eid_val.ucode_len = 1;
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else
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core_2_eid_val.ucode_len = 0;
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for (i = 0; i < ndev->hw.se_cores; i++) {
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offset = UCD_SE_EID_UCODE_BLOCK_NUMX(i);
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nitrox_write_csr(ndev, offset, core_2_eid_val.value);
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}
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fw_name = AE_FW;
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dev_info(DEV(ndev), "Loading firmware \"%s\"\n", fw_name);
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ret = request_firmware(&fw, fw_name, DEV(ndev));
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if (ret < 0) {
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dev_err(DEV(ndev), "failed to get firmware %s\n", fw_name);
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return ret;
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}
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ucode = (struct ucode *)fw->data;
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ucode_size = be32_to_cpu(ucode->code_size) * 2;
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if (!ucode_size || ucode_size > CNN55XX_MAX_UCODE_SIZE) {
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dev_err(DEV(ndev), "Invalid ucode size: %u for firmware %s\n",
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ucode_size, fw_name);
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release_firmware(fw);
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return -EINVAL;
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}
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ucode_data = ucode->code;
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/* copy the firmware version */
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memcpy(&ndev->hw.fw_name[1][0], ucode->version, (VERSION_LEN - 2));
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ndev->hw.fw_name[1][VERSION_LEN - 1] = '\0';
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/* Load AE Firmware on UCD Block 2 */
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write_to_ucd_unit(ndev, ucode_size, ucode_data, 2);
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release_firmware(fw);
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/* put all AE cores in DEFAULT_AE_GROUP */
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offset = AQM_GRP_EXECMSK_LOX(DEFAULT_AE_GROUP);
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aqm_grp_execmask_lo.exec_0_to_39 = 0xFFFFFFFFFFULL;
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nitrox_write_csr(ndev, offset, aqm_grp_execmask_lo.value);
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offset = AQM_GRP_EXECMSK_HIX(DEFAULT_AE_GROUP);
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aqm_grp_execmask_hi.exec_40_to_79 = 0xFFFFFFFFFFULL;
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nitrox_write_csr(ndev, offset, aqm_grp_execmask_hi.value);
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/* write block number and firmware length
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* bit:<2:0> block number
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* bit:3 is set SE uses 32KB microcode
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* bit:3 is clear SE uses 64KB microcode
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*/
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core_2_eid_val.value = 0ULL;
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core_2_eid_val.ucode_blk = 0;
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if (ucode_size <= CNN55XX_UCD_BLOCK_SIZE)
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core_2_eid_val.ucode_len = 1;
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else
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core_2_eid_val.ucode_len = 0;
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for (i = 0; i < ndev->hw.ae_cores; i++) {
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offset = UCD_AE_EID_UCODE_BLOCK_NUMX(i);
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nitrox_write_csr(ndev, offset, core_2_eid_val.value);
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}
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return 0;
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}
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@ -309,8 +397,8 @@ static int nitrox_pf_hw_init(struct nitrox_device *ndev)
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nitrox_config_lbc_unit(ndev);
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nitrox_config_rand_unit(ndev);
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/* load firmware on SE cores */
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err = nitrox_load_fw(ndev, SE_FW);
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/* load firmware on cores */
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err = nitrox_load_fw(ndev);
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if (err)
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return err;
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