drm/nva3/clk: For PLL clocks always make sure the PLL is not in use
Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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@ -305,8 +305,17 @@ prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx)
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const u32 src1 = 0x004160 + (clk * 4);
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const u32 ctrl = pll + 0;
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const u32 coef = pll + 4;
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u32 bypass;
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if (info->pll) {
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/* Always start from a non-PLL clock */
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bypass = nv_rd32(priv, ctrl) & 0x00000008;
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if (!bypass) {
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nv_mask(priv, src1, 0x00000101, 0x00000101);
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nv_mask(priv, ctrl, 0x00000008, 0x00000008);
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udelay(20);
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}
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nv_mask(priv, src0, 0x003f3141, 0x00000101 | info->clk);
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nv_wr32(priv, coef, info->pll);
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nv_mask(priv, ctrl, 0x00000015, 0x00000015);
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