ASoC: davinci-mcasp: Set rule constraints if implicit BCLK divider is used
Set rule constraints to allow only combinations of sample-rate, sample-format, and channels counts that can be played/captured with reasonable sample-rate accuracy. The logic with tdm-slots and serializers (=i2s data wires) goes like this: The first wire will take all channels up to number of tdm-slots, before following wires (if any) are used. If the first wire is used fully, the remaining wires share the same clocks and the divider can be calculated for the first wire. Also, takes the number of tdm-slots into account when implicitly selecting the BLCK divider. Signed-off-by: Jyri Sarha <jsarha@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Jyri Sarha
Mark Brown
Родитель
66e618857c
Коммит
a75a053f1e
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@ -27,6 +27,7 @@
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#include <linux/of_platform.h>
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#include <linux/of_device.h>
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#include <linux/platform_data/davinci_asp.h>
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#include <linux/math64.h>
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#include <sound/asoundef.h>
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#include <sound/core.h>
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@ -65,6 +66,11 @@ struct davinci_mcasp_context {
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bool pm_state;
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};
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struct davinci_mcasp_ruledata {
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struct davinci_mcasp *mcasp;
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int serializers;
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};
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struct davinci_mcasp {
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struct snd_dmaengine_dai_dma_data dma_data[2];
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void __iomem *base;
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@ -99,6 +105,8 @@ struct davinci_mcasp {
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#ifdef CONFIG_PM_SLEEP
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struct davinci_mcasp_context context;
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#endif
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struct davinci_mcasp_ruledata ruledata[2];
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};
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static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
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@ -868,6 +876,30 @@ static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
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return 0;
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}
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static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
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unsigned int bclk_freq,
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int *error_ppm)
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{
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int div = mcasp->sysclk_freq / bclk_freq;
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int rem = mcasp->sysclk_freq % bclk_freq;
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if (rem != 0) {
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if (div == 0 ||
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((mcasp->sysclk_freq / div) - bclk_freq) >
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(bclk_freq - (mcasp->sysclk_freq / (div+1)))) {
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div++;
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rem = rem - bclk_freq;
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}
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}
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if (error_ppm)
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*error_ppm =
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(div*1000000 + (int)div64_long(1000000LL*rem,
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(int)bclk_freq))
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/div - 1000000;
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return div;
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}
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static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *cpu_dai)
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@ -883,16 +915,20 @@ static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
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* the machine driver, we need to calculate the ratio.
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*/
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if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
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unsigned int bclk_freq = snd_soc_params_to_bclk(params);
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unsigned int div = mcasp->sysclk_freq / bclk_freq;
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if (mcasp->sysclk_freq % bclk_freq != 0) {
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if (((mcasp->sysclk_freq / div) - bclk_freq) >
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(bclk_freq - (mcasp->sysclk_freq / (div+1))))
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div++;
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dev_warn(mcasp->dev,
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"Inaccurate BCLK: %u Hz / %u != %u Hz\n",
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mcasp->sysclk_freq, div, bclk_freq);
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}
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int channels = params_channels(params);
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int rate = params_rate(params);
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int sbits = params_width(params);
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int ppm, div;
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if (channels > mcasp->tdm_slots)
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channels = mcasp->tdm_slots;
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div = davinci_mcasp_calc_clk_div(mcasp, rate*sbits*channels,
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&ppm);
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if (ppm)
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dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
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ppm);
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__davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0);
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}
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@ -974,6 +1010,120 @@ static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
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return ret;
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}
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static const unsigned int davinci_mcasp_dai_rates[] = {
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8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
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88200, 96000, 176400, 192000,
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};
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#define DAVINCI_MAX_RATE_ERROR_PPM 1000
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static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
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struct snd_pcm_hw_rule *rule)
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{
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struct davinci_mcasp_ruledata *rd = rule->private;
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struct snd_interval *ri =
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hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
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int sbits = params_width(params);
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int channels = params_channels(params);
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unsigned int list[ARRAY_SIZE(davinci_mcasp_dai_rates)];
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int i, count = 0;
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if (channels > rd->mcasp->tdm_slots)
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channels = rd->mcasp->tdm_slots;
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for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
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if (ri->min <= davinci_mcasp_dai_rates[i] &&
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ri->max >= davinci_mcasp_dai_rates[i]) {
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uint bclk_freq = sbits*channels*
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davinci_mcasp_dai_rates[i];
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int ppm;
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davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm);
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if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM)
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list[count++] = davinci_mcasp_dai_rates[i];
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}
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}
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dev_dbg(rd->mcasp->dev,
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"%d frequencies (%d-%d) for %d sbits and %d channels\n",
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count, ri->min, ri->max, sbits, channels);
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return snd_interval_list(hw_param_interval(params, rule->var),
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count, list, 0);
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}
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static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
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struct snd_pcm_hw_rule *rule)
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{
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struct davinci_mcasp_ruledata *rd = rule->private;
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struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
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struct snd_mask nfmt;
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int rate = params_rate(params);
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int channels = params_channels(params);
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int i, count = 0;
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snd_mask_none(&nfmt);
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if (channels > rd->mcasp->tdm_slots)
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channels = rd->mcasp->tdm_slots;
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for (i = 0; i < SNDRV_PCM_FORMAT_LAST; i++) {
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if (snd_mask_test(fmt, i)) {
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uint bclk_freq = snd_pcm_format_width(i)*channels*rate;
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int ppm;
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davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm);
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if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
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snd_mask_set(&nfmt, i);
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count++;
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}
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}
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}
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dev_dbg(rd->mcasp->dev,
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"%d possible sample format for %d Hz and %d channels\n",
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count, rate, channels);
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return snd_mask_refine(fmt, &nfmt);
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}
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static int davinci_mcasp_hw_rule_channels(struct snd_pcm_hw_params *params,
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struct snd_pcm_hw_rule *rule)
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{
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struct davinci_mcasp_ruledata *rd = rule->private;
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struct snd_interval *ci =
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hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
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int sbits = params_width(params);
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int rate = params_rate(params);
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int max_chan_per_wire = rd->mcasp->tdm_slots < ci->max ?
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rd->mcasp->tdm_slots : ci->max;
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unsigned int list[ci->max - ci->min + 1];
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int c1, c, count = 0;
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for (c1 = ci->min; c1 <= max_chan_per_wire; c1++) {
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uint bclk_freq = c1*sbits*rate;
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int ppm;
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davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm);
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if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
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/* If we can use all tdm_slots, we can put any
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amount of channels to remaining wires as
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long as they fit in. */
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if (c1 == rd->mcasp->tdm_slots) {
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for (c = c1; c <= rd->serializers*c1 &&
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c <= ci->max; c++)
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list[count++] = c;
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} else {
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list[count++] = c1;
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}
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}
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}
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dev_dbg(rd->mcasp->dev,
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"%d possible channel counts (%d-%d) for %d Hz and %d sbits\n",
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count, ci->min, ci->max, rate, sbits);
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return snd_interval_list(hw_param_interval(params, rule->var),
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count, list, 0);
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}
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static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *cpu_dai)
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{
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@ -999,6 +1149,7 @@ static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
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if (mcasp->serial_dir[i] == dir)
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max_channels++;
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}
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mcasp->ruledata[dir].serializers = max_channels;
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max_channels *= mcasp->tdm_slots;
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/*
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* If the already active stream has less channels than the calculated
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@ -1013,6 +1164,42 @@ static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
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snd_pcm_hw_constraint_minmax(substream->runtime,
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SNDRV_PCM_HW_PARAM_CHANNELS,
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2, max_channels);
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/*
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* If we rely on implicit BCLK divider setting we should
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* set constraints based on what we can provide.
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*/
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if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
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int ret;
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mcasp->ruledata[dir].mcasp = mcasp;
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ret = snd_pcm_hw_rule_add(substream->runtime, 0,
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SNDRV_PCM_HW_PARAM_RATE,
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davinci_mcasp_hw_rule_rate,
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&mcasp->ruledata[dir],
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SNDRV_PCM_HW_PARAM_FORMAT,
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SNDRV_PCM_HW_PARAM_CHANNELS, -1);
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if (ret)
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return ret;
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ret = snd_pcm_hw_rule_add(substream->runtime, 0,
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SNDRV_PCM_HW_PARAM_FORMAT,
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davinci_mcasp_hw_rule_format,
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&mcasp->ruledata[dir],
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SNDRV_PCM_HW_PARAM_RATE,
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SNDRV_PCM_HW_PARAM_CHANNELS, -1);
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if (ret)
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return ret;
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ret = snd_pcm_hw_rule_add(substream->runtime, 0,
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SNDRV_PCM_HW_PARAM_CHANNELS,
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davinci_mcasp_hw_rule_channels,
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&mcasp->ruledata[dir],
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SNDRV_PCM_HW_PARAM_RATE,
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SNDRV_PCM_HW_PARAM_FORMAT, -1);
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if (ret)
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return ret;
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}
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return 0;
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}
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