x86, microcode, amd: Refactor functions to prepare for early loading
In preparation work for early loading, refactor some common functions that will be shared, and move some struct defines to a common header file. Signed-off-by: Jacob Shin <jacob.shin@amd.com> Link: http://lkml.kernel.org/r/1369940959-2077-4-git-send-email-jacob.shin@amd.com Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com>
This commit is contained in:
Jacob Shin
H. Peter Anvin
Родитель
f2b3ee820a
Коммит
a76096a657
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@ -0,0 +1,64 @@
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#ifndef _ASM_X86_MICROCODE_AMD_H
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#define _ASM_X86_MICROCODE_AMD_H
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#include <asm/microcode.h>
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#define UCODE_MAGIC 0x00414d44
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#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
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#define UCODE_UCODE_TYPE 0x00000001
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#define SECTION_HDR_SIZE 8
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#define CONTAINER_HDR_SZ 12
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struct equiv_cpu_entry {
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u32 installed_cpu;
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u32 fixed_errata_mask;
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u32 fixed_errata_compare;
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u16 equiv_cpu;
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u16 res;
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} __attribute__((packed));
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struct microcode_header_amd {
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u32 data_code;
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u32 patch_id;
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u16 mc_patch_data_id;
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u8 mc_patch_data_len;
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u8 init_flag;
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u32 mc_patch_data_checksum;
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u32 nb_dev_id;
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u32 sb_dev_id;
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u16 processor_rev_id;
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u8 nb_rev_id;
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u8 sb_rev_id;
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u8 bios_api_rev;
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u8 reserved1[3];
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u32 match_reg[8];
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} __attribute__((packed));
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struct microcode_amd {
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struct microcode_header_amd hdr;
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unsigned int mpb[0];
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};
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static inline u16 find_equiv_id(struct equiv_cpu_entry *equiv_cpu_table,
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unsigned int sig)
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{
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int i = 0;
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if (!equiv_cpu_table)
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return 0;
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while (equiv_cpu_table[i].installed_cpu != 0) {
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if (sig == equiv_cpu_table[i].installed_cpu)
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return equiv_cpu_table[i].equiv_cpu;
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i++;
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}
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return 0;
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}
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extern int __apply_microcode_amd(struct microcode_amd *mc_amd);
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extern int apply_microcode_amd(int cpu);
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extern enum ucode_state load_microcode_amd(int cpu, const u8 *data, size_t size);
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#endif /* _ASM_X86_MICROCODE_AMD_H */
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@ -31,48 +31,12 @@
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#include <asm/microcode.h>
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#include <asm/processor.h>
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#include <asm/msr.h>
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#include <asm/microcode_amd.h>
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MODULE_DESCRIPTION("AMD Microcode Update Driver");
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MODULE_AUTHOR("Peter Oruba");
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MODULE_LICENSE("GPL v2");
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#define UCODE_MAGIC 0x00414d44
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#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
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#define UCODE_UCODE_TYPE 0x00000001
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struct equiv_cpu_entry {
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u32 installed_cpu;
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u32 fixed_errata_mask;
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u32 fixed_errata_compare;
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u16 equiv_cpu;
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u16 res;
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} __attribute__((packed));
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struct microcode_header_amd {
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u32 data_code;
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u32 patch_id;
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u16 mc_patch_data_id;
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u8 mc_patch_data_len;
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u8 init_flag;
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u32 mc_patch_data_checksum;
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u32 nb_dev_id;
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u32 sb_dev_id;
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u16 processor_rev_id;
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u8 nb_rev_id;
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u8 sb_rev_id;
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u8 bios_api_rev;
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u8 reserved1[3];
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u32 match_reg[8];
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} __attribute__((packed));
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struct microcode_amd {
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struct microcode_header_amd hdr;
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unsigned int mpb[0];
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};
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#define SECTION_HDR_SIZE 8
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#define CONTAINER_HDR_SZ 12
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static struct equiv_cpu_entry *equiv_cpu_table;
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struct ucode_patch {
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@ -84,21 +48,10 @@ struct ucode_patch {
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static LIST_HEAD(pcache);
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static u16 find_equiv_id(unsigned int cpu)
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static u16 __find_equiv_id(unsigned int cpu)
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{
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struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
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int i = 0;
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if (!equiv_cpu_table)
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return 0;
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while (equiv_cpu_table[i].installed_cpu != 0) {
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if (uci->cpu_sig.sig == equiv_cpu_table[i].installed_cpu)
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return equiv_cpu_table[i].equiv_cpu;
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i++;
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}
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return 0;
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return find_equiv_id(equiv_cpu_table, uci->cpu_sig.sig);
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}
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static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu)
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@ -163,7 +116,7 @@ static struct ucode_patch *find_patch(unsigned int cpu)
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{
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u16 equiv_id;
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equiv_id = find_equiv_id(cpu);
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equiv_id = __find_equiv_id(cpu);
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if (!equiv_id)
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return NULL;
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@ -215,7 +168,21 @@ static unsigned int verify_patch_size(int cpu, u32 patch_size,
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return patch_size;
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}
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static int apply_microcode_amd(int cpu)
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int __apply_microcode_amd(struct microcode_amd *mc_amd)
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{
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u32 rev, dummy;
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wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
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/* verify patch application was successful */
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rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
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if (rev != mc_amd->hdr.patch_id)
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return -1;
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return 0;
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}
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int apply_microcode_amd(int cpu)
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{
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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struct microcode_amd *mc_amd;
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@ -242,19 +209,15 @@ static int apply_microcode_amd(int cpu)
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return 0;
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}
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wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
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/* verify patch application was successful */
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rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
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if (rev != mc_amd->hdr.patch_id) {
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if (__apply_microcode_amd(mc_amd))
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pr_err("CPU%d: update failed for patch_level=0x%08x\n",
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cpu, mc_amd->hdr.patch_id);
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return -1;
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}
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cpu, mc_amd->hdr.patch_id);
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else
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pr_info("CPU%d: new patch_level=0x%08x\n", cpu,
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mc_amd->hdr.patch_id);
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pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
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uci->cpu_sig.rev = rev;
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c->microcode = rev;
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uci->cpu_sig.rev = mc_amd->hdr.patch_id;
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c->microcode = mc_amd->hdr.patch_id;
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return 0;
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}
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@ -364,7 +327,7 @@ static int verify_and_add_patch(unsigned int cpu, u8 *fw, unsigned int leftover)
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return crnt_size;
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}
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static enum ucode_state load_microcode_amd(int cpu, const u8 *data, size_t size)
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static enum ucode_state __load_microcode_amd(int cpu, const u8 *data, size_t size)
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{
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enum ucode_state ret = UCODE_ERROR;
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unsigned int leftover;
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@ -398,6 +361,21 @@ static enum ucode_state load_microcode_amd(int cpu, const u8 *data, size_t size)
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return UCODE_OK;
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}
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enum ucode_state load_microcode_amd(int cpu, const u8 *data, size_t size)
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{
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enum ucode_state ret;
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/* free old equiv table */
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free_equiv_cpu_table();
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ret = __load_microcode_amd(cpu, data, size);
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if (ret != UCODE_OK)
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cleanup();
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return ret;
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}
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/*
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* AMD microcode firmware naming convention, up to family 15h they are in
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* the legacy file:
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@ -440,12 +418,7 @@ static enum ucode_state request_microcode_amd(int cpu, struct device *device,
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goto fw_release;
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}
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/* free old equiv table */
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free_equiv_cpu_table();
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ret = load_microcode_amd(cpu, fw->data, fw->size);
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if (ret != UCODE_OK)
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cleanup();
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fw_release:
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release_firmware(fw);
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