Merge branches 'am35xx_hwmod_data_fixes_a_3.6', 'am35xx_emac_mdio_devel_3.6' and 'am35xx_prcm_data_devel_3.6' into am35xx_devel_3.6
This commit is contained in:
Paul Walmsley
Коммит
a77e1c4d09
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@ -15,27 +15,13 @@
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* General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/davinci_emac.h>
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#include <linux/platform_device.h>
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#include <plat/irqs.h>
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#include <asm/system.h>
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#include <plat/omap_device.h>
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#include <mach/am35xx.h>
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#include "control.h"
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static struct mdio_platform_data am35xx_emac_mdio_pdata;
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static struct resource am35xx_emac_mdio_resources[] = {
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DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET, SZ_4K),
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};
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static struct platform_device am35xx_emac_mdio_device = {
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.name = "davinci_mdio",
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.id = 0,
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.num_resources = ARRAY_SIZE(am35xx_emac_mdio_resources),
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.resource = am35xx_emac_mdio_resources,
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.dev.platform_data = &am35xx_emac_mdio_pdata,
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};
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#include "am35xx-emac.h"
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static void am35xx_enable_emac_int(void)
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{
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@ -69,41 +55,57 @@ static struct emac_platform_data am35xx_emac_pdata = {
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.interrupt_disable = am35xx_disable_emac_int,
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};
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static struct resource am35xx_emac_resources[] = {
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DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE, 0x30000),
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DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RXTHRESH_IRQ),
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DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RX_PULSE_IRQ),
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DEFINE_RES_IRQ(INT_35XX_EMAC_C0_TX_PULSE_IRQ),
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DEFINE_RES_IRQ(INT_35XX_EMAC_C0_MISC_PULSE_IRQ),
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};
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static struct mdio_platform_data am35xx_mdio_pdata;
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static struct platform_device am35xx_emac_device = {
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.name = "davinci_emac",
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.id = -1,
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.num_resources = ARRAY_SIZE(am35xx_emac_resources),
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.resource = am35xx_emac_resources,
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.dev = {
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.platform_data = &am35xx_emac_pdata,
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},
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};
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static int __init omap_davinci_emac_dev_init(struct omap_hwmod *oh,
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void *pdata, int pdata_len)
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{
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struct platform_device *pdev;
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pdev = omap_device_build(oh->class->name, 0, oh, pdata, pdata_len,
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NULL, 0, false);
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if (IS_ERR(pdev)) {
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WARN(1, "Can't build omap_device for %s:%s.\n",
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oh->class->name, oh->name);
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return PTR_ERR(pdev);
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}
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return 0;
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}
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void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
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{
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struct omap_hwmod *oh;
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u32 v;
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int err;
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int ret;
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am35xx_emac_pdata.rmii_en = rmii_en;
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am35xx_emac_mdio_pdata.bus_freq = mdio_bus_freq;
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err = platform_device_register(&am35xx_emac_device);
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if (err) {
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pr_err("AM35x: failed registering EMAC device: %d\n", err);
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oh = omap_hwmod_lookup("davinci_mdio");
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if (!oh) {
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pr_err("Could not find davinci_mdio hwmod\n");
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return;
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}
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err = platform_device_register(&am35xx_emac_mdio_device);
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if (err) {
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pr_err("AM35x: failed registering EMAC MDIO device: %d\n", err);
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platform_device_unregister(&am35xx_emac_device);
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am35xx_mdio_pdata.bus_freq = mdio_bus_freq;
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ret = omap_davinci_emac_dev_init(oh, &am35xx_mdio_pdata,
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sizeof(am35xx_mdio_pdata));
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if (ret) {
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pr_err("Could not build davinci_mdio hwmod device\n");
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return;
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}
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oh = omap_hwmod_lookup("davinci_emac");
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if (!oh) {
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pr_err("Could not find davinci_emac hwmod\n");
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return;
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}
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am35xx_emac_pdata.rmii_en = rmii_en;
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ret = omap_davinci_emac_dev_init(oh, &am35xx_emac_pdata,
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sizeof(am35xx_emac_pdata));
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if (ret) {
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pr_err("Could not build davinci_emac hwmod device\n");
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return;
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}
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@ -3478,7 +3478,7 @@ static struct omap_clk omap3xxx_clks[] = {
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CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
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CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
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CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
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CLK("davinci_emac", NULL, &emac_ick, CK_AM35XX),
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CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX),
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CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX),
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CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
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CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
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@ -59,6 +59,12 @@ static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = {
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{ NULL },
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};
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static struct clkdm_dep gfx_sgx_am35x_wkdeps[] = {
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{ .clkdm_name = "mpu_clkdm" },
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{ .clkdm_name = "wkup_clkdm" },
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{ NULL },
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};
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/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
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static struct clkdm_dep per_wkdeps[] = {
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{ .clkdm_name = "core_l3_clkdm" },
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@ -69,6 +75,14 @@ static struct clkdm_dep per_wkdeps[] = {
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{ NULL },
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};
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static struct clkdm_dep per_am35x_wkdeps[] = {
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{ .clkdm_name = "core_l3_clkdm" },
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{ .clkdm_name = "core_l4_clkdm" },
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{ .clkdm_name = "mpu_clkdm" },
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{ .clkdm_name = "wkup_clkdm" },
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{ NULL },
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};
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/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
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static struct clkdm_dep usbhost_wkdeps[] = {
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{ .clkdm_name = "core_l3_clkdm" },
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@ -79,6 +93,14 @@ static struct clkdm_dep usbhost_wkdeps[] = {
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{ NULL },
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};
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static struct clkdm_dep usbhost_am35x_wkdeps[] = {
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{ .clkdm_name = "core_l3_clkdm" },
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{ .clkdm_name = "core_l4_clkdm" },
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{ .clkdm_name = "mpu_clkdm" },
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{ .clkdm_name = "wkup_clkdm" },
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{ NULL },
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};
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/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
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static struct clkdm_dep mpu_3xxx_wkdeps[] = {
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{ .clkdm_name = "core_l3_clkdm" },
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@ -89,6 +111,14 @@ static struct clkdm_dep mpu_3xxx_wkdeps[] = {
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{ NULL },
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};
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static struct clkdm_dep mpu_am35x_wkdeps[] = {
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{ .clkdm_name = "core_l3_clkdm" },
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{ .clkdm_name = "core_l4_clkdm" },
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{ .clkdm_name = "dss_clkdm" },
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{ .clkdm_name = "per_clkdm" },
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{ NULL },
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};
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/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
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static struct clkdm_dep iva2_wkdeps[] = {
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{ .clkdm_name = "core_l3_clkdm" },
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@ -116,6 +146,12 @@ static struct clkdm_dep dss_wkdeps[] = {
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{ NULL },
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};
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static struct clkdm_dep dss_am35x_wkdeps[] = {
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{ .clkdm_name = "mpu_clkdm" },
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{ .clkdm_name = "wkup_clkdm" },
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{ NULL },
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};
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/* 3430: PM_WKDEP_NEON: MPU */
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static struct clkdm_dep neon_wkdeps[] = {
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{ .clkdm_name = "mpu_clkdm" },
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@ -131,6 +167,11 @@ static struct clkdm_dep dss_sleepdeps[] = {
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{ NULL },
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};
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static struct clkdm_dep dss_am35x_sleepdeps[] = {
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{ .clkdm_name = "mpu_clkdm" },
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{ NULL },
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};
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/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
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static struct clkdm_dep per_sleepdeps[] = {
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{ .clkdm_name = "mpu_clkdm" },
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@ -138,6 +179,11 @@ static struct clkdm_dep per_sleepdeps[] = {
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{ NULL },
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};
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static struct clkdm_dep per_am35x_sleepdeps[] = {
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{ .clkdm_name = "mpu_clkdm" },
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{ NULL },
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};
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/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
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static struct clkdm_dep usbhost_sleepdeps[] = {
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{ .clkdm_name = "mpu_clkdm" },
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@ -145,6 +191,11 @@ static struct clkdm_dep usbhost_sleepdeps[] = {
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{ NULL },
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};
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static struct clkdm_dep usbhost_am35x_sleepdeps[] = {
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{ .clkdm_name = "mpu_clkdm" },
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{ NULL },
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};
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/* 3430: CM_SLEEPDEP_CAM: MPU */
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static struct clkdm_dep cam_sleepdeps[] = {
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{ .clkdm_name = "mpu_clkdm" },
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@ -175,6 +226,15 @@ static struct clockdomain mpu_3xxx_clkdm = {
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
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};
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static struct clockdomain mpu_am35x_clkdm = {
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.name = "mpu_clkdm",
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.pwrdm = { .name = "mpu_pwrdm" },
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.flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
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.dep_bit = OMAP3430_EN_MPU_SHIFT,
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.wkdep_srcs = mpu_am35x_wkdeps,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
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};
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static struct clockdomain neon_clkdm = {
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.name = "neon_clkdm",
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.pwrdm = { .name = "neon_pwrdm" },
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@ -210,6 +270,15 @@ static struct clockdomain sgx_clkdm = {
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.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
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};
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static struct clockdomain sgx_am35x_clkdm = {
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.name = "sgx_clkdm",
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.pwrdm = { .name = "sgx_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.wkdep_srcs = gfx_sgx_am35x_wkdeps,
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.sleepdep_srcs = gfx_sgx_sleepdeps,
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.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
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};
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/*
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* The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
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* then that information was removed from the 34xx ES2+ TRM. It is
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@ -261,6 +330,16 @@ static struct clockdomain dss_3xxx_clkdm = {
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
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};
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static struct clockdomain dss_am35x_clkdm = {
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.name = "dss_clkdm",
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.pwrdm = { .name = "dss_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
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.wkdep_srcs = dss_am35x_wkdeps,
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.sleepdep_srcs = dss_am35x_sleepdeps,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
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};
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static struct clockdomain cam_clkdm = {
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.name = "cam_clkdm",
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.pwrdm = { .name = "cam_pwrdm" },
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@ -279,6 +358,15 @@ static struct clockdomain usbhost_clkdm = {
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.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
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};
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static struct clockdomain usbhost_am35x_clkdm = {
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.name = "usbhost_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.wkdep_srcs = usbhost_am35x_wkdeps,
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.sleepdep_srcs = usbhost_am35x_sleepdeps,
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.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
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};
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static struct clockdomain per_clkdm = {
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.name = "per_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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@ -289,6 +377,16 @@ static struct clockdomain per_clkdm = {
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
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};
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static struct clockdomain per_am35x_clkdm = {
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.name = "per_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.dep_bit = OMAP3430_EN_PER_SHIFT,
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.wkdep_srcs = per_am35x_wkdeps,
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.sleepdep_srcs = per_am35x_sleepdeps,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
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};
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/*
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* Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
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* switched of even if sdti is in use
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@ -341,28 +439,41 @@ static struct clkdm_autodep clkdm_autodeps[] = {
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}
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};
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static struct clkdm_autodep clkdm_am35x_autodeps[] = {
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{
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.clkdm = { .name = "mpu_clkdm" },
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},
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{
|
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.clkdm = { .name = NULL },
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}
|
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};
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/*
|
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*
|
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*/
|
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|
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static struct clockdomain *clockdomains_omap3430_common[] __initdata = {
|
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static struct clockdomain *clockdomains_common[] __initdata = {
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&wkup_common_clkdm,
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&cm_common_clkdm,
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&prm_common_clkdm,
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&mpu_3xxx_clkdm,
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&neon_clkdm,
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&iva2_clkdm,
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&d2d_clkdm,
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&core_l3_3xxx_clkdm,
|
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&core_l4_3xxx_clkdm,
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&emu_clkdm,
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&dpll1_clkdm,
|
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&dpll3_clkdm,
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&dpll4_clkdm,
|
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NULL
|
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};
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|
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static struct clockdomain *clockdomains_omap3430[] __initdata = {
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&mpu_3xxx_clkdm,
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&iva2_clkdm,
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&d2d_clkdm,
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&dss_3xxx_clkdm,
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&cam_clkdm,
|
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&per_clkdm,
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&emu_clkdm,
|
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&dpll1_clkdm,
|
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&dpll2_clkdm,
|
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&dpll3_clkdm,
|
||||
&dpll4_clkdm,
|
||||
NULL
|
||||
};
|
||||
|
||||
|
|
@ -378,21 +489,41 @@ static struct clockdomain *clockdomains_omap3430es2plus[] __initdata = {
|
|||
NULL,
|
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};
|
||||
|
||||
static struct clockdomain *clockdomains_am35x[] __initdata = {
|
||||
&mpu_am35x_clkdm,
|
||||
&sgx_am35x_clkdm,
|
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&dss_am35x_clkdm,
|
||||
&per_am35x_clkdm,
|
||||
&usbhost_am35x_clkdm,
|
||||
&dpll5_clkdm,
|
||||
NULL
|
||||
};
|
||||
|
||||
void __init omap3xxx_clockdomains_init(void)
|
||||
{
|
||||
struct clockdomain **sc;
|
||||
unsigned int rev;
|
||||
|
||||
if (!cpu_is_omap34xx())
|
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return;
|
||||
|
||||
clkdm_register_platform_funcs(&omap3_clkdm_operations);
|
||||
clkdm_register_clkdms(clockdomains_omap3430_common);
|
||||
clkdm_register_clkdms(clockdomains_common);
|
||||
|
||||
sc = (omap_rev() == OMAP3430_REV_ES1_0) ? clockdomains_omap3430es1 :
|
||||
clockdomains_omap3430es2plus;
|
||||
rev = omap_rev();
|
||||
|
||||
clkdm_register_clkdms(sc);
|
||||
if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
|
||||
clkdm_register_clkdms(clockdomains_am35x);
|
||||
clkdm_register_autodeps(clkdm_am35x_autodeps);
|
||||
} else {
|
||||
clkdm_register_clkdms(clockdomains_omap3430);
|
||||
|
||||
sc = (rev == OMAP3430_REV_ES1_0) ?
|
||||
clockdomains_omap3430es1 : clockdomains_omap3430es2plus;
|
||||
|
||||
clkdm_register_clkdms(sc);
|
||||
clkdm_register_autodeps(clkdm_autodeps);
|
||||
}
|
||||
|
||||
clkdm_register_autodeps(clkdm_autodeps);
|
||||
clkdm_complete_init();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -36,6 +36,8 @@
|
|||
#define AM35XX_EMAC_CNTRL_MOD_OFFSET (0x0)
|
||||
#define AM35XX_EMAC_CNTRL_RAM_OFFSET (0x20000)
|
||||
#define AM35XX_EMAC_MDIO_OFFSET (0x30000)
|
||||
#define AM35XX_IPSS_MDIO_BASE (AM35XX_IPSS_EMAC_BASE + \
|
||||
AM35XX_EMAC_MDIO_OFFSET)
|
||||
#define AM35XX_EMAC_CNTRL_RAM_SIZE (0x2000)
|
||||
#define AM35XX_EMAC_RAM_ADDR (AM3517_EMAC_BASE + \
|
||||
AM3517_EMAC_CNTRL_RAM_OFFSET)
|
||||
|
|
|
|||
|
|
@ -3154,6 +3154,107 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
|
|||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* am35xx has Davinci MDIO & EMAC */
|
||||
static struct omap_hwmod_class am35xx_mdio_class = {
|
||||
.name = "davinci_mdio",
|
||||
};
|
||||
|
||||
static struct omap_hwmod am35xx_mdio_hwmod = {
|
||||
.name = "davinci_mdio",
|
||||
.class = &am35xx_mdio_class,
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX Should be connected to an IPSS hwmod, not the L3 directly;
|
||||
* but this will probably require some additional hwmod core support,
|
||||
* so is left as a future to-do item.
|
||||
*/
|
||||
static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
|
||||
.master = &am35xx_mdio_hwmod,
|
||||
.slave = &omap3xxx_l3_main_hwmod,
|
||||
.clk = "emac_fck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
|
||||
{
|
||||
.pa_start = AM35XX_IPSS_MDIO_BASE,
|
||||
.pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> davinci mdio */
|
||||
/*
|
||||
* XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
|
||||
* but this will probably require some additional hwmod core support,
|
||||
* so is left as a future to-do item.
|
||||
*/
|
||||
static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &am35xx_mdio_hwmod,
|
||||
.clk = "emac_fck",
|
||||
.addr = am35xx_mdio_addrs,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
|
||||
{ .name = "rxthresh", .irq = INT_35XX_EMAC_C0_RXTHRESH_IRQ },
|
||||
{ .name = "rx_pulse", .irq = INT_35XX_EMAC_C0_RX_PULSE_IRQ },
|
||||
{ .name = "tx_pulse", .irq = INT_35XX_EMAC_C0_TX_PULSE_IRQ },
|
||||
{ .name = "misc_pulse", .irq = INT_35XX_EMAC_C0_MISC_PULSE_IRQ },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class am35xx_emac_class = {
|
||||
.name = "davinci_emac",
|
||||
};
|
||||
|
||||
static struct omap_hwmod am35xx_emac_hwmod = {
|
||||
.name = "davinci_emac",
|
||||
.mpu_irqs = am35xx_emac_mpu_irqs,
|
||||
.class = &am35xx_emac_class,
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
/* l3_core -> davinci emac interface */
|
||||
/*
|
||||
* XXX Should be connected to an IPSS hwmod, not the L3 directly;
|
||||
* but this will probably require some additional hwmod core support,
|
||||
* so is left as a future to-do item.
|
||||
*/
|
||||
static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
|
||||
.master = &am35xx_emac_hwmod,
|
||||
.slave = &omap3xxx_l3_main_hwmod,
|
||||
.clk = "emac_ick",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
|
||||
{
|
||||
.pa_start = AM35XX_IPSS_EMAC_BASE,
|
||||
.pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> davinci emac */
|
||||
/*
|
||||
* XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
|
||||
* but this will probably require some additional hwmod core support,
|
||||
* so is left as a future to-do item.
|
||||
*/
|
||||
static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &am35xx_emac_hwmod,
|
||||
.clk = "emac_ick",
|
||||
.addr = am35xx_emac_addrs,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
|
||||
&omap3xxx_l3_main__l4_core,
|
||||
&omap3xxx_l3_main__l4_per,
|
||||
|
|
@ -3282,6 +3383,10 @@ static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
|
|||
&omap3xxx_l4_core__usb_tll_hs,
|
||||
&omap3xxx_l4_core__es3plus_mmc1,
|
||||
&omap3xxx_l4_core__es3plus_mmc2,
|
||||
&am35xx_mdio__l3,
|
||||
&am35xx_l4_core__mdio,
|
||||
&am35xx_emac__l3,
|
||||
&am35xx_l4_core__emac,
|
||||
NULL
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -71,6 +71,22 @@ static struct powerdomain mpu_3xxx_pwrdm = {
|
|||
.voltdm = { .name = "mpu_iva" },
|
||||
};
|
||||
|
||||
static struct powerdomain mpu_am35x_pwrdm = {
|
||||
.name = "mpu_pwrdm",
|
||||
.prcm_offs = MPU_MOD,
|
||||
.pwrsts = PWRSTS_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_ON,
|
||||
.flags = PWRDM_HAS_MPU_QUIRK,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_ON,
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON,
|
||||
},
|
||||
.voltdm = { .name = "mpu_iva" },
|
||||
};
|
||||
|
||||
/*
|
||||
* The USBTLL Save-and-Restore mechanism is broken on
|
||||
* 3430s up to ES3.0 and 3630ES1.0. Hence this feature
|
||||
|
|
@ -120,6 +136,23 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = {
|
|||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
static struct powerdomain core_am35x_pwrdm = {
|
||||
.name = "core_pwrdm",
|
||||
.prcm_offs = CORE_MOD,
|
||||
.pwrsts = PWRSTS_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_ON,
|
||||
.banks = 2,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_ON, /* MEM1RETSTATE */
|
||||
[1] = PWRSTS_ON, /* MEM2RETSTATE */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* MEM1ONSTATE */
|
||||
[1] = PWRSTS_ON, /* MEM2ONSTATE */
|
||||
},
|
||||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
static struct powerdomain dss_pwrdm = {
|
||||
.name = "dss_pwrdm",
|
||||
.prcm_offs = OMAP3430_DSS_MOD,
|
||||
|
|
@ -135,6 +168,21 @@ static struct powerdomain dss_pwrdm = {
|
|||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
static struct powerdomain dss_am35x_pwrdm = {
|
||||
.name = "dss_pwrdm",
|
||||
.prcm_offs = OMAP3430_DSS_MOD,
|
||||
.pwrsts = PWRSTS_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_ON, /* MEMRETSTATE */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* MEMONSTATE */
|
||||
},
|
||||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
/*
|
||||
* Although the 34XX TRM Rev K Table 4-371 notes that retention is a
|
||||
* possible SGX powerstate, the SGX device itself does not support
|
||||
|
|
@ -156,6 +204,21 @@ static struct powerdomain sgx_pwrdm = {
|
|||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
static struct powerdomain sgx_am35x_pwrdm = {
|
||||
.name = "sgx_pwrdm",
|
||||
.prcm_offs = OMAP3430ES2_SGX_MOD,
|
||||
.pwrsts = PWRSTS_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_ON, /* MEMRETSTATE */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* MEMONSTATE */
|
||||
},
|
||||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
static struct powerdomain cam_pwrdm = {
|
||||
.name = "cam_pwrdm",
|
||||
.prcm_offs = OMAP3430_CAM_MOD,
|
||||
|
|
@ -186,6 +249,21 @@ static struct powerdomain per_pwrdm = {
|
|||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
static struct powerdomain per_am35x_pwrdm = {
|
||||
.name = "per_pwrdm",
|
||||
.prcm_offs = OMAP3430_PER_MOD,
|
||||
.pwrsts = PWRSTS_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_ON, /* MEMRETSTATE */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* MEMONSTATE */
|
||||
},
|
||||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
static struct powerdomain emu_pwrdm = {
|
||||
.name = "emu_pwrdm",
|
||||
.prcm_offs = OMAP3430_EMU_MOD,
|
||||
|
|
@ -200,6 +278,14 @@ static struct powerdomain neon_pwrdm = {
|
|||
.voltdm = { .name = "mpu_iva" },
|
||||
};
|
||||
|
||||
static struct powerdomain neon_am35x_pwrdm = {
|
||||
.name = "neon_pwrdm",
|
||||
.prcm_offs = OMAP3430_NEON_MOD,
|
||||
.pwrsts = PWRSTS_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_ON,
|
||||
.voltdm = { .name = "mpu_iva" },
|
||||
};
|
||||
|
||||
static struct powerdomain usbhost_pwrdm = {
|
||||
.name = "usbhost_pwrdm",
|
||||
.prcm_offs = OMAP3430ES2_USBHOST_MOD,
|
||||
|
|
@ -293,6 +379,22 @@ static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
|
|||
NULL
|
||||
};
|
||||
|
||||
static struct powerdomain *powerdomains_am35x[] __initdata = {
|
||||
&wkup_omap2_pwrdm,
|
||||
&mpu_am35x_pwrdm,
|
||||
&neon_am35x_pwrdm,
|
||||
&core_am35x_pwrdm,
|
||||
&sgx_am35x_pwrdm,
|
||||
&dss_am35x_pwrdm,
|
||||
&per_am35x_pwrdm,
|
||||
&emu_pwrdm,
|
||||
&dpll1_pwrdm,
|
||||
&dpll3_pwrdm,
|
||||
&dpll4_pwrdm,
|
||||
&dpll5_pwrdm,
|
||||
NULL
|
||||
};
|
||||
|
||||
void __init omap3xxx_powerdomains_init(void)
|
||||
{
|
||||
unsigned int rev;
|
||||
|
|
@ -301,21 +403,34 @@ void __init omap3xxx_powerdomains_init(void)
|
|||
return;
|
||||
|
||||
pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
|
||||
pwrdm_register_pwrdms(powerdomains_omap3430_common);
|
||||
|
||||
rev = omap_rev();
|
||||
|
||||
if (rev == OMAP3430_REV_ES1_0)
|
||||
pwrdm_register_pwrdms(powerdomains_omap3430es1);
|
||||
else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
|
||||
rev == OMAP3430_REV_ES3_0 || rev == OMAP3630_REV_ES1_0)
|
||||
pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
|
||||
else if (rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2 ||
|
||||
rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1 ||
|
||||
rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2)
|
||||
pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
|
||||
else
|
||||
WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
|
||||
if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
|
||||
pwrdm_register_pwrdms(powerdomains_am35x);
|
||||
} else {
|
||||
pwrdm_register_pwrdms(powerdomains_omap3430_common);
|
||||
|
||||
switch (rev) {
|
||||
case OMAP3430_REV_ES1_0:
|
||||
pwrdm_register_pwrdms(powerdomains_omap3430es1);
|
||||
break;
|
||||
case OMAP3430_REV_ES2_0:
|
||||
case OMAP3430_REV_ES2_1:
|
||||
case OMAP3430_REV_ES3_0:
|
||||
case OMAP3630_REV_ES1_0:
|
||||
pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
|
||||
break;
|
||||
case OMAP3430_REV_ES3_1:
|
||||
case OMAP3430_REV_ES3_1_2:
|
||||
case OMAP3630_REV_ES1_1:
|
||||
case OMAP3630_REV_ES1_2:
|
||||
pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
|
||||
break;
|
||||
default:
|
||||
WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
|
||||
}
|
||||
}
|
||||
|
||||
pwrdm_complete_init();
|
||||
}
|
||||
|
|
|
|||
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