net: ipa: move some GSI setup functions
Move gsi_irq_setup() and gsi_ring_setup() so they're defined right above gsi_setup() where they're called. This is a trivial movement of code to prepare for upcoming patches. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Alex Elder
David S. Miller
Родитель
4a4ba483e4
Коммит
a7860a5f89
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@ -198,77 +198,6 @@ static void gsi_irq_type_disable(struct gsi *gsi, enum gsi_irq_type_id type_id)
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gsi_irq_type_update(gsi, gsi->type_enabled_bitmap & ~BIT(type_id));
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}
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/* Turn off all GSI interrupts initially; there is no gsi_irq_teardown() */
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static void gsi_irq_setup(struct gsi *gsi)
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{
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/* Disable all interrupt types */
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gsi_irq_type_update(gsi, 0);
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/* Clear all type-specific interrupt masks */
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iowrite32(0, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET);
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iowrite32(0, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET);
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iowrite32(0, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
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iowrite32(0, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET);
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/* The inter-EE interrupts are not supported for IPA v3.0-v3.1 */
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if (gsi->version > IPA_VERSION_3_1) {
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u32 offset;
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/* These registers are in the non-adjusted address range */
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offset = GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET;
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iowrite32(0, gsi->virt_raw + offset);
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offset = GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET;
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iowrite32(0, gsi->virt_raw + offset);
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}
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iowrite32(0, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET);
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}
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/* Get # supported channel and event rings; there is no gsi_ring_teardown() */
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static int gsi_ring_setup(struct gsi *gsi)
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{
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struct device *dev = gsi->dev;
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u32 count;
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u32 val;
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if (gsi->version < IPA_VERSION_3_5_1) {
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/* No HW_PARAM_2 register prior to IPA v3.5.1, assume the max */
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gsi->channel_count = GSI_CHANNEL_COUNT_MAX;
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gsi->evt_ring_count = GSI_EVT_RING_COUNT_MAX;
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return 0;
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}
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val = ioread32(gsi->virt + GSI_GSI_HW_PARAM_2_OFFSET);
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count = u32_get_bits(val, NUM_CH_PER_EE_FMASK);
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if (!count) {
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dev_err(dev, "GSI reports zero channels supported\n");
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return -EINVAL;
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}
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if (count > GSI_CHANNEL_COUNT_MAX) {
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dev_warn(dev, "limiting to %u channels; hardware supports %u\n",
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GSI_CHANNEL_COUNT_MAX, count);
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count = GSI_CHANNEL_COUNT_MAX;
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}
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gsi->channel_count = count;
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count = u32_get_bits(val, NUM_EV_PER_EE_FMASK);
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if (!count) {
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dev_err(dev, "GSI reports zero event rings supported\n");
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return -EINVAL;
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}
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if (count > GSI_EVT_RING_COUNT_MAX) {
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dev_warn(dev,
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"limiting to %u event rings; hardware supports %u\n",
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GSI_EVT_RING_COUNT_MAX, count);
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count = GSI_EVT_RING_COUNT_MAX;
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}
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gsi->evt_ring_count = count;
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return 0;
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}
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/* Event ring commands are performed one at a time. Their completion
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* is signaled by the event ring control GSI interrupt type, which is
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* only enabled when we issue an event ring command. Only the event
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@ -1878,6 +1807,77 @@ static void gsi_channel_teardown(struct gsi *gsi)
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gsi_irq_disable(gsi);
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}
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/* Turn off all GSI interrupts initially; there is no gsi_irq_teardown() */
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static void gsi_irq_setup(struct gsi *gsi)
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{
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/* Disable all interrupt types */
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gsi_irq_type_update(gsi, 0);
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/* Clear all type-specific interrupt masks */
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iowrite32(0, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET);
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iowrite32(0, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET);
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iowrite32(0, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
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iowrite32(0, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET);
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/* The inter-EE interrupts are not supported for IPA v3.0-v3.1 */
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if (gsi->version > IPA_VERSION_3_1) {
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u32 offset;
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/* These registers are in the non-adjusted address range */
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offset = GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET;
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iowrite32(0, gsi->virt_raw + offset);
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offset = GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET;
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iowrite32(0, gsi->virt_raw + offset);
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}
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iowrite32(0, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET);
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}
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/* Get # supported channel and event rings; there is no gsi_ring_teardown() */
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static int gsi_ring_setup(struct gsi *gsi)
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{
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struct device *dev = gsi->dev;
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u32 count;
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u32 val;
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if (gsi->version < IPA_VERSION_3_5_1) {
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/* No HW_PARAM_2 register prior to IPA v3.5.1, assume the max */
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gsi->channel_count = GSI_CHANNEL_COUNT_MAX;
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gsi->evt_ring_count = GSI_EVT_RING_COUNT_MAX;
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return 0;
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}
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val = ioread32(gsi->virt + GSI_GSI_HW_PARAM_2_OFFSET);
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count = u32_get_bits(val, NUM_CH_PER_EE_FMASK);
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if (!count) {
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dev_err(dev, "GSI reports zero channels supported\n");
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return -EINVAL;
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}
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if (count > GSI_CHANNEL_COUNT_MAX) {
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dev_warn(dev, "limiting to %u channels; hardware supports %u\n",
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GSI_CHANNEL_COUNT_MAX, count);
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count = GSI_CHANNEL_COUNT_MAX;
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}
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gsi->channel_count = count;
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count = u32_get_bits(val, NUM_EV_PER_EE_FMASK);
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if (!count) {
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dev_err(dev, "GSI reports zero event rings supported\n");
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return -EINVAL;
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}
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if (count > GSI_EVT_RING_COUNT_MAX) {
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dev_warn(dev,
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"limiting to %u event rings; hardware supports %u\n",
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GSI_EVT_RING_COUNT_MAX, count);
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count = GSI_EVT_RING_COUNT_MAX;
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}
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gsi->evt_ring_count = count;
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return 0;
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}
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/* Setup function for GSI. GSI firmware must be loaded and initialized */
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int gsi_setup(struct gsi *gsi)
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{
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