cacheinfo and arch_topology updates for v6.4
The cache information can be extracted from either a Device Tree(DT), the PPTT ACPI table, or arch registers (clidr_el1 for arm64). When the DT is used but no cache properties are advertised, the current code doesn't correctly fallback to using arch information. The changes fixes the same and also assuse the that L1 data/instruction caches are private and L2/higher caches are shared when the cache information is missing in DT/ACPI and is derived form clidr_el1/arch registers. Currently the cacheinfo is built from the primary CPU prior to secondary CPUs boot, if the DT/ACPI description contains cache information. However, if not present, it still reverts to the old behavior, which allocates the cacheinfo memory on each secondary CPUs which causes RT kernels to triggers a "BUG: sleeping function called from invalid context". The changes here attempts to enable automatic detection for RT kernels when no DT/ACPI cache information is available, by pre-allocating cacheinfo memory on the primary CPU. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAmQ9bmEACgkQAEG6vDF+ 4pggDhAAo75vFky/U63PV9x4IMvVTkNGIK/DSihvG+s5GsujiSS78f4tSSpLAY1X yWTEYsU+1q03cE8rv0Xmkw+cxLerjOGisvPZCdnKVljUF5TWez6OlwKw5V1QqWk9 faOmWBSb8fH4X0ys73e0SBsF3bzyJB/cORmbOL8OnCE7rGkyMQ0plhYVOBQ3CoV8 KMrw7rnPlc5Aoq/8LgTY+Gojqf82njacCIQPrn1TjS/V0SdobC8xm7ZoepZgG9Q1 MHzBtTmKzGrVxWawxcfTaE89t2rudAafa3noYr4xy+dI8ptSkTQNKCG9pvTxIcFo KXKfBO6+hTWNREf7a4ginKdKcIKDD7Oo2oTnPBYr9O9/2r727c5Wa5FEGsXa4c14 0dN3vFbhwWIDc5sA7eBOCDYycJm6XyTGJ6iPR+fmaWKwgXhIM2WxakeO8aptuwhn sV+XO7IJxSF79GrrAkSN6AtVj6NHvNpzwRx9mBwHkT3ajDGb04P23AOuqoNDt7kh wcz217ng3hG4CDEbOk9JCQqtFhJeSuIWP5T3wofUfYeXy2opQhwzmiOL+NVROuGY h/cwQCcXCEYUohJhln2PvbMS7w0bBNserpetzEFJfc5aLLdocaH3aQ/AFnCXmCdN YPXP6bp0WdbmfcMskVY8vlb/TBlcOzu6+W0qB1dXTWuib7cwm3o= =4hhJ -----END PGP SIGNATURE----- Merge tag 'cacheinfo-updates-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into driver-core-next Sudeep writes: cacheinfo and arch_topology updates for v6.4 The cache information can be extracted from either a Device Tree(DT), the PPTT ACPI table, or arch registers (clidr_el1 for arm64). When the DT is used but no cache properties are advertised, the current code doesn't correctly fallback to using arch information. The changes fixes the same and also assuse the that L1 data/instruction caches are private and L2/higher caches are shared when the cache information is missing in DT/ACPI and is derived form clidr_el1/arch registers. Currently the cacheinfo is built from the primary CPU prior to secondary CPUs boot, if the DT/ACPI description contains cache information. However, if not present, it still reverts to the old behavior, which allocates the cacheinfo memory on each secondary CPUs which causes RT kernels to triggers a "BUG: sleeping function called from invalid context". The changes here attempts to enable automatic detection for RT kernels when no DT/ACPI cache information is available, by pre-allocating cacheinfo memory on the primary CPU. * tag 'cacheinfo-updates-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: cacheinfo: Add use_arch[|_cache]_info field/function arch_topology: Remove early cacheinfo error message if -ENOENT cacheinfo: Check cache properties are present in DT cacheinfo: Check sib_leaf in cache_leaves_are_shared() cacheinfo: Allow early level detection when DT/ACPI info is missing/broken cacheinfo: Add arm64 early level initializer implementation cacheinfo: Add arch specific early level initializer
This commit is contained in:
Greg Kroah-Hartman
Коммит
a7b3a470fd
|
|
@ -38,11 +38,9 @@ static void ci_leaf_init(struct cacheinfo *this_leaf,
|
|||
this_leaf->type = type;
|
||||
}
|
||||
|
||||
int init_cache_level(unsigned int cpu)
|
||||
static void detect_cache_level(unsigned int *level_p, unsigned int *leaves_p)
|
||||
{
|
||||
unsigned int ctype, level, leaves;
|
||||
int fw_level, ret;
|
||||
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
|
||||
|
||||
for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) {
|
||||
ctype = get_cache_type(level);
|
||||
|
|
@ -54,6 +52,27 @@ int init_cache_level(unsigned int cpu)
|
|||
leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1;
|
||||
}
|
||||
|
||||
*level_p = level;
|
||||
*leaves_p = leaves;
|
||||
}
|
||||
|
||||
int early_cache_level(unsigned int cpu)
|
||||
{
|
||||
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
|
||||
|
||||
detect_cache_level(&this_cpu_ci->num_levels, &this_cpu_ci->num_leaves);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int init_cache_level(unsigned int cpu)
|
||||
{
|
||||
unsigned int level, leaves;
|
||||
int fw_level, ret;
|
||||
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
|
||||
|
||||
detect_cache_level(&level, &leaves);
|
||||
|
||||
if (acpi_disabled) {
|
||||
fw_level = of_find_last_cache_level(cpu);
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -835,18 +835,19 @@ void __init init_cpu_topology(void)
|
|||
if (ret) {
|
||||
/*
|
||||
* Discard anything that was parsed if we hit an error so we
|
||||
* don't use partial information.
|
||||
* don't use partial information. But do not return yet to give
|
||||
* arch-specific early cache level detection a chance to run.
|
||||
*/
|
||||
reset_cpu_topology();
|
||||
return;
|
||||
}
|
||||
|
||||
for_each_possible_cpu(cpu) {
|
||||
ret = fetch_cache_info(cpu);
|
||||
if (ret) {
|
||||
if (!ret)
|
||||
continue;
|
||||
else if (ret != -ENOENT)
|
||||
pr_err("Early cacheinfo failed, ret = %d\n", ret);
|
||||
break;
|
||||
}
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -28,6 +28,9 @@ static DEFINE_PER_CPU(struct cpu_cacheinfo, ci_cpu_cacheinfo);
|
|||
#define per_cpu_cacheinfo_idx(cpu, idx) \
|
||||
(per_cpu_cacheinfo(cpu) + (idx))
|
||||
|
||||
/* Set if no cache information is found in DT/ACPI. */
|
||||
static bool use_arch_info;
|
||||
|
||||
struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu)
|
||||
{
|
||||
return ci_cacheinfo(cpu);
|
||||
|
|
@ -38,11 +41,11 @@ static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf,
|
|||
{
|
||||
/*
|
||||
* For non DT/ACPI systems, assume unique level 1 caches,
|
||||
* system-wide shared caches for all other levels. This will be used
|
||||
* only if arch specific code has not populated shared_cpu_map
|
||||
* system-wide shared caches for all other levels.
|
||||
*/
|
||||
if (!(IS_ENABLED(CONFIG_OF) || IS_ENABLED(CONFIG_ACPI)))
|
||||
return !(this_leaf->level == 1);
|
||||
if (!(IS_ENABLED(CONFIG_OF) || IS_ENABLED(CONFIG_ACPI)) ||
|
||||
use_arch_info)
|
||||
return (this_leaf->level != 1) && (sib_leaf->level != 1);
|
||||
|
||||
if ((sib_leaf->attributes & CACHE_ID) &&
|
||||
(this_leaf->attributes & CACHE_ID))
|
||||
|
|
@ -79,6 +82,9 @@ bool last_level_cache_is_shared(unsigned int cpu_x, unsigned int cpu_y)
|
|||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
|
||||
static bool of_check_cache_nodes(struct device_node *np);
|
||||
|
||||
/* OF properties to query for a given cache type */
|
||||
struct cache_type_info {
|
||||
const char *size_prop;
|
||||
|
|
@ -206,6 +212,11 @@ static int cache_setup_of_node(unsigned int cpu)
|
|||
return -ENOENT;
|
||||
}
|
||||
|
||||
if (!of_check_cache_nodes(np)) {
|
||||
of_node_put(np);
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
prev = np;
|
||||
|
||||
while (index < cache_leaves(cpu)) {
|
||||
|
|
@ -230,6 +241,25 @@ static int cache_setup_of_node(unsigned int cpu)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static bool of_check_cache_nodes(struct device_node *np)
|
||||
{
|
||||
struct device_node *next;
|
||||
|
||||
if (of_property_present(np, "cache-size") ||
|
||||
of_property_present(np, "i-cache-size") ||
|
||||
of_property_present(np, "d-cache-size") ||
|
||||
of_property_present(np, "cache-unified"))
|
||||
return true;
|
||||
|
||||
next = of_find_next_cache_node(np);
|
||||
if (next) {
|
||||
of_node_put(next);
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int of_count_cache_leaves(struct device_node *np)
|
||||
{
|
||||
unsigned int leaves = 0;
|
||||
|
|
@ -261,6 +291,11 @@ int init_of_cache_level(unsigned int cpu)
|
|||
struct device_node *prev = NULL;
|
||||
unsigned int levels = 0, leaves, level;
|
||||
|
||||
if (!of_check_cache_nodes(np)) {
|
||||
of_node_put(np);
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
leaves = of_count_cache_leaves(np);
|
||||
if (leaves > 0)
|
||||
levels = 1;
|
||||
|
|
@ -312,6 +347,10 @@ static int cache_setup_properties(unsigned int cpu)
|
|||
else if (!acpi_disabled)
|
||||
ret = cache_setup_acpi(cpu);
|
||||
|
||||
// Assume there is no cache information available in DT/ACPI from now.
|
||||
if (ret && use_arch_cache_info())
|
||||
use_arch_info = true;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -330,7 +369,7 @@ static int cache_shared_cpu_map_setup(unsigned int cpu)
|
|||
* to update the shared cpu_map if the cache attributes were
|
||||
* populated early before all the cpus are brought online
|
||||
*/
|
||||
if (!last_level_cache_is_valid(cpu)) {
|
||||
if (!last_level_cache_is_valid(cpu) && !use_arch_info) {
|
||||
ret = cache_setup_properties(cpu);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
@ -398,6 +437,11 @@ static void free_cache_attributes(unsigned int cpu)
|
|||
cache_shared_cpu_map_remove(cpu);
|
||||
}
|
||||
|
||||
int __weak early_cache_level(unsigned int cpu)
|
||||
{
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
int __weak init_cache_level(unsigned int cpu)
|
||||
{
|
||||
return -ENOENT;
|
||||
|
|
@ -423,32 +467,71 @@ int allocate_cache_info(int cpu)
|
|||
|
||||
int fetch_cache_info(unsigned int cpu)
|
||||
{
|
||||
struct cpu_cacheinfo *this_cpu_ci;
|
||||
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
|
||||
unsigned int levels = 0, split_levels = 0;
|
||||
int ret;
|
||||
|
||||
if (acpi_disabled) {
|
||||
ret = init_of_cache_level(cpu);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
} else {
|
||||
ret = acpi_get_cache_info(cpu, &levels, &split_levels);
|
||||
if (ret < 0)
|
||||
if (!ret) {
|
||||
this_cpu_ci->num_levels = levels;
|
||||
/*
|
||||
* This assumes that:
|
||||
* - there cannot be any split caches (data/instruction)
|
||||
* above a unified cache
|
||||
* - data/instruction caches come by pair
|
||||
*/
|
||||
this_cpu_ci->num_leaves = levels + split_levels;
|
||||
}
|
||||
}
|
||||
|
||||
if (ret || !cache_leaves(cpu)) {
|
||||
ret = early_cache_level(cpu);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
this_cpu_ci = get_cpu_cacheinfo(cpu);
|
||||
this_cpu_ci->num_levels = levels;
|
||||
/*
|
||||
* This assumes that:
|
||||
* - there cannot be any split caches (data/instruction)
|
||||
* above a unified cache
|
||||
* - data/instruction caches come by pair
|
||||
*/
|
||||
this_cpu_ci->num_leaves = levels + split_levels;
|
||||
if (!cache_leaves(cpu))
|
||||
return -ENOENT;
|
||||
|
||||
this_cpu_ci->early_ci_levels = true;
|
||||
}
|
||||
if (!cache_leaves(cpu))
|
||||
|
||||
return allocate_cache_info(cpu);
|
||||
}
|
||||
|
||||
static inline int init_level_allocate_ci(unsigned int cpu)
|
||||
{
|
||||
unsigned int early_leaves = cache_leaves(cpu);
|
||||
|
||||
/* Since early initialization/allocation of the cacheinfo is allowed
|
||||
* via fetch_cache_info() and this also gets called as CPU hotplug
|
||||
* callbacks via cacheinfo_cpu_online, the init/alloc can be skipped
|
||||
* as it will happen only once (the cacheinfo memory is never freed).
|
||||
* Just populate the cacheinfo. However, if the cacheinfo has been
|
||||
* allocated early through the arch-specific early_cache_level() call,
|
||||
* there is a chance the info is wrong (this can happen on arm64). In
|
||||
* that case, call init_cache_level() anyway to give the arch-specific
|
||||
* code a chance to make things right.
|
||||
*/
|
||||
if (per_cpu_cacheinfo(cpu) && !ci_cacheinfo(cpu)->early_ci_levels)
|
||||
return 0;
|
||||
|
||||
if (init_cache_level(cpu) || !cache_leaves(cpu))
|
||||
return -ENOENT;
|
||||
|
||||
/*
|
||||
* Now that we have properly initialized the cache level info, make
|
||||
* sure we don't try to do that again the next time we are called
|
||||
* (e.g. as CPU hotplug callbacks).
|
||||
*/
|
||||
ci_cacheinfo(cpu)->early_ci_levels = false;
|
||||
|
||||
if (cache_leaves(cpu) <= early_leaves)
|
||||
return 0;
|
||||
|
||||
kfree(per_cpu_cacheinfo(cpu));
|
||||
return allocate_cache_info(cpu);
|
||||
}
|
||||
|
||||
|
|
@ -456,23 +539,10 @@ int detect_cache_attributes(unsigned int cpu)
|
|||
{
|
||||
int ret;
|
||||
|
||||
/* Since early initialization/allocation of the cacheinfo is allowed
|
||||
* via fetch_cache_info() and this also gets called as CPU hotplug
|
||||
* callbacks via cacheinfo_cpu_online, the init/alloc can be skipped
|
||||
* as it will happen only once (the cacheinfo memory is never freed).
|
||||
* Just populate the cacheinfo.
|
||||
*/
|
||||
if (per_cpu_cacheinfo(cpu))
|
||||
goto populate_leaves;
|
||||
|
||||
if (init_cache_level(cpu) || !cache_leaves(cpu))
|
||||
return -ENOENT;
|
||||
|
||||
ret = allocate_cache_info(cpu);
|
||||
ret = init_level_allocate_ci(cpu);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
populate_leaves:
|
||||
/*
|
||||
* If LLC is valid the cache leaves were already populated so just go to
|
||||
* update the cpu map.
|
||||
|
|
|
|||
|
|
@ -76,9 +76,11 @@ struct cpu_cacheinfo {
|
|||
unsigned int num_levels;
|
||||
unsigned int num_leaves;
|
||||
bool cpu_map_populated;
|
||||
bool early_ci_levels;
|
||||
};
|
||||
|
||||
struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu);
|
||||
int early_cache_level(unsigned int cpu);
|
||||
int init_cache_level(unsigned int cpu);
|
||||
int init_of_cache_level(unsigned int cpu);
|
||||
int populate_cache_leaves(unsigned int cpu);
|
||||
|
|
@ -129,4 +131,10 @@ static inline int get_cpu_cacheinfo_id(int cpu, int level)
|
|||
return -1;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARM64
|
||||
#define use_arch_cache_info() (true)
|
||||
#else
|
||||
#define use_arch_cache_info() (false)
|
||||
#endif
|
||||
|
||||
#endif /* _LINUX_CACHEINFO_H */
|
||||
|
|
|
|||
Загрузка…
Ссылка в новой задаче