Samsung DeviceTree updates and improvements for v4.6, second round:
1. Split common reboot/poweroff node to separate DTSI. 2. Don't overheat Odroid XU3 by cooling CPU with cpufreq. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJW1VvJAAoJEME3ZuaGi4PX0IoP/24addMWJyve/UVCh28cNV0l gNWhCuVq1bXJIPRNSw+ZOln/XZSjcyuwqU1JNfjz2SsgaaVffPGIioJbKk55qnW7 gUO6vtwO3hxMe1kmAp7cehOep3zSr7YjxvckCmTZVZm/S0skNtsY1YM5M1hqBqi5 yoiozpoUk7LE+4VEYlDhjArwW4qaiQ1PzwD7w+G91zpuRefPiKslWdiOJw0h7BD/ yA0X6rbXC2zjRfKI5kF6dq/bKpWAqweW1FshA4EWG5Tx6jrip2q9qlH5bCl423lc 55mbJYg0YYMBt4I/GQ2oVRnqQulraj2Id2txrXlVbyji9fq7rvJdoMkVjH3CXyod P7s7FqCgLxd/VVZw9n/Yz8XFlMRvhFMBQ/9ZXm2rpJoRcW3IekIXib23h8kX1I5l Dd8PCAwmjCRzWCGIaGh1M7JfGDKTXyCrohK+iu78PCJQd0PYkF79Bzc7Ckcsyj/k P7wzjpwZb83RkSU/VhgpqWxBFICTEyHruLLVCIiTFLyC0CUYOtff9aUYAiWNCQRZ moLTJr7bqMwuDd0kz/poJ8wdQ+FRZEQfnY64Lxy73L6/lHg9tbHw3tDC7OP3RyWX QzR3kKrDQdkUp7O+i8YPmQ+AdfnA1cqqds4RlFm+/m6Rm3/7V6d9I1bLy3hgrYcJ 87Zu00PFeuDrDORDhRCY =P/fL -----END PGP SIGNATURE----- Merge tag 'samsung-dt-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt Merge "ARM: EXYNOS: dts for 4.6, 2nd pull" from Krzysztof Kozlowski: Samsung DeviceTree updates and improvements for v4.6, second round: 1. Split common reboot/poweroff node to separate DTSI. 2. Don't overheat Odroid XU3 by cooling CPU with cpufreq. * tag 'samsung-dt-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: Don't overheat the Odroid XU3-Lite on high load ARM: dts: exynos: Add cooling levels for Exynos5422/5800 CPUs ARM: dts: exynos: Add cooling levels for Exynos5420 CPUs ARM: dts: exynos: Move syscon reboot/poweroff to common dtsi
This commit is contained in:
Arnd Bergmann
Коммит
a7d1357664
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@ -0,0 +1,27 @@
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/*
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* Samsung's Exynos SoC syscon reboot/poweroff nodes common definition.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/ {
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soc {
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compatible = "simple-bus";
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poweroff: syscon-poweroff {
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compatible = "syscon-poweroff";
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regmap = <&pmu_system_controller>;
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offset = <0x330C>; /* PS_HOLD_CONTROL */
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mask = <0x5200>; /* reset value */
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};
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reboot: syscon-reboot {
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compatible = "syscon-reboot";
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regmap = <&pmu_system_controller>;
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offset = <0x0400>; /* SWRESET */
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mask = <0x1>;
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};
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};
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};
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@ -19,6 +19,7 @@
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#include "skeleton.dtsi"
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#include "exynos4-cpu-thermal.dtsi"
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#include "exynos-syscon-restart.dtsi"
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#include <dt-bindings/clock/exynos3250.h>
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/ {
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@ -152,20 +153,6 @@
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interrupt-parent = <&gic>;
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};
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poweroff: syscon-poweroff {
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compatible = "syscon-poweroff";
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regmap = <&pmu_system_controller>;
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offset = <0x330C>; /* PS_HOLD_CONTROL */
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mask = <0x5200>; /* Reset value */
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};
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reboot: syscon-reboot {
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compatible = "syscon-reboot";
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regmap = <&pmu_system_controller>;
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offset = <0x0400>; /* SWRESET */
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mask = <0x1>;
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};
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mipi_phy: video-phy@10020710 {
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compatible = "samsung,s5pv210-mipi-video-phy";
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#phy-cells = <1>;
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@ -22,6 +22,7 @@
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#include <dt-bindings/clock/exynos4.h>
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#include <dt-bindings/clock/exynos-audss-clk.h>
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#include "skeleton.dtsi"
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#include "exynos-syscon-restart.dtsi"
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/ {
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interrupt-parent = <&gic>;
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@ -163,20 +164,6 @@
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interrupt-parent = <&gic>;
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};
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poweroff: syscon-poweroff {
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compatible = "syscon-poweroff";
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regmap = <&pmu_system_controller>;
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offset = <0x330C>; /* PS_HOLD_CONTROL */
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mask = <0x5200>; /* reset value */
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};
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reboot: syscon-reboot {
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compatible = "syscon-reboot";
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regmap = <&pmu_system_controller>;
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offset = <0x0400>; /* SWRESET */
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mask = <0x1>;
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};
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dsi_0: dsi@11C80000 {
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compatible = "samsung,exynos4210-mipi-dsi";
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reg = <0x11C80000 0x10000>;
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@ -14,6 +14,7 @@
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*/
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#include "skeleton.dtsi"
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#include "exynos-syscon-restart.dtsi"
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/ {
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interrupt-parent = <&gic>;
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@ -93,20 +94,6 @@
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status = "disabled";
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};
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poweroff: syscon-poweroff {
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compatible = "syscon-poweroff";
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regmap = <&pmu_system_controller>;
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offset = <0x330C>; /* PS_HOLD_CONTROL */
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mask = <0x5200>; /* reset value */
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};
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reboot: syscon-reboot {
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compatible = "syscon-reboot";
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regmap = <&pmu_system_controller>;
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offset = <0x0400>; /* SWRESET */
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mask = <0x1>;
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};
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fimd: fimd@14400000 {
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compatible = "samsung,exynos5250-fimd";
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interrupt-parent = <&combiner>;
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@ -14,6 +14,7 @@
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*/
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#include "skeleton.dtsi"
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#include "exynos-syscon-restart.dtsi"
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#include <dt-bindings/clock/exynos5410.h>
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/ {
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@ -117,20 +118,6 @@
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reg = <0x10040000 0x5000>;
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};
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poweroff: syscon-poweroff {
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compatible = "syscon-poweroff";
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regmap = <&pmu_system_controller>;
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offset = <0x330C>; /* PS_HOLD_CONTROL */
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mask = <0x5200>; /* reset value */
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};
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reboot: syscon-reboot {
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compatible = "syscon-reboot";
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regmap = <&pmu_system_controller>;
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offset = <0x0400>; /* SWRESET */
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mask = <0x1>;
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};
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mct: mct@101C0000 {
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compatible = "samsung,exynos4210-mct";
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reg = <0x101C0000 0xB00>;
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@ -33,6 +33,9 @@
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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operating-points-v2 = <&cluster_a15_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <11>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu1: cpu@1 {
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@ -42,6 +45,9 @@
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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operating-points-v2 = <&cluster_a15_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <11>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu2: cpu@2 {
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@ -51,6 +57,9 @@
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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operating-points-v2 = <&cluster_a15_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <11>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu3: cpu@3 {
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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operating-points-v2 = <&cluster_a15_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <11>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu4: cpu@100 {
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@ -70,6 +82,9 @@
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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operating-points-v2 = <&cluster_a7_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <7>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu5: cpu@101 {
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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operating-points-v2 = <&cluster_a7_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <7>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu6: cpu@102 {
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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operating-points-v2 = <&cluster_a7_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <7>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu7: cpu@103 {
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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operating-points-v2 = <&cluster_a7_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <7>;
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#cooling-cells = <2>; /* min followed by max */
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};
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};
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};
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@ -16,7 +16,7 @@
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thermal-zones {
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cpu0_thermal: cpu0-thermal {
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thermal-sensors = <&tmu_cpu0 0>;
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polling-delay-passive = <0>;
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polling-delay-passive = <250>;
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polling-delay = <0>;
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trips {
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cpu_alert0: cpu-alert-0 {
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hysteresis = <0>; /* millicelsius */
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type = "critical";
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};
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/*
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* Exyunos542x support only 4 trip-points
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* so for these polling mode is required.
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* Start polling at temperature level of last
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* interrupt-driven trip: cpu_alert2
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*/
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cpu_alert3: cpu-alert-3 {
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temperature = <70000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "passive";
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};
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cpu_alert4: cpu-alert-4 {
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temperature = <85000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "passive";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert2>;
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cooling-device = <&fan0 2 3>;
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};
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/*
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* When reaching cpu_alert3, reduce CPU
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* by 2 steps. On Exynos5422/5800 that would
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* be: 1500 MHz and 1100 MHz.
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*/
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map3 {
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trip = <&cpu_alert3>;
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cooling-device = <&cpu0 0 2>;
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};
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map4 {
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trip = <&cpu_alert3>;
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cooling-device = <&cpu4 0 2>;
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};
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/*
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* When reaching cpu_alert4, reduce CPU
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* further, down to 600 MHz (11 steps for big,
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* 7 steps for LITTLE).
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*/
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map5 {
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trip = <&cpu_alert4>;
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cooling-device = <&cpu0 3 7>;
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};
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map6 {
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trip = <&cpu_alert4>;
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cooling-device = <&cpu4 3 11>;
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};
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};
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};
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};
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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operating-points-v2 = <&cluster_a7_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <11>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu1: cpu@101 {
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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operating-points-v2 = <&cluster_a7_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <11>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu2: cpu@102 {
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@ -50,6 +56,9 @@
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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operating-points-v2 = <&cluster_a7_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <11>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu3: cpu@103 {
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@ -59,6 +68,9 @@
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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operating-points-v2 = <&cluster_a7_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <11>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu4: cpu@0 {
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@ -69,6 +81,9 @@
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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operating-points-v2 = <&cluster_a15_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <15>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu5: cpu@1 {
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@ -78,6 +93,9 @@
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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operating-points-v2 = <&cluster_a15_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <15>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu6: cpu@2 {
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@ -87,6 +105,9 @@
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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operating-points-v2 = <&cluster_a15_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <15>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu7: cpu@3 {
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@ -96,6 +117,9 @@
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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operating-points-v2 = <&cluster_a15_opp_table>;
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cooling-min-level = <0>;
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cooling-max-level = <15>;
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#cooling-cells = <2>; /* min followed by max */
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};
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};
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};
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