k3dma: Add cyclic mode for audio
Currently the k3dma driver doesn't offer the cyclic mode necessary for handling audio. This patch adds it. Cc: Zhangfei Gao <zhangfei.gao@linaro.org> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Vinod Koul <vinod.koul@intel.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Mark Brown <broonie@kernel.org> Cc: Andy Green <andy@warmcat.com> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Andy Green <andy.green@linaro.org> [jstultz: Forward ported to mainline, removed a few bits of logic that didn't seem to have much effect] Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Andy Green
Vinod Koul
Родитель
36387a2b1f
Коммит
a7e08fa6cc
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013 Linaro Ltd.
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* Copyright (c) 2013 - 2015 Linaro Ltd.
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* Copyright (c) 2013 Hisilicon Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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@ -27,23 +27,28 @@
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#define DRIVER_NAME "k3-dma"
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#define DMA_MAX_SIZE 0x1ffc
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#define DMA_CYCLIC_MAX_PERIOD 0x1000
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#define LLI_BLOCK_SIZE (4 * PAGE_SIZE)
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#define INT_STAT 0x00
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#define INT_TC1 0x04
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#define INT_TC2 0x08
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#define INT_ERR1 0x0c
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#define INT_ERR2 0x10
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#define INT_TC1_MASK 0x18
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#define INT_TC2_MASK 0x1c
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#define INT_ERR1_MASK 0x20
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#define INT_ERR2_MASK 0x24
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#define INT_TC1_RAW 0x600
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#define INT_TC2_RAW 0x608
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#define INT_ERR1_RAW 0x610
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#define INT_ERR2_RAW 0x618
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#define CH_PRI 0x688
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#define CH_STAT 0x690
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#define CX_CUR_CNT 0x704
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#define CX_LLI 0x800
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#define CX_CNT 0x810
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#define CX_CNT1 0x80c
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#define CX_CNT0 0x810
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#define CX_SRC 0x814
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#define CX_DST 0x818
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#define CX_CFG 0x81c
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@ -52,6 +57,7 @@
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#define CX_LLI_CHAIN_EN 0x2
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#define CX_CFG_EN 0x1
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#define CX_CFG_NODEIRQ BIT(1)
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#define CX_CFG_MEM2PER (0x1 << 2)
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#define CX_CFG_PER2MEM (0x2 << 2)
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#define CX_CFG_SRCINCR (0x1 << 31)
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@ -84,6 +90,7 @@ struct k3_dma_chan {
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enum dma_transfer_direction dir;
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dma_addr_t dev_addr;
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enum dma_status status;
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bool cyclic;
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};
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struct k3_dma_phy {
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@ -139,6 +146,7 @@ static void k3_dma_terminate_chan(struct k3_dma_phy *phy, struct k3_dma_dev *d)
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val = 0x1 << phy->idx;
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writel_relaxed(val, d->base + INT_TC1_RAW);
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writel_relaxed(val, d->base + INT_TC2_RAW);
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writel_relaxed(val, d->base + INT_ERR1_RAW);
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writel_relaxed(val, d->base + INT_ERR2_RAW);
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}
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@ -146,7 +154,7 @@ static void k3_dma_terminate_chan(struct k3_dma_phy *phy, struct k3_dma_dev *d)
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static void k3_dma_set_desc(struct k3_dma_phy *phy, struct k3_desc_hw *hw)
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{
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writel_relaxed(hw->lli, phy->base + CX_LLI);
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writel_relaxed(hw->count, phy->base + CX_CNT);
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writel_relaxed(hw->count, phy->base + CX_CNT0);
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writel_relaxed(hw->saddr, phy->base + CX_SRC);
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writel_relaxed(hw->daddr, phy->base + CX_DST);
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writel_relaxed(AXI_CFG_DEFAULT, phy->base + AXI_CFG);
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@ -180,11 +188,13 @@ static void k3_dma_enable_dma(struct k3_dma_dev *d, bool on)
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/* unmask irq */
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writel_relaxed(0xffff, d->base + INT_TC1_MASK);
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writel_relaxed(0xffff, d->base + INT_TC2_MASK);
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writel_relaxed(0xffff, d->base + INT_ERR1_MASK);
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writel_relaxed(0xffff, d->base + INT_ERR2_MASK);
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} else {
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/* mask irq */
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writel_relaxed(0x0, d->base + INT_TC1_MASK);
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writel_relaxed(0x0, d->base + INT_TC2_MASK);
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writel_relaxed(0x0, d->base + INT_ERR1_MASK);
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writel_relaxed(0x0, d->base + INT_ERR2_MASK);
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}
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@ -197,19 +207,20 @@ static irqreturn_t k3_dma_int_handler(int irq, void *dev_id)
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struct k3_dma_chan *c;
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u32 stat = readl_relaxed(d->base + INT_STAT);
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u32 tc1 = readl_relaxed(d->base + INT_TC1);
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u32 tc2 = readl_relaxed(d->base + INT_TC2);
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u32 err1 = readl_relaxed(d->base + INT_ERR1);
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u32 err2 = readl_relaxed(d->base + INT_ERR2);
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u32 i, irq_chan = 0;
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while (stat) {
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i = __ffs(stat);
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stat &= (stat - 1);
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if (likely(tc1 & BIT(i))) {
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stat &= ~BIT(i);
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if (likely(tc1 & BIT(i)) || (tc2 & BIT(i))) {
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unsigned long flags;
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p = &d->phy[i];
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c = p->vchan;
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if (c) {
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unsigned long flags;
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if (c && (tc1 & BIT(i))) {
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spin_lock_irqsave(&c->vc.lock, flags);
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vchan_cookie_complete(&p->ds_run->vd);
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WARN_ON_ONCE(p->ds_done);
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@ -217,6 +228,12 @@ static irqreturn_t k3_dma_int_handler(int irq, void *dev_id)
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p->ds_run = NULL;
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spin_unlock_irqrestore(&c->vc.lock, flags);
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}
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if (c && (tc2 & BIT(i))) {
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spin_lock_irqsave(&c->vc.lock, flags);
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if (p->ds_run != NULL)
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vchan_cyclic_callback(&p->ds_run->vd);
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spin_unlock_irqrestore(&c->vc.lock, flags);
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}
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irq_chan |= BIT(i);
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}
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if (unlikely((err1 & BIT(i)) || (err2 & BIT(i))))
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@ -224,6 +241,7 @@ static irqreturn_t k3_dma_int_handler(int irq, void *dev_id)
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}
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writel_relaxed(irq_chan, d->base + INT_TC1_RAW);
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writel_relaxed(irq_chan, d->base + INT_TC2_RAW);
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writel_relaxed(err1, d->base + INT_ERR1_RAW);
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writel_relaxed(err2, d->base + INT_ERR2_RAW);
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@ -359,7 +377,7 @@ static enum dma_status k3_dma_tx_status(struct dma_chan *chan,
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* its total size.
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*/
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vd = vchan_find_desc(&c->vc, cookie);
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if (vd) {
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if (vd && !c->cyclic) {
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bytes = container_of(vd, struct k3_dma_desc_sw, vd)->size;
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} else if ((!p) || (!p->ds_run)) {
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bytes = 0;
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@ -369,7 +387,8 @@ static enum dma_status k3_dma_tx_status(struct dma_chan *chan,
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bytes = k3_dma_get_curr_cnt(d, p);
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clli = k3_dma_get_curr_lli(p);
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index = (clli - ds->desc_hw_lli) / sizeof(struct k3_desc_hw);
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index = ((clli - ds->desc_hw_lli) /
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sizeof(struct k3_desc_hw)) + 1;
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for (; index < ds->desc_num; index++) {
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bytes += ds->desc_hw[index].count;
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/* end of lli */
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@ -410,9 +429,10 @@ static void k3_dma_issue_pending(struct dma_chan *chan)
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static void k3_dma_fill_desc(struct k3_dma_desc_sw *ds, dma_addr_t dst,
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dma_addr_t src, size_t len, u32 num, u32 ccfg)
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{
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if ((num + 1) < ds->desc_num)
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if (num != ds->desc_num - 1)
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ds->desc_hw[num].lli = ds->desc_hw_lli + (num + 1) *
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sizeof(struct k3_desc_hw);
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ds->desc_hw[num].lli |= CX_LLI_CHAIN_EN;
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ds->desc_hw[num].count = len;
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ds->desc_hw[num].saddr = src;
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@ -467,6 +487,7 @@ static struct dma_async_tx_descriptor *k3_dma_prep_memcpy(
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if (!ds)
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return NULL;
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c->cyclic = 0;
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ds->size = len;
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num = 0;
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@ -510,6 +531,8 @@ static struct dma_async_tx_descriptor *k3_dma_prep_slave_sg(
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if (sgl == NULL)
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return NULL;
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c->cyclic = 0;
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for_each_sg(sgl, sg, sglen, i) {
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avail = sg_dma_len(sg);
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if (avail > DMA_MAX_SIZE)
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@ -549,6 +572,73 @@ static struct dma_async_tx_descriptor *k3_dma_prep_slave_sg(
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return vchan_tx_prep(&c->vc, &ds->vd, flags);
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}
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static struct dma_async_tx_descriptor *
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k3_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
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size_t buf_len, size_t period_len,
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enum dma_transfer_direction dir,
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unsigned long flags)
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{
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struct k3_dma_chan *c = to_k3_chan(chan);
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struct k3_dma_desc_sw *ds;
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size_t len, avail, total = 0;
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dma_addr_t addr, src = 0, dst = 0;
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int num = 1, since = 0;
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size_t modulo = DMA_CYCLIC_MAX_PERIOD;
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u32 en_tc2 = 0;
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dev_dbg(chan->device->dev, "%s: buf %p, dst %p, buf len %d, period_len = %d, dir %d\n",
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__func__, (void *)buf_addr, (void *)to_k3_chan(chan)->dev_addr,
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(int)buf_len, (int)period_len, (int)dir);
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avail = buf_len;
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if (avail > modulo)
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num += DIV_ROUND_UP(avail, modulo) - 1;
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ds = k3_dma_alloc_desc_resource(num, chan);
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if (!ds)
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return NULL;
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c->cyclic = 1;
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addr = buf_addr;
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avail = buf_len;
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total = avail;
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num = 0;
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if (period_len < modulo)
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modulo = period_len;
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do {
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len = min_t(size_t, avail, modulo);
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if (dir == DMA_MEM_TO_DEV) {
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src = addr;
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dst = c->dev_addr;
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} else if (dir == DMA_DEV_TO_MEM) {
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src = c->dev_addr;
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dst = addr;
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}
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since += len;
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if (since >= period_len) {
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/* descriptor asks for TC2 interrupt on completion */
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en_tc2 = CX_CFG_NODEIRQ;
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since -= period_len;
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} else
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en_tc2 = 0;
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k3_dma_fill_desc(ds, dst, src, len, num++, c->ccfg | en_tc2);
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addr += len;
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avail -= len;
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} while (avail);
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/* "Cyclic" == end of link points back to start of link */
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ds->desc_hw[num - 1].lli |= ds->desc_hw_lli;
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ds->size = total;
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return vchan_tx_prep(&c->vc, &ds->vd, flags);
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}
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static int k3_dma_config(struct dma_chan *chan,
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struct dma_slave_config *cfg)
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{
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@ -771,11 +861,13 @@ static int k3_dma_probe(struct platform_device *op)
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INIT_LIST_HEAD(&d->slave.channels);
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dma_cap_set(DMA_SLAVE, d->slave.cap_mask);
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dma_cap_set(DMA_MEMCPY, d->slave.cap_mask);
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dma_cap_set(DMA_CYCLIC, d->slave.cap_mask);
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d->slave.dev = &op->dev;
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d->slave.device_free_chan_resources = k3_dma_free_chan_resources;
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d->slave.device_tx_status = k3_dma_tx_status;
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d->slave.device_prep_dma_memcpy = k3_dma_prep_memcpy;
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d->slave.device_prep_slave_sg = k3_dma_prep_slave_sg;
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d->slave.device_prep_dma_cyclic = k3_dma_prep_dma_cyclic;
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d->slave.device_issue_pending = k3_dma_issue_pending;
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d->slave.device_config = k3_dma_config;
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d->slave.device_pause = k3_dma_transfer_pause;
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